ATTINY261A-MU Atmel, ATTINY261A-MU Datasheet - Page 145

• Manufacturer Part Number: ATTINY261A-MU
• Description: NO NEW DESIGNS, USE TINY261A-XU - 20MHZ, QFN/MLF,IND TEMP, G
• Manufacturer: Atmel

8197B–AVR–01/10
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See
15-6. This assures a fixed delay from the trigger event to the start of conversion. In this mode,
the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 15-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode (see
conversion completes, while ADSC remains high.
Figure 15-7. ADC Timing Diagram, Free Running Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
MUX and REFS
Update
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
2
Figure
Conversion
Complete
3
One Conversion
Sample &
Hold
11
4
15-7), a new conversion will be started immediately after the
12
5
6
13
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
2
MUX and REFS
Update
9
3
10
Conversion
Complete
Sample & Hold
11
4
12
13
Sign and MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
Figure
2
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