ATTINY261A-MU Atmel, ATTINY261A-MU Datasheet - Page 154

• Manufacturer Part Number: ATTINY261A-MU
• Description: NO NEW DESIGNS, USE TINY261A-XU - 20MHZ, QFN/MLF,IND TEMP, G
• Manufacturer: Atmel

15.13.2
15.13.2.1
15.13.2.2
15.13.3
154
ATtiny261A/461A/861A
ADCL and ADCH – The ADC Data Register
ADMUX – ADC Multiplexer Selection Register
ADLAR = 0
ADLAR = 1
Table 15-3.
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
Bit
0x05 (0x25)
0x04 (0x24)
Read/Write
Initial Value
Bit
0x05 (0x25)
0x04 (0x24)
Read/Write
Initial Value
Bit
0x07 (0x27)
Read/Write
Initial Value
151.
ADPS2
1
1
1
1
ADC Prescaler Selections (Continued)
REFS1
ADC7
ADC9
ADC1
R/W
15
15
R
R
R
R
–
7
0
0
7
0
0
7
0
REFS0
ADC6
ADC8
ADC0
R/W
14
14
ADPS1
R
R
R
R
–
6
0
0
6
0
0
6
0
0
0
1
1
ADLAR
ADC5
ADC7
R/W
13
13
R
R
R
R
–
5
0
0
–
5
0
0
5
0
ADC4
ADC6
MUX4
R/W
12
12
R
R
R
R
–
4
0
0
–
4
0
0
4
0
ADPS0
0
1
0
1
ADC3
ADC5
MUX3
R/W
11
11
R
R
R
R
3
0
–
3
0
0
–
3
0
0
MUX2
ADC2
ADC4
R/W
10
10
R
R
R
R
–
2
0
0
–
2
0
0
2
0
“ADC Conversion Result” on
MUX1
ADC9
ADC1
ADC3
Division Factor
R/W
R
R
R
R
9
1
0
0
9
–
1
0
0
1
0
128
16
32
64
MUX0
ADC8
ADC0
ADC2
R/W
R
R
R
R
0
0
8
0
0
0
8
–
0
0
0
8197B–AVR–01/10
ADCH
ADCL
ADCH
ADCL
ADMUX