P87C51RB2BBD NXP Semiconductors, P87C51RB2BBD Datasheet - Page 42

• Manufacturer Part Number: P87C51RB2BBD
• Description: MCU 8-Bit 87C 80C51 CISC 16KB EPROM 3.3V/5V 44-Pin LQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of P87C51RB2BBD

• Package: 44LQFP
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 33 MHz
• Ram Size: 512 Byte
• Program Memory Size: 16 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 32
• Interface Type: UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

Philips Semiconductors
HARDWARE WATCHDOG TIMER (ONE-TIME
ENABLED WITH RESET-OUT FOR
P87C51RA2/RB2/RC2/RD2)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, the user must write
01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
When the WDT is enabled, it will increment every machine cycle
while the oscillator is running and there is no way to disable the
WDT except through reset (either hardware reset or WDT overflow
reset). When the WDT overflows, it will drive an output reset HIGH
pulse at the RST-pin (see the note below).
2003 Jan 24
80C51 8-bit microcontroller family
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
100
256 or 768 BYTES
Figure 33. Internal and External Data Memory Address Space with EXTRAM = 0
ERAM
8KB/16KB/32KB/64KB OTP
FF
80
00
INTERNAL RAM
INTERNAL RAM
128 BYTES
128 BYTES
LOWER
UPPER
42
FF
80
00
Using the WDT
To enable the WDT, the user must write 01EH and 0E1H in sequence
to the WDTRST, SFR location 0A6H. When the WDT is enabled, the
user needs to service it by writing 01EH and 0E1H to WDTRST to
avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH) and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the oscillator is
running. This means the user must reset the WDT at least every
16383 machine cycles. To reset the WDT, the user must write 01EH
and 0E1H to WDTRST. WDTRST is a write only register. The WDT
counter cannot be read or written. When the WDT overflows, it will
generate an output RESET pulse at the reset pin (see note below).
The RESET pulse duration is 98 T
12-clock mode), where T
WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT
reset.
FUNCTION
REGISTER
SPECIAL
P87C51RA2/RB2/RC2/RD2
FFFF
OSC
0000
= 1/f
EXTERNAL
MEMORY
OSC
DATA
OSC
. To make the best use of the
(6-clock mode; 196 in
SU01293
Product data