KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 67

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

outputs prior to AC-coupling. Its value could be ranged from 140 to 240 Ω depending on the clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8548E SerDes
reference clock’s differential input amplitude requirement (between 200 and 800 mV differential peak).
For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock
input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. Consult a
clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular
clock driver chip.
Figure 46
It assumes the DC levels of the clock driver are compatible with the MPC8548E SerDes reference clock
input’s DC requirement.
Freescale Semiconductor
LVPECL CLK Driver Chip
Clock Driver
Single-Ended CLK
Clock Driver
Clock Driver
Clock Driver
Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Driver Chip
shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
CLK_Out
CLK_Out
CLK_Out
CLK_Out
CLK_Out
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Figure 46. Single-Ended Connection (Reference Only)
33 Ω
R1
R1
100 Ω Differential PWB Trace
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
R2
R2
R2
R2
50 Ω
100 Ω Differential PWB Trace
10 nF
10 nF
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
50 Ω
50 Ω
50 Ω
50 Ω
High-Speed Serial Interfaces (HSSI)
MPC8548E
SerDes Refer.
CLK Receiver
SerDes Refer.
CLK Receiver
MPC8548E
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