IS43DR16128-3DBLI ISSI, Integrated Silicon Solution Inc, IS43DR16128-3DBLI Datasheet - Page 14

• Manufacturer Part Number: IS43DR16128-3DBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43DR16128-3DBLI

• Lead Free Status / Rohs Status: Supplier Unconfirmed

IS43/46DR16128
AC and DC Logic Input Levels
Single‐ended DC Input Logic Level
Single‐ended AC Input logic level
Note: Refer to Overshoot and Undershoot Specification for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot.
AC Input Test Conditions
Notes:
1.
2.
3.
AC Input Test Signal Waveform
Differential Input AC logic level
Notes:
1.
2.
3.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00B, 3/28/2011
Symbol
VREF
VREF
SLEW
Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for
falling edges as shown in the below figure.
AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
VID(AC) specifies the input differential voltage |VTR ‐VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP
is the complementary input signal (such as CK#, DQS#, LDQS# or UDQS#). The minimum value is equal to V IH(AC) ‐ V IL(AC).
The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates
the voltage at which differential input signals must cross.
Refer to Overshoot and Undershoot Specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot.
VIH(DC)
Symbol
VIL(DC)
VID(AC)
Symbol
VIX(AC)
Symbol
VIH(AC)
VIL(AC)
V
Falling Slew =
SWING(MAX)
Input signal maximum peak to peak swing
AC differential crosspoint voltage
AC input logic HIGH
AC input logic LOW
AC differential input voltage
DC input logic HIGH
DC input logic LOW
Input signal minimum slew rate
Parameter
Parameter
Input reference voltage
ΔTF
V
Parameter
REF
Condition
- V
ΔTF
IL(ac)
max
VSSQ ‐ Vpeak
VREF + 0.250
Min.
VREF + 0.125
Min.
‐ 0.3
0.5*VDDQ‐0.175
VDDQ + Vpeak
VREF ‐ 0.250
Rising Slew =
Min.
0.5
Max.
ΔTR
VDDQ + 0.3 V
0.5 x VDDQ
VREF ‐ 0.125
Value
Max.
1.0
1.0
Units
0.5*VDDQ+0.175
V
V
V
IH(ac)
VDDQ
Max.
V
V
V
V
V
V
V
min - V
ΔTR
DDQ
IH(ac)
IH(dc)
REF
IL(dc)
IL(ac)
SS
max
max
REF
min
min
Units
Units
V
V
V/ns
V
V
Units
V
V
Notes
2, 3
Notes
Notes
1
1
1, 3
2
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