IS43DR16128-3DBLI ISSI, Integrated Silicon Solution Inc, IS43DR16128-3DBLI Datasheet - Page 4

• Manufacturer Part Number: IS43DR16128-3DBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43DR16128-3DBLI

• Lead Free Status / Rohs Status: Supplier Unconfirmed

IS43/46DR16128
Initialization Sequence after Power‐Up Diagram
Programming the Mode Register and Extended Mode Registers
For application flexibility, burst length, burst type, CAS# latency, DLL reset function, write recovery time (WR) are user defined
variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance,
additive CAS latency, ODT (On Die Termination), single‐ended strobe, and OCD (off chip driver impedance adjustment) are also user
defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register
(MR) or Extended Mode Registers EMR[1] and EMR[2] can be altered by re‐executing the MRS or EMRS Commands. Even if the user
chooses to modify only a subset of the MR, EMR[1], or EMR[2] variables, all variables within the addressed register must be
redefined when the MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect memory array contents, which mean re‐initialization including those can be executed at any
time after power‐up without affecting memory array contents.
DDR2 Mode Register (MR) Setting
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS# latency, burst
length, burst sequence, DLL reset, tWR and active power down exit time to make DDR2 SDRAM useful for various applications. The
default value of the mode register is not defined, therefore the mode register must be written after power‐up for proper operation.
The mode register is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2 while controlling the state of address
pins A0 ‐ A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the mode register. The
mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register
contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in
the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ‐ A2
with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is
defined by A3; CAS latency is defined by A4 ‐ A6. The DDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is
used for DLL reset. A7 must be set to LOW for normal MRS operation. Write recovery time tWR is defined by A9 ‐ A11. Refer to the
table for specific codes.
Integrated Silicon Solution, Inc. – www.issi.com –
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Rev. 00B, 3/28/2011