DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 177

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

Bit 2: Automatic RDI Defeat (ARDID) – When 0, the RDI is automatically generated based received DS3 alarms.
When 1, the RDI is inserted from the register bit TRDI.
Bit 1: Transmit Frame Generation Control (TFGC) – When this bit is zero, the Transmit Frame Processor frame
generation is enabled. The DS3 overhead positions in the incoming DS3 payload will be overwritten with the
internally generated DS3 overhead. When this bit is one, the Transmit Frame Processor frame generation is
disabled. The DS3 overhead positions in the incoming DS3 payload will be passed through to error insertion. Note:
Frame generation will still overwrite the P-bits if PBGE = 1. Also, the DS3 overhead periods can still be overwritten
by overhead insertion.
Bit 0: Transmit Alarm Indication Signal (TAIS) –
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 11: Continuous C-bit Parity Error Insertion Enable (CCPEIE) – When 0, single C-bit parity error insertion is
enabled. When 1, continuous C-bit parity error insertion is enabled, and C-bit parity errors will be transmitted
continuously if CPEI is high.
Bit 10: C-bit Parity Error Insertion Enable (CPEI) – When 0, C-bit parity error insertion is disabled. When 1, C-bit
parity error insertion is enabled.
Bit 9: Continuous Far-End Block Error Insertion Enable (CFBEIE) – When 0, single far-end block error
insertion is enabled. When 1, continuous far-end block error insertion is enabled, and far-end block errors will be
transmitted continuously if FBEI is high.
Bit 8: Far-End Block Error Insertion Enable (FBEI) – When 0, far-end block error insertion is disabled. When 1,
far-end block error insertion is enabled.
Bit 6: Continuous P-bit Parity Error Insertion Enable (CPEIE) – When 0, single P-bit parity error insertion is
enabled. When 1, continuous P-bit parity error insertion is enabled, and P-bit parity errors will be transmitted
continuously if PEI is high.
Bit 5: P-bit Parity Error Insertion Enable (PEI) – When 0, P-bit parity error insertion is disabled. When 1, P-bit
parity error insertion is enabled.
Bits 4 to 3: Framing Error Insertion Control (FEIC[1:0]) – These two bits control the framing error event to be
inserted.
Bit 2: Framing Error Insertion Enable (FEI) – When 0, framing error insertion is disabled. When 1, framing error
insertion is enabled.
0 = Transmit Alarm Indication Signal is not inserted
1 = Transmit Alarm Indication Signal is inserted into data stream payload
00 = F-bit error.
01 = M-bit error.
10 = SEF error.
11 = OOMF error.
Reserved
15
--
0
7
0
CPEIE
14
--
0
6
0
T3.TEIR
T3 Transmit Error Insertion Register
(1,3,5,7)1Ah
PEI
13
--
0
5
0
FEIC1
12
--
0
0
4
177
CCPEIE
FEIC0
11
0
3
0
CPEI
FEI
10
0
2
0
CFBEIE
TSEI
9
0
1
0
MEIMS
FBEI
8
0
0
0