DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 6

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

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12
13
10.11 BERT......................................................................................................................................................... 107
10.12 LIU—L
12.1 R
12.2 G
12.3 P
12.4 BERT......................................................................................................................................................... 144
12.5 B3ZS/HDB3 L
12.6 HDLC......................................................................................................................................................... 157
12.7 FEAC C
12.8 T
12.9 DS3/E3 F
13.1 JTAG D
13.2 JTAG TAP C
13.3 JTAG I
10.10.4 Transmit Line Interface ...................................................................................................................... 105
10.10.5 Receive Line Interface ....................................................................................................................... 105
10.10.6 B3ZS/HDB3 Decoder ......................................................................................................................... 105
10.11.1 General Description ........................................................................................................................... 107
10.11.2 Features ............................................................................................................................................. 107
10.11.3 Configuration and Monitoring............................................................................................................. 107
10.11.4 Receive Pattern Detection ................................................................................................................. 108
10.11.5 Transmit Pattern Generation.............................................................................................................. 110
10.12.1 General Description ........................................................................................................................... 111
10.12.2 Features ............................................................................................................................................. 111
10.12.3 Detailed Description ........................................................................................................................... 112
10.12.4 Transmitter ......................................................................................................................................... 112
10.12.5 Receiver ............................................................................................................................................. 113
OVERALL REGISTER MAP
REGISTER MAPS AND DESCRIPTIONS
12.1.1 Global Register Bit Map ..................................................................................................................... 119
12.1.2 HDLC Register Bit Map...................................................................................................................... 122
12.1.3 T3 Register Bit Map ........................................................................................................................... 124
12.1.4 E3 G.751 Register Bit Map ................................................................................................................ 124
12.1.5 E3 G.832 Register Bit Map ................................................................................................................ 125
12.1.6 Clear Channel Register Bit Map ........................................................................................................ 126
12.2.1 Register Bit Descriptions.................................................................................................................... 127
12.3.1 Register Bit Descriptions.................................................................................................................... 134
12.4.1 BERT Register Map ........................................................................................................................... 144
12.4.2 BERT Register Bit Descriptions ......................................................................................................... 144
12.5.1 Transmit Side Line Encoder/Decoder Register Map ......................................................................... 152
12.5.2 Receive Side Line Encoder/Decoder Register Map .......................................................................... 153
12.6.1 HDLC Transmit Side Register Map.................................................................................................... 157
12.6.2 HDLC Receive Side Register Map..................................................................................................... 161
12.7.1 FEAC Transmit Side Register Map.................................................................................................... 165
12.7.2 FEAC Receive Side Register Map..................................................................................................... 167
12.8.1 Trail Trace Transmit Side................................................................................................................... 170
12.8.2 Trail Trace Receive Side Register Map ............................................................................................. 172
12.9.1 Transmit DS3 ..................................................................................................................................... 176
12.9.2 Receive DS3 Register Map................................................................................................................ 178
12.9.3 Transmit G.751 E3 ............................................................................................................................. 187
12.9.4 Receive G.751 E3 Register Map ....................................................................................................... 189
12.9.5 Transmit G.832 E3 Register Map ...................................................................................................... 195
12.9.6 Receive G.832 E3 Register Map ....................................................................................................... 198
12.9.7 Transmit Clear Channel ..................................................................................................................... 207
12.9.8 Receive Clear Channel ...................................................................................................................... 208
JTAG INFORMATION
RAIL
ER
EGISTERS
LOBAL
P
T
ORT
INE
NSTRUCTION
RACE
R
ESCRIPTION
ONTROLLER
EGISTERS
RAMER
C
I
NTERFACE
B
OMMON
............................................................................................................................................... 170
IT
ONTROLLER
INE
M
APS
........................................................................................................................................ 176
E
.................................................................................................................................... 127
.................................................................................................................................... 134
NCODER
.................................................................................................................................... 210
R
................................................................................................................................... 165
.................................................................................................................................. 119
EGISTER AND
U
NIT
S
......................................................................................................................... 111
TATE
/D
ECODER
M
ACHINE
I
NSTRUCTIONS
....................................................................................................... 152
D
ESCRIPTION
6
...................................................................................... 213
............................................................................. 211
116
119
210