DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 84

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

X
the parity bits used for line error monitoring. M
alignment bits. C
value of one. C
of one. C
Block Error (FEBE) bits used for remote path error monitoring. C
(or HDLC) bits. C
value of one. The X-bit, P-bit, M-bit, C-bit, and F-bit positions are overhead bits, and the other bit positions in the
T3 frame are payload bits regardless of how they are marked by TDEN.
10.6.5.2 Transmit C-Bit DS3 Frame Generation
C-bit DS3 frame generation receives the incoming payload data stream, and overwrites all of the overhead bit
locations.
The multiframe alignment bits (M
respectively.
The subframe alignment bits (F
respectively.
The X-bits (X
programmable (automatic, 1, or 0). If the RDI is generated automatically, the X-bits are set to zero when one or
more of the indicated alarm conditions is present, and set to one when all of the indicated alarm conditions are
absent. Automatically setting RDI on LOS, SEF, LOF, or AIS is individually programmable (on or off).
The P-bits (P
payload parity is calculated by performing modulo 2 addition of all of the payload bits after all frame processing has
been completed. P-bit generation is programmable (on or off). The P-bits will be generated if either P-bit generation
is enabled or frame generation is enabled.
The bits C
The bit C
The bits C
The bits C
generated automatically or inserted from a register bit. The FEBE bit source is programmable (automatic or
register). If the FEBE bit is generated automatically, it is zero when at least one C-bit parity error has been detected
during the previous frame.
The bits C
Once all of the DS3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming DS3 signal is passed on to error insertion. Frame generation is programmable
(on or off). Note: P-bit generation may still be performed even if frame generation is disabled.
10.6.5.3 Transmit C-bit DS3 Error Insertion
Error insertion inserts various types of errors into the different DS3 overhead bits. The types of errors that can be
inserted are framing errors, P-bit parity errors, C-bit parity errors, and Far-End Block Error (FEBE) errors.
The framing error insertion mode is programmable (F-bit, M-bit, SEF, or OOMF). An F-bit error is a single subframe
alignment bit (F
error in all the subframe alignment bits in a subframe (F
alignment bit (M
A P-bit parity error is generated by is inverting the value of the P-bits (P
error(s) can be inserted one error at a time, or continuously. The P-bit parity error insertion mode (single or
continuous) is programmable.
A C-bit parity error is generated by is inverting the value of the C
parity error(s) can be inserted one error at a time, or continuously. The C-bit parity error insertion mode (single or
continuous) is programmable.
1
and X
2
13
31
11
31
51
are the Remote Defect Indication (RDI) bits (also referred to as the far-end SEF/AIS bits). P
, C
41
is overwritten with the Far-End Alarm and Control (FEAC) data input from the transmit FEAC controller.
, C
, C
, C
, C
1
32
1
12
32
52
and P
13
XY
, and C
1
42
, C
, and C
, and C
, M
11
and X
) error. An M-bit error is a single multiframe alignment bit (M
is the Far-End Alarm and Control (FEAC) signal. C
61
, and C
is the Application Identification Channel (AIC). C
21
, C
2
, or M
, C
2
) are both overwritten with the calculated payload parity from the previous DS3 frame. The
62
33
2
33
53
22
, and C
) are both overwritten with the Remote Defect Indicator (RDI). The RDI source is
, C
are the C-bit parity bits used for path error monitoring. C
are all overwritten with the calculated payload parity from the previous DS3 frame.
are overwritten with the path maintenance data link input from the HDLC controller.
43
3
) error in two consecutive DS3 frames.
23
are all overwritten with the Far-End Block Error (FEBE) bit. The FEBE bit can be
, C
X1
63
61
, F
are unused, and have a value of one. C
, C
1
X2
, M
, F
62
, C
2
X3
, and M
, and F
63
, C
1
71
, M
, C
X4
3
2
) are overwritten with the values zero, one, and zero (010)
) are overwritten with the values one, zero, zero, and one (1001)
, and M
72
, and C
X1
84
, F
3
73
are the multiframe alignment bits. F
X2
, F
are all overwritten with a one.
51
X3
, C
31
, and F
12
, C
21
52
is reserved for future network use, and has a
, C
, and C
32
1
, and C
and P
22
X4
71
, and C
). An OOMF error is a single multiframe
, C
1
53
, M
2
72
) in a single DS3 frame. P-bit parity
33
are the path maintenance data link
, and C
2
, or M
bits in a single DS3 frame. C-bit
23
41
, C
are unused, and have a value
42
3
73
) error. An SEF error is an
, and C
are unused, and have a
XY
43
are the subframe
are the Far-End
1
and P
2
are