DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 45

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

Figure 8-23. 16-Bit Mode without Byte Swap
Figure 8-24. 16-Bit Mode with Byte Swap
Clearing status latched registers on a read or write access is selectable via the GL.CR1.LSBCRE register bit.
Clearing on read clears all bits in the register, while the clear on write clears only those bits which are written with a
‘1’ when the user writes to the status latched register.
To use the Clear on Read method, the user must only read the status latched register. All bits are set to zero after
the read.
register has cleared.
To use the Clear on Write method, the user must write the register with ones in the bit locations that he desires to
clear.
that he wrote a ‘1.’ See also Section 10.1.5.
A[0]/BSWAP
A[0]/BSWAP
Note: Address 0x2B0 = 0x1234
Note: Address 0x2B0 = 0x1234
Figure 8-26
A[10:1]
D[15:0]
A[10:1]
D[15:0]
RDY
Figure 8-25
RD
WR
RDY
CS
WR
RD
CS
0x2B2 = 0x5678
0x2B2 = 0x5678
Z
Z
shows a read, a write, and then a subsequent read revealing the results of clearing of the bits
shows a read of a status latched register and another read of the same register verifying the
0x2B0
0x3412
0x2B0
0x1234
Z
Z
Z
Z
0x2B2
45
0x7856
0x2B2
0x5678
Z
Z