SC16C852LIB,151 NXP Semiconductors, SC16C852LIB,151 Datasheet - Page 38
![IC UART DUAL W/FIFO 48-LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
SC16C852LIB,151
Manufacturer Part Number
SC16C852LIB,151
Description
IC UART DUAL W/FIFO 48-LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C852LIBS151.pdf
(64 pages)
Specifications of SC16C852LIB,151
Package / Case
48-LQFP
Features
Programmable
Number Of Channels
2, DUART
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
1.8V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
2.5 V
Supply Voltage (min)
1.8 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4208
935283098151
SC16C852LIB-S
935283098151
SC16C852LIB-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C852LIB,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC16C852L
Product data sheet
7.17 Flow Control Trigger Level High (FLWCNTH)
7.18 Flow Control Trigger Level Low (FLWCNTL)
7.19 Clock Prescaler (CLKPRES)
[1]
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control.
bit settings; see
Table 29.
[1]
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control.
bit settings; see
Table 30.
[1]
This register hold values for the clock prescaler.
Table 31.
Bit
7:0
Bit
7:0
Bit
7:4
3:0
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
FLWCNTH[7:0]
FLWCNTL[7:0]
Symbol
Symbol
Symbol
CLKPRES[7:4]
CLKPRES[3:0]
FLWCNTH register bits description
FLWCNTL register bits description
Clock Prescaler register bits description
All information provided in this document is subject to legal disclaimers.
Section
Section
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 4 — 1 February 2011
6.5.
6.5.
This register stores the programmable HIGH threshold level for
This register stores the programmable LOW threshold level for
reserved
Clock Prescaler value. Reset to 0.
Description
hardware and software flow control for 128-byte FIFO mode
Description
hardware and software flow control for 128-byte FIFO mode
Description
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Section
Section
Section
7.3.
7.3.
7.3.
Table 29
Table 30
shows FLWCNTH register
shows FLWCNTL register
SC16C852L
© NXP B.V. 2011. All rights reserved.
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