SC16C650BIA44,512 NXP Semiconductors, SC16C650BIA44,512 Datasheet - Page 9
![IC UART SOT187-2](/photos/6/98/69845/568-44-plcc_sot187-2_sml.jpg)
SC16C650BIA44,512
Manufacturer Part Number
SC16C650BIA44,512
Description
IC UART SOT187-2
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C650BIB48151.pdf
(48 pages)
Specifications of SC16C650BIA44,512
Number Of Channels
1, UART
Fifo's
32 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935274392512
SC16C650BIA44
SC16C650BIA44
SC16C650BIA44
SC16C650BIA44
NXP Semiconductors
SC16C650B_4
Product data sheet
6.1 Internal registers
6.2 FIFO operation
The SC16C650B provides 17 internal registers for monitoring and control. These registers
are shown in
standard 16C550. These registers function as data holding registers (THR/RHR), interrupt
status and control registers (IER/ISR), a FIFO control register (FCR), line status and
control registers (LCR/LSR), modem status and control registers (MCR/MSR),
programmable data rate (clock) control registers (DLL/DLM), and a user accessible
ScratchPad Register (SPR). Beyond the general 16C550 features and capabilities, the
SC16C650B offers an enhanced feature register set (EFR, Xon1/Xoff1, Xon2/Xoff2) that
provides on-board hardware/software flow control. Register functions are more fully
described in the following paragraphs.
Table 3.
[1]
[2]
[3]
The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
bit 0 (FCR[0]). With 16C550 devices, the user can set the receive trigger level, but not the
transmit trigger level. The SC16C650B provides independent trigger levels for both
receiver and transmitter. To remain compatible with SC16C550, the transmit interrupt
trigger level is set to 16 following a reset. It should be noted that the user can set the
transmit trigger levels by writing to the FCR register, but activation will not take place until
EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)
0
0
0
0
1
1
1
1
Baud rate register set (DLL/DLM)
0
0
Enhanced register set (EFR, Xon1, Xoff1, Xon2, Xoff2)
0
1
1
1
1
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, Xon2 and Xoff1, Xoff2 are accessible only when the LCR is set to BFh.
A1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
Internal registers decoding
Table
A0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
3. Twelve registers are similar to those already available in the
Rev. 04 — 14 September 2009
Read mode
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
[2]
UART with 32-byte FIFOs and IrDA encoder/decoder
[3]
Write mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
SC16C650B
[1]
© NXP B.V. 2009. All rights reserved.
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