SC16C754BIBM,157 NXP Semiconductors, SC16C754BIBM,157 Datasheet - Page 24
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SC16C754BIBM,157
Manufacturer Part Number
SC16C754BIBM,157
Description
IC UART QUAD 64BYTE 64LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C754BIB80557.pdf
(51 pages)
Specifications of SC16C754BIBM,157
Number Of Channels
4, QUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935279069157
SC16C754BIBM
SC16C754BIBM
SC16C754BIBM
SC16C754BIBM
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C754BIBM,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC16C754B_4
Product data sheet
7.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels, and selecting the type of DMA signalling.
shows FIFO control register bit settings.
Table 11.
Bit
7:6
5:4
3
2
1
0
Symbol
FCR[7] (MSB),
FCR[6] (LSB)
FCR[5] (MSB),
FCR[4] (LSB)
FCR[3]
FCR[2]
FCR[1]
FCR[0]
FIFO control register bits description
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 04 — 6 October 2008
Description
RX trigger. Sets the trigger level for the RX FIFO.
00 — 8 characters
01 — 16 characters
10 — 56 characters
11 — 60 characters
TX trigger. Sets the trigger level for the TX FIFO.
00 — 8 spaces
01 — 16 spaces
10 — 32 spaces
11 — 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
DMA mode select.
Reset TX FIFO.
Reset RX FIFO.
FIFO enable.
logic 0 = set DMA mode 0
logic 1 = set DMA mode 1
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO
SC16C754B
© NXP B.V. 2008. All rights reserved.
Table 11
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