SC16C2550IB48,151 NXP Semiconductors, SC16C2550IB48,151 Datasheet - Page 25

• Manufacturer Part Number: SC16C2550IB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C2550IB48,151

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 3.5 V ~ 4.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3261; 935270020151; SC16C2550IB48-S

Philips Semiconductors
9397 750 11621
Product data
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C2550 and
the CPU.
Table 18:
Bit
7
6
5
4
3
2
Line Status Register bits description
Symbol
LSR[7]
LSR[6]
LSR[5]
LSR[4]
LSR[3]
LSR[2]
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
Rev. 03 — 19 June 2003
Description
FIFO data error.
THR and TSR empty. This bit is the Transmit Empty indicator. This
bit is set to a logic 1 whenever the transmit holding register and the
transmit shift register are both empty. It is reset to logic 0 whenever
either the THR or TSR contains a data character. In the FIFO
mode, this bit is set to ‘1’ whenever the transmit FIFO and transmit
shift register are both empty.
THR empty. This bit is the Transmit Holding Register Empty
indicator. This bit indicates that the UART is ready to accept a new
character for transmission. In addition, this bit causes the UART to
issue an interrupt to CPU when the THR interrupt enable is set.
The THR bit is set to a logic 1 when a character is transferred from
the transmit holding register into the transmitter shift register. The
bit is reset to a logic 0 concurrently with the loading of the
transmitter holding register by the CPU. In the FIFO mode, this bit
is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
Break interrupt.
Framing error.
Parity error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break
indication is in the current FIFO data. This bit is cleared when
there are no remaining error flags associated with the remaining
data in the FIFO.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0
for one character frame time). In the FIFO mode, only one break
character is loaded into the FIFO.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a
valid stop bit(s). In the FIFO mode, this error is associated with
the character at the top of the FIFO.
Logic 0 = No parity error (normal default condition.
Logic 1 = Parity error. The receive character does not have
correct parity information and is suspect. In the FIFO mode, this
error is associated with the character at the top of the FIFO.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C2550
encoder/decoder
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