TDA8933BTW/N2,118 NXP Semiconductors, TDA8933BTW/N2,118 Datasheet - Page 23

• Manufacturer Part Number: TDA8933BTW/N2,118
• Description: IC AMP AUDIO CLASS D 32HTSSOP
• Manufacturer: NXP Semiconductors
• Type: Class Dr

Specifications of TDA8933BTW/N2,118

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 20.6W x 1 @ 16 Ohm; 10.3W x 2 @ 8 Ohm
• Voltage - Supply: 10 V ~ 36 V, ±5 V ~ 18 V
• Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935285222118

NXP Semiconductors
Table 5:
T
to a capacitor, unless otherwise specified. All voltages are measured with respect to signal ground (pin 7); currents are
positive when flowing into the IC.
[1]
[2]
[3]
11. Application information
UBA2074(A)
Preliminary data sheet
Symbol
I
Chip enable levels
V
V
Synchronisation
V
T
D
F
V
T
nonFAULT(sink)
amb
sync(width), in
sync
sync(width), out
EN(high)
EN(low)
sync(peak), in
sync(peak), out
sync
The zener clamp on pin VDD is only activated for high start-up level (
GLA, GLB, GHA and GHB open.
PWMd is active low: A low level on the PWMd pin corresponds with lamps on. Example: D
each cyle low and the lamps are 20% of the time on, resulting in een light output of 20%.
= 25 °C; V
/F
s(min)
Characteristics
VDC
= 15 V; VDD not connected to VDC; V
Parameter
maximum low output current on
pin nonFAULT
logic high level on pin EN
logic low level on pin EN
amplitude of input pulse on pin
SYNC
input pulse width at SYNC pin
input pulse duty cycle at SYNC
pin
input sync frequency
amplitude of output pulse of pin
SYNC
Output pulse width of SYNC
pin
Figure 20
a high voltage (for instance 400V) and the IC is supplied via a start-up bleeder resistor
and a dV/dt supply. Two lamp are connected, each to another output of the same
transformer. The leakage inductances of this transformer provides the ballast impedances
for the lamp. Inductors L1 and L2 provide current for zero voltage switching during PWM
dimming. An analogue voltage is converted to a PWM signal to provide for the desired
brightness level PWM signal. Synchronisation to a predetermined frequency can also be
achieved, when required. Optional lamp short detection is via the lamp voltage sensing
and D13, D23 and the nonFAULT-pin is indicated.
…continued
shows an example backlighting configuration, where the inverter is supplied by
Rev. 02.0 — February 2007
Conditions
V
load on SYNC pin 4.7kΩ//10pF
load on SYNC pin 4.7kΩ//10pF
nonFAULT
High Voltage Full-bridge control IC for CCFL backlighting
EN
=V
= 1V
VDD
V
; C
VDC
VDD
=V
=100nF; R
VDD
) in disabled and stop mode only.
IREF
PWM
=20% means PMWd is during 20% of
= 33 kΩ and CPWM pin connected
Min
0.75
0.9
2.5
0.3
1
2.5
0.36
UBA2074(A)
Typ
1
2.9
0.44
© NXP B.V. 2007. All rights reserved.
Max
1.5
1.7
5
50
1.1
3.3
0.52
Unit
mA
V
V
V
µs
%
V
µs
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