P28F001BX-T120 Intel Corporation, P28F001BX-T120 Datasheet
P28F001BX-T120
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P28F001BX-T120 Summary of contents
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... Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 1-MBIT (128K x 8) High-Performance Read ...
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Figure 1 28F001BX Block Diagram Symbol Type A –A INPUT ADDRESS INPUTS for memory addresses Addresses are internally latched during write cycle DQ –DQ INPUT DATA INPUTS OUTPUTS Inputs data and commands during memory write ...
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GND Figure 2 DIP Pin Configuration 28F010 A 11 ...
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Figure 4 PLCC Lead Configuration APPLICATIONS The 28F001BX flash ‘boot block’ memory augments the non-volatility in-system electrical erasure and reprogrammability of Intel’s standard flash memory by offering four separately erasable blocks and inte- grating a state machine to ...
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Reprogrammable environments such as the per- sonal computer are ideal applications for the 28F001BX The internal state machine provides SRAM-like timings for program and erasure using the Command and Status Registers The blocking scheme allows BIOS update in the main ...
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PRINCIPLES OF OPERATION The 28F001BX introduces on-chip write automation to manage write and erase functions The write state machine allows for 100% TTL-level control inputs fixed power supplies during erasure and program- ming minimal processor overhead with RAM-like ...
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BUS OPERATION Flash memory reads erases and writes in-system via the local CPU All bus cycles to or from the flash memory conform to standard microprocessor bus cycles Read The 28F001BX has three read modes The memory can be read ...
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The use of RP during system reset is important with automated write erase devices When the sys- tem comes out of reset it expects to read from the flash memory Automated flash memories provide status information when accessed ...
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Table 3 28F001BX Command Definitions Bus Command Cycles Req’d Read Array Reset 1 Intelligent Identifier 3 Read Status Register 2 Clear Status Register 1 Erase Setup Erase Confirm 2 Erase Suspend Erase Resume 2 Program Setup Program 2 NOTES 1 ...
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Table 4 28F001BX Status Register Definitions WSMS ESS WRITE STATE MACHINE STATUS e 1 Ready e 0 Busy ERASE SUSPEND STATUS e 1 Erase Suspended e 0 Erase In Progress ...
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Program Setup Program Commands Programming is executed by a two-write sequence The program Setup command (40H) is written to the Command Register followed by a second write specifying the address and data (latched on the ris- ing edge of WE ...
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BOOT BLOCK PROGRAM AND ERASE The boot block is intended to contain secure code which will minimally bring up a system and control programming and erase of other blocks of the de- vice if needed Therefore additional ‘‘lockout’’ ...
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Bus Command Operation Write Erase Setup Write Erase Read Standby Repeat for subsequent blocks Full status check can be done after each block or after a sequence of blocks Write FFH after the last block erase operation to reset the ...
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Figure 11 28F001BX Erase Suspend Resume Flowchart Programming Equipment For PROM programming equipment that cannot bring RP to high voltage OE provides an alter- nate boot block access mechanism OE sition minimum of 480 ns ...
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Power Supply Decoupling Flash memory power switching characteristics re- quire careful device coupling System designers are interested in 3 supply current issues standby current levels (I ) active current levels (I ) and transient SB CC peaks producted by falling ...
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ABSOLUTE MAXIMUM RATINGS Operating Temperature During Read During Erase Program Operating Temperature During Read During Erase Program Temperature under Bias Temperature under Bias 20 ...
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DC CHARACTERISTICS (Continued 10 Symbol Parameter I V Read Current CCR Programming Current CCP Erase Current CCE CC I ...
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DC CHARACTERISTICS 10 Symbol Parameter I Input Load Current IL I Output Leakage Current Standby Current CCS Deep Power-Down ...
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NOTES 1 All currents are in RMS unless otherwise noted Typical values at V are valid for all product versions (packages and speeds specified with the device deselected If the 28F001BX is read while in Erase Suspend ...
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AC CHARACTERISTICS Read-Only Operations Symbol Parameter t t Read Cycle Time AVAV Address to Output Delay AVQV ACC Output Delay ELQV Output Delay PHQV PWH t ...
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... Sampled not 100% tested 28F001BX-T 28F001BX-B (1) E28F001BX-120 10% N28F001BX-120 P28F001BX-120 Notes Min Max 120 120 3 120 600 PLCC P PDIP T Extended Temperature Refer without impact E28F001BX-150 TE28F001BX-150 N28F001BX-150 Unit TN28F001BX-150 P28F001BX-150 Min Max 150 ns 150 ns 150 ns 600 ...
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Figure 12 AC Waveform for Read Operations 22 ...
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AC CHARACTERISTICS Write Erase Program Operations Symbol Parameter t t Write Cycle Time AVAV High Recovery to WE PHWL PS Going Low Setup to WE Going Low ELWL Pulse ...
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AC CHARACTERISTICS Write Erase Program Operations Versions Symbol Parameter t t Write Cycle Time AVAV High Recovery to WE PHWL Setup to WE ELWL Pulse Width ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Notes Boot Block Erase Time Boot Block Program Time Parameter Block Erase Time Parameter Block Program Time Main Block Erase Time Main Block Program Time Chip Erase Time Chip Program Time NOTES ...
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Figure 13 28F001BX Typical Programming Capability Figure 15 28F001BX Typical Erase Capability 26 290406– 19 Figure 14 28F001BX Typical Programming Time at 12V 290406– 21 Figure 16 28F001BX Typical Erase Time at 12V 290406 –20 290406 –22 ...
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Figure 17 AC Waveform for Write Operations 28F001BX-T 28F001BX-B 27 ...
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Figure 18 Alternate Boot Block Access Method Using OE 28 290406 –15 ...
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AC CHARACTERISTICS FOR CE -CONTROLLED WRITES Symbol Parameter t t Write Cycle Time AVAV High Recovery to CE PHEL PS Going Low Setup to CE Going Low WLEL Pulse ...
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AC CHARACTERISTICS FOR CE -CONTROLLED WRITES Versions Symbol Parameter t t Write Cycle Time AVAV High Recovery to CE PHEL Setup to CE Going Low WLEL ...
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Figure 19 Alternate AC Waveform for Write Operations 28F001BX-T 28F001BX-B 31 ...
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... Layout Planning Using Intel’s Boot Block Flash Memory’’ 294005 ER-20 ‘‘ETOX II Flash Memory Technology’’ 32 32-Lead PLCC 32-Pin PDIP N28F001BX-T70 P28F001BX-T70 N28F001BX-T90 P28F001BX-T90 N28F001BX-T120 P28F001BX-T120 N28F001BX-T150 P28F001BX-T150 N28F001BX-B70 P28F001BX-B70 N28F001BX-B90 P28F001BX-B90 N28F001BX-B120 P28F001BX-B120 N28F001BX-B150 P28F001BX-B150 TN28F001BX-T90 ...
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Revision History Number -004 Removed Preliminary classification Latched address A in Figure 5 16 Updated Boot Block Program and Erase section ‘‘If boot block program or erase is attempted while either the Program Status or Erase ...