STLC5444B1 STMicroelectronics, STLC5444B1 Datasheet
STLC5444B1
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STLC5444B1 Summary of contents
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... A hardware current limiting programmable feature is available. December 1997 STLC5444 QUAD FEEDER POWER SUPPLY DIP24 ORDERING NUMBERS: STLC5444B1 (DIP24) STLC5444FN (PLCC44) DIP24 PIN CONNECTION (Top view INT 3 BGND 4 VCC 5 ...
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STLC5444 PLCC44 PIN CONNECTION (Top view) 6 VBB 7 N.C. 8 BGND 9 N.C. 10 VCC 11 ILIM 12 N.C. 13 N.C. 14 VBB 15 N.C. 16 VBB 17 18 BLOCK DIAGRAM MUX LINE ENABLE REGISTER BUS ADDRESS BUS 0/2 ...
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PIN DESCRIPTION Name PLCC DIP Bit 1 of the tri state I/O data bus NC 2,4,8,10, 7,9 No connection 13,14, 16,18, 20,23, 25,26, 28,34, 37,38, Bit 0 of the tri ...
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STLC5444 FUNCTIONAL DESCRIPTION (continued) DGND - Ground Digital ILIM - Current Limit Programming (Input) ILIM programs the current limit of the Output driv- ers using an external resistor connected between ILIM and VBB. The ILIM pin is 1.25V more posi- ...
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DC CHARACTERISTICS (V = -54V Symbol Parameter V Input Voltage High Level IH V Input Voltage Low Level IL I High Level Output Current OH I Low Level Output Current OL I High Level Input Current IH I ...
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STLC5444 SWITCHING CHARACTERISTICS (V MICROPROCESSOR READ/WRITE TIMING NON MULTIPLEXED MODE (for references see figure 1a and 2b). Symbol Parameter t RD, CS pulse width RLRH t RD, recovery time RHRL T t RD, CS low to data available RLDA t ...
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Figure 1: Microprocessor Read Timing. t AHAL ALE t t ADAL ADAZ AZRL t ADDA RD DATA Notes negative and t CLRL RHRL RLRH AZRL ...
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STLC5444 Figure 1a: Microprocessor Read Timing non multiplexed mode. ALE ASRL t ADDA RD DATA Notes negative and t CLRL RHRL RLRH AZRL RLDA 2 ...
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OPERATIVE DESCRIPTION. Initialization The device is initialized by the RESET pin. In this state the analog drivers are switched off, the Indi- rect Address Register (IAR) is cleared, and the in- ternally latched address A0 is cleared. Power at Output ...
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STLC5444 The LER is used to enable or disable the individ- ual line drivers. The line drivers will only become active if the corresponding bit in the TOR is inac- tive. The LER is a read/write register. The MPI is ...
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The contents and format of the status groups and the LER are as follows : LVD: Bit The Low Voltage Detector (LVD) indicates the voltage level on the output lines, even when the lines are disabled. ...
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... guaranteed by characterization and periodic sampling of production units. ORDERING TYPES: STLC5444B1, PDIP24 package Temperature range. STLC5444FN, PLCC44 package Temperature range. STLC5444B1-X, PDIP24 package: - Temperature range. STLC5444FN-X, PLCC44 package: - Temperature range. APPLICATION HINT In the Absolute Maximum Ratings table it is speci- fied that the voltage applied on the -V should never exceed by more than 0 ...
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COUNTER FEEDING It is possible that, in some applications, a commu- nication channel that the STLC5444 feeds, is also biased at the other end by another feeding de- vice. Figure 3: Typical PABX connection. U STLC5444 D95TL229 ...
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STLC5444 NOTE Possible effect on the device of a Vbat variation Be aware that a variation of Vbat during operation, when the switches are on can cause anomalous be- haviour. To avoid that a turn-off occurs the variation should have ...
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DIP24 PACKAGE MECHANICAL DATA DIM. MIN. TYP. a1 0.63 b 0.45 b1 0. 15.2 e 2.54 e3 27. 4.445 L mm MAX. MIN. 0.31 0.009 32.2 16.68 0.598 14.1 3.3 STLC5444 inch TYP. MAX. ...
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STLC5444 PLCC44 PACKAGE MECHANICAL DATA DIM. MIN. TYP. A 17.4 B 16.51 C 3.65 D 4.2 d1 2.59 d2 0.68 E 14.99 e 1.27 e3 12.7 F 0. 1.16 M1 1.14 16/17 mm MAX. MIN. 17.65 ...
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ESD - The SGS-THOMSON Internal Quality Standards set a target that each pin of the devic e should withstand in a series of tests based on the Human Body Model (MIL-STD 883 Method 3015): with C = ...