P82C42PC Intel Corporation, P82C42PC Datasheet

no-image

P82C42PC

Manufacturer Part Number
P82C42PC
Description
Universal peripheral interface CHMOS 8-bit slave microcontroller.
Manufacturer
Intel Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P82C42PC
Manufacturer:
INTEL
Quantity:
5 530
Part Number:
P82C42PC
Manufacturer:
INTEL
Quantity:
6 250
Part Number:
P82C42PC
Manufacturer:
FSC
Quantity:
6 218
Y
Y
Y
Y
Y
Y
Y
Y
The UPI-C42 is an enhanced CHMOS version of the industry standard Intel UPI-42 family It is fabricated on
Intel’s CHMOS III-E process The UPI-C42 is pin software and architecturally compatible with the NMOS UPI
family The UPI-C42 has all of the same features of the NMOS family plus a larger user programmable memory
array (4K) hardware A20 gate support and lower power consumption inherent to a CHMOS product
The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low
voltage 3 3V operation
The UPI-C42 is essentially a ‘‘slave’’ microcontroller or a microcontroller with a slave interface included on the
chip Interface registers are included to enable the UPI device to function as a slave peripheral controller in the
MCS Modules and iAPX family as well as other 8- 16- and 32-bit systems
To allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM
(OTP)
Pin Software and Architecturally
Compatible with all UPI-41 and UPI-42
Products
Low Voltage Operation with the UPI-
L42
Hardware A20 Gate Support
Suspend Power Down Mode
Security Bit Code Protection Support
8-Bit CPU plus ROM OTP EPROM RAM
I O Timer Counter and Clock in a
Single Package
4096 x 8 ROM OTP 256 x 8 RAM 8-Bit
Timer Counter 18 Programmable I O
Pins
DMA Interrupt or Polled Operation
Supported
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
Other brands and names are the property of their respective owners
Figure 1 DIP Pin
Configuration
Full 3 3V Support
CHMOS 8-BIT SLAVE MICROCONTROLLER
290414 – 1
INTEL CORPORATION 1996
UNIVERSAL PERIPHERAL INTERFACE
Figure 2 PLCC Pin Configuration
UPI-C42 UPI-L42
December 1995
290414 –2
Y
Y
Y
Y
Y
Y
Y
Y
One 8-Bit Status and Two Data
Registers for Asynchronous Slave-to-
Master Interface
Fully Compatible with all Intel and Most
Other Microprocessor Families
Interchangeable ROM and OTP EPROM
Versions
Expandable I O
Sync Mode Available
Over 90 Instructions 70% Single Byte
Quick Pulse Programming Algorithm
Available in 40-Lead Plastic 44-Lead
Plastic Leaded Chip Carrier and
44-Lead Quad Flat Pack Packages
(See Packaging Spec Order
and S)
Fast OTP Programming
Figure 3 QFP Pin Configuration
240800 Package Type P N
Order Number 290414-003
290414 – 3

P82C42PC Summary of contents

Page 1

... Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1996 UPI-C42 UPI-L42 One 8-Bit Status and Two Data ...

Page 2

UPI-C42 UPI-L42 DIP PLCC QFP Symbol Pin Pin Pin Type TEST TEST XTAL XTAL RESET ...

Page 3

Table 1 Pin Description (Continued) DIP PLCC QFP Symbol Pin Pin Pin –P 21– 24 24–27 39– 35– 38 39–42 11 13– 15 PROG ...

Page 4

UPI-C42 UPI-L42 UPI-C42 L42 PRODUCT SELECTION GUIDE UPI-C42 Low power CHMOS version of the UPI-42 Device Package ROM 80C42 82C42PC 82C42PD 82C42PE 87C42 UPI-L42 ...

Page 5

UPI-42 COMPATIBLE FEATURES 1 Two Data Bus Buffers one for input and one for output This allows a much cleaner Master Slave protocol 2 8 Bits of Status IBF OBF ...

Page 6

UPI-C42 UPI-L42 If ‘‘EN DMA’’ has been executed P the DACK (DMA ACKnowledge) pin This pin acts as a chip select input for the Data Bus Buffer registers during DMA transfers EN DMA Op Code 0E5H ...

Page 7

This feature is enabled by the A20EN instruction and remains enabled until the de- vice is reset It is important to note that the execu- tion of the A20EN instruction redefines Port 2 ...

Page 8

UPI-C42 UPI-L42 Table 2 covers all suspend mode pin states In addi- tion to the suspend power down mode the UPI-C42 will also support the NMOS power down mode as outlined in Chapter 4 of the UPI-42AH users manual Table ...

Page 9

This circuitry gives the host direct control of port 2 bit 1 (P2 1) without intervention by the internal CPU When this opcode is executed P2 1 becomes a ded- icated output pin The status of this pin is read-able ...

Page 10

UPI-C42 UPI-L42 Figure 6 Quick-Pulse Programming Algorithm Quick-Pulse Programming Algorithm As previously stated the UPI-C42 will be pro- grammed using the Quick-Pulse Programming Algo- rithm developed by Intel to substantially reduce the thorughput time in production programming The Quick-Pulse Programming ...

Page 11

Apply access code to appropriate inputs to put the device into security mode c Apply high voltage to EA and Follow the programming procedure as per the Quick-Pulse Programming Algorithm with known data on the databus ...

Page 12

UPI-C42 UPI-L42 Test Code Checksum Intel Signature User Signature Test Signature Security Byte UPI-C42 Intel Signature User Defined UPI-C42 OTP EPROM Space ACCESS CODE The following table summarizes the access codes required to invoke the Sync Mode Signature Mode and ...

Page 13

SYNC MODE TIMING DIAGRAMS Minimum Specifications SYNC Operation Time XTAL 2 Clock cycles Reset Time t e SYNC NOTE The rising and falling edges of T0 should occur during low state of XTAL 2 clock APPLICATIONS Figure ...

Page 14

UPI-C42 UPI-L42 APPLICATIONS (Continued) Figure 9 8048H-UPI-C42 Interface Figure 10 UPI-C42-8243 Keyboard Scanner Figure 11 UPI-C42 80-Column Matrix Printer Interface 14 290414 –10 290414 –11 290414 –13 ...

Page 15

ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground b Power Dissipation DC CHARACTERISTICS Symbol Parameter V Input Low Voltage IL V Input High Voltage ...

Page 16

UPI-C42 UPI-L42 DC CHARACTERISTICS Symbol Parameter I I Total Supply Current Active Mode 12 5 MHz Suspend Mode I Standby Power ...

Page 17

AC CHARACTERISTICS NOTE All AC Characteristics apply to both the UPI-C42 and UPI-L42 DBB READ Symbol Parameter Setup ...

Page 18

UPI-C42 UPI-L42 AC CHARACTERISTICS CLOCK Symbol t UPI-C42 UPI-L42 CY t UPI-C42 UPI-L42 CYC t PWH t PWL NOTE 1 t ...

Page 19

AC CHARACTERISTICS PROGRAMMING (UPI-C42 AND UPI-L42 25V 0 25V (87C42 87L42 ONLY) Symbol Parameter t Address Setup Time to RESET AW t Address Hold Time after ...

Page 20

UPI-C42 UPI-L42 DRIVING FROM AN EXTERNAL SOURCE NOTE See XTAL1 Configuration Table LC OSCILLATOR MODE L C NOMINAL MHz 120 MHz Each C Should be Approximately 20 pF including ...

Page 21

WAVEFORMS READ OPERATION DATA BUS BUFFER REGISTER WRITE OPERATION DATA BUS BUFFER REGISTER CLOCK TIMING UPI-C42 UPI-L42 290414 –22 290414 –23 290414 –24 21 ...

Page 22

UPI-C42 UPI-L42 WAVEFORMS (Continued) COMBINATION PROGRAM VERIFY MODE NOTES 1 A must be held low (0V) during program verify modes 0 2 For and V IH IH1 IL IL1 DDH DDL 3 When programming the ...

Page 23

WAVEFORMS (Continued) DMA PORT 2 PORT TIMING DURING EXTERNAL ACCESS (EA) On the Rising Edge of SYNC and EA is Enabled Port Data is Valid and can be Strobed On the Trailing Edge of Sync the Program Counter Contents are ...

Page 24

UPI-C42 UPI-L42 Mnemonic Description Bytes ACCUMULATOR ADD A Rr Add register to A ADD A Rr Add data memory to A ADD A data Add immediate to A ADDC A Rr Add register to A with carry ADDC A Rr ...

Page 25

Table 4 UPI Instruction Set (Continued) Mnemonic Description Bytes CONTROL (Continued) SUSPEND Invoke Suspend Power- down mode NOP No Operation REGISTERS INC Rr Increment register INC Rr Increment data memory DEC Rr Decrement register SUBROUTINE CALL addr Jump to subroutine ...

Related keywords