ISPLSI1048C-70LQ Lattice Semiconductor Corp., ISPLSI1048C-70LQ Datasheet
ISPLSI1048C-70LQ
Specifications of ISPLSI1048C-70LQ
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ISPLSI1048C-70LQ Summary of contents
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... Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 1048C Functional Block Diagram I/O I/O I/O I/O I RESET GOE0 Generic Output Routing Pool (ORP) GOE1 Logic Blocks (GLBs I I ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure 2) Test Condition R1 A ...
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External Timing Parameters 4 2 TEST PARAMETER # DESCRIPTION COND. t pd1 A 1 Data Propagation Delay, 4PT bypass, ORP bypass t 2 Data Propagation Delay A pd2 Clock Frequency with Internal Feedback max (Int.) f – ...
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Internal Timing Parameters 2 PARAMETER DESCRIPTION # Inputs t 24 I/O Register Bypass iobp t 25 I/O Latch Delay iolat t 26 I/O Register Setup Time before Clock iosu t 27 I/O Register Hold Time after Clock ioh t 28 ...
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Internal Timing Parameters 2 PARAMETER DESCRIPTION # Outputs Output Buffer Delay t oen 51 I/O Cell OE to Output Enabled t odis 52 I/O Cell OE to Output Disabled t goe 53 Global OE Clocks t gy0 ...
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Timing Model I/O Cell Ded. In #30 I/O Reg Bypass GRP 4 I/O Pin #24 (Input) GRP Input Register Loading D Q Delay RST #31, 33, #59 # 34, 35 Reset Clock Distribution Y1,2,3 #55, 56, ...
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Maximum GRP Delay vs GLB Loads Power Consumption Power consumption in the ispLSI 1048C device depends on two primary factors: the speed at which the device is operating, and the ...
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Pin Description PQFP PIN NUMBERS NAME I I/O 5 21, 22, 23, 24, 25 I/O 11 27, 28, 29, 30, 31 I/O 17 34, 35, 36, 37, 38, 39 I/O ...
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Pin Description NAME CPGA PIN NUMBERS I I/O 5 J2, J3, K1, I I/O 11 L2, K3, N1, I I/O 17 M3, P2, N3, I I/O 23 P4, M5, N5, I/O 24 ...
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Pin Configuration ispLSI 1048C 128-Pin PQFP Pinout Diagram GND ...
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Pin Configuration ispLSI 1048C 133-Pin CPGA Pinout Diagram I/O59 I/O61 I/O64 I/O66 I/O69 I/O56 GND I/O62 I/O65 I/O68 I/O53 I/O60 I/O63 I/O67 I/O57 I/O58 I/O51 I/O54 I/O50 I/O52 I/O55 IN6 I/O48 I/O49 Y1 Vcc Vcc ...
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Part Number Description ispLSI Device Family Device Number Speed MHz max MHz max Ordering Information f Family max (MHz) ispLSI f Family max (MHz) ispLSI f t Family max (MHz) pd (ns) ...