HY57V161610D Hynix Semiconductor, HY57V161610D Datasheet
HY57V161610D
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HY57V161610D Summary of contents
Page 1
... HY57V161610D is organized as 2banks of 524,288x16. HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL ...
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... RAS, CAS and WE define the operation. Refer function truth table for details DQM control output buffer in read mode and mask input data in write mode Multiplexed data input / output pin Power supply for internal circuit and input buffer Power supply for DQ No connection HY57V161610D ...
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... UDQM LDQM Mode Register Rev. 4.0/Aug. 02 Refresh Counter Sense AMP & I/O gates Address Register Overflow Burst Length Counter Sense AMP & I/O gates HY57V161610D 512Kx16 Bank 0 Column Decoder Column Addr. Latch & Counter Column Decoder 512Kx16 Bank 1 Test Mode I/O Control DQ0 DQ1 ...
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... Output load capacitance for access time measurement Note : 1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF). For details, refer to AC/DC output load circuit (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns (min) of HY57V161610DTC-5/55 is 3.15V‘ DD Rev ...
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... Input leakage current IL Output leakage current IO Output high voltage V OH Output low voltage V OL Note : 1.V (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610DTC-5/55 is 3.15V DD 3 3.6V, All other pins are not under test = 0V IN 4.D is disabled 3.6V OUT OUT Rev ...
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... Auto Refresh Current IDD5 tRRC t tRRC(min), All banks active Self Refresh Current IDD6 CKE Note : 1.V (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610DTC-5/55 is 3.15V DD 3.I and I depend on output loading and cycle rates. Specified values are measured with the output open. ...
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... CLK to data output in low Z- tOLZ time CLK to data output in high tOHZ Z-time Rev. 4.0/Aug. 02 Note1,2 =3.0V to3.6V -55 Min Max Min Max 5 5 1.75 2 1.75 2 4.5 5 1.5 2 1.5 1 1.5 1 1.5 1 1.5 1 5.5 HY57V161610D ) -6 -7 Min Max Min Max 2.5 - 1 ...
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... CLK to data output in high Z-time Note : 1.V (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610DTC-5/55 is 3.15V DD 3.tCK2 is 8.9ns only when tAC2 is 7.9ns in HY57V161610DTC-6 and HY57V161610DTC-7. 4.Assume (input rise and fall time ) is 1ns. Rev. 4.0/Aug. 02 Note1,2 =3.0V to3.6V ...
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... SS -5 -55 Min Max Min Max tRC 16.5 40 100K 38.5 100K tRP HY57V161610D Note1 Min Max Min Max 100K 45 100K ...
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... Precharge to data output Hi-Z Power down exit time Self refresh exit time Refresh Time Note : 1. V (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610DTC-5/55 is 3.15V new command can be given tRRC after self refresh exit. DEVICE OPERATING OPTION TABLE ...
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... HY57V161610DTC-8 CAS Latency 125MHz 3CLKs 100MHz 3CLKs 83MHz 2CLKs HY57V161610DTC-10 CAS Latency 100MHz 3CLKs 83MHz 2CLKs HY57V161610DTC-15 CAS Latency 66MHz 1CLKs Rev. 4.0/Aug. 02 tRCD tRAS tRC 3CLKs 7CLKs 10CLKs 3CLKs 7CLKs 10CLKs 3CLKs 7CLKs 10CLKs tRCD tRAS ...
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... HY57V161610D A10/ WE DQM A0~ code Row Address L Column H X Address H L Column L X Address ...
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... Synchronous DRAM 1.2(0.0472) 1.0(0.0394) 0.646 REF GAGE PLANE 0~5deg Rev. 4.0/Aug. 02 10.262(0.4040) 10.059(0.3960) 0.45(0.0177) 0.8(0.0315 BSC) 0.30(0.0118) 21.057(0.8290) 20.879(0.8220) 0.210(0.0083) 0.597(0.0235) 0.120(0.0118) 0.406(0.0160) HY57V161610D UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 0.150(0.0059) 0.050(0.0020) 13 ...