CS4218-KL Cirrus Logic, Inc., CS4218-KL Datasheet
CS4218-KL
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CS4218-KL Summary of contents
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... The CS4218 is pin and function compatible with the CS4216 when used in Serial modes 3 and 4. See the Appendix A at the end of this data sheet for details trademark of Philips. Ordering Information: CS4218-KL CS4218-KQ D/A OUTPUT MUTE D/A SERIAL INTERFACE CONTROL VOLTAGE REFERENCE ...
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... Serial Interface Modes - Serial Mode 3 - Serial Mode 4 - Serial Mode 5 Power Supply and Grounding . Pin Diagrams and Descriptions Package Information Parameter Definitions . Appendix A: CS4218 Compatibility with the CS4216 . Appendix B: Applications of Serial Mode 4 (SM4) Appendix C: Setting CLKIN/SCLK Ratio for Desired Sample Rate ...
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... DGND = 0V, all voltages with respect Symbol Digital VD Digital (Low Voltage) VD Analog VA +5V; Input Levels: Logic 0 = 0V, A Symbol (Note 1) (Note 3) IDR THD (Note 1) (Note 1) 0dB Gain 22.5dB Gain (Notes 1,2) (Note 1) CS4218 Min Typ Max Units 4.75 5.0 5.25 3.0 3.3 3.6 4.75 5.0 5. Min Typ Max Units 16 - ...
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... Parameter definitions are given at the end of this data sheet. 4 (Continued) Symbol (Note 1) TDR IDR (Note 4) THD (Note 4) (Note 1) (Note 5) (Note 5) (Note 5) (Note 1) (Note 6) (Note 7) (Note 4) (Note 1) (22 kHz to 100 kHz) Operating (VD = 5.0V) Operating (VD = 3.3V) Power Down (1 kHz) CS4218 Min Typ Max Units Bits - - 0.9 LSB - 0.02 ...
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... RESET low time prior to PDN rising RESET low hold time after PDN rising Notes: 7. When the CS4218 is in master modes (SSYNC and SCLK outputs), the SCLK duty cycle is 50%. The equation is based on the selected sample frequency (Fs) and the number of bits per frame (bpf). ...
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... DO1 LAtt4 LAtt3 LAtt2 Err1 1 Err0 LCL Serial Mode 4. Control Data Serial Port Timing CS4218 Bit 33 Bit 63 Bit 64 (Bit 1) (Bit 32) (Bit 31 Bit 63 Bit 33 Bit 64 (Bit 31) (Bit 32) (Bit 1) ADV t ccdov LAtt1 LAtt0 RAtt4 RAtt3 7 8 ...
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... Mode) Power Down Mode Timing ( 5V 3.3V) A Symbol (Digital Inputs) (High-Z Digital Outputs) (Note 1) C OUT (Note CS4218 t ckl t ckh t pd3 SCLK & SSYNC Output Timing (Master Mode) t rhold t rph Min Typ Max 2.0 - VD+0.3 -0.3 - ...
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... Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 8 Symbol (0-0.4Fs) Symbol (0-0.4Fs) (AGND, DGND = 0V, all voltages with respect to 0V.) Symbol Digital VD Analog VA (Except Supply Pins) (Power Applied) CS4218 Min Typ Max Units 0 - 0.40Fs -0 0.1 0.40Fs - 0 ...
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... Input Frequency ( Fs) Figure 5. CS4218 DAC Passband Ripple DS135F1 0.2 0.1 -0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0.6 0.7 0.8 0.9 1.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0. -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Figure 4. CS4218 DAC Frequency Response 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70 CS4218 Input Frequency ( Fs) Figure 2. CS4218 ADC Passband Ripple Input Frequency ( Fs) Input Frequency ( Fs) Figure 6. CS4218 DAC Transition Band 9 ...
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... Input Frequency ( Fs) Figure 7. CS4218 DAC Deviation from Linear Phase 10 CS4218 DS135F1 ...
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... REFBUF 27 LIN1 40 MF1:F1/CDOUT 39 MF2:F2/CDIN 35 MF3:DI3/F3/CCLK 36 MF4:MA/CCS 38 MF5:DO2/INT 34 MF6:DI2/F1 AGND DGND 23 5 Figure 8. Typical Connection Diagram CS4218 +5V 0.1 F Analog If a separate +5V Analog supply is used, remove 24 the 2.0 ohm resistor VA > 1 ROUT 40 k 0.0022 F NPO > 1 LOUT 40 k 0.0022 F ...
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... Since the converters contain all the re- quired filters in digital or sampled analog form, the filters’ frequency responses track the sample rate of the CS4218. Only a single-pole RC filter is required for the analog inputs and outputs. Communication with the CS4218 is via a serial port, with separate pins for data input and out- put ...
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... DI pins are latched, and when the DO pins are updated. Reset and Power Down Modes Reset places the CS4218 into a known state and must be held low for at least 50 ms after power hard power down. In reset, the digital outputs are driven low ...
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... SDOUT, SDIN, SCLK, and SSYNC. The serial port protocol is based on frames con- sisting sub-frames. The frame rate is the system sample rate. Each sub-frame is used by one CS4218 device CS4218s may be Minimum SCLK attached to the same serial control lines. SFS1 Frequency ...
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... Figure 13. Control data bits all reset to zero. CS4218 SERIAL INTERFACE MODES The CS4218 has three serial port modes, selected by the SMODE1, SMODE2 and SMODE3 pins. In all modes, CLKIN, SCLK and SSYNC must be derived from the same clock source. SM3 ...
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... SCLK and SSYNC must be synchro- nous to the master clock. Sub-frame Sub-frame DAC - Right Word 0 Figure 11. Serial Data Input Format - SM3, SM5. Sub-frame Sub-frame ADC - Right Word 0 CS4218 Fs . For exam- max . For max Word Word B X ...
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... Digital Output Output LOW 1 = Output HIGH unused Unused, write with 0’s Symbol Description VER3-VER0 CS4218 Version Number 0000 = Rev A 1000 = Rev B and later ADC-RIGHT Audio Data, ADC Right 2’s Complement data, MSB first (Bit 33 = MSB) reserved These bits can ...
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... Selecting 64 bits per frame (MF8:SFS2 = 0) al- lows only one CS4218 to occupy the serial port. Since there is only one sub-frame (which is equal to one frame), MF7:SFS1 is defined differ- ently in this mode. MF7:SFS1 selects the format of SSYNC ...
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... Word A FRAME (n+2) FRAME (n+3) Sub-frame 1 Sub-frame 1 Word B Word A Word B Word A Figure 14. SM3-M and SM3-MM Sub-Modes. LSB MSB Word A 32 CLOCKS CS4218 FRAME (n+3) Sub-frame 1 MF8: MF7: Sub- SFS2 SFS1 frame Word B Word A Word FRAME (n+4) Sub-frame 1 MF8: MF7: Sub- SFS2 SFS1 frame Word B ...
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... Slave Sub-Mode (SM3-S) In SM3, Slave sub-mode is selected by setting MF4: which configures SSYNC and SCLK as inputs to the CS4218. These two sig- nals must be externally derived from CLKIN. In SM3-S and SM3-MS sub-modes, the phase rela- tionship between SCLK/SSYNC and CLKIN cannot be controlled since SCLK and SSYNC are externally derived ...
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... FRAME (n+1) Sub-frame 1 Sub-frame 2 Word B Word A Word B Word A FRAME n 256 SCLK Periods Sub-frame 3 Sub-frame 4 Word B Word A Word B Word A CS4218 MF8: MF7: Sub- Word B SFS2 SFS1 frame 0 FRAME (n+2) Sub-frame 1 MF8: MF7: Sub- SFS2 SFS1 frame Word B Word A Word FRAME (n+1) MF8: MF7: Sub- ...
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... DAC - Right Word 22 Master Sub-Mode (SM4) Master sub-mode configures SSYNC and SCLK as outputs from the CS4218. During power down, SSYNC and SCLK are driven high im- pedance, and during reset they both are driven low. There are two SM4 Master sub-modes. One allows 32 bits per frame and the other allows 64 bits per frame ...
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... Table 7. SM4-Master, Fs Select Slave Sub-Mode (SM4) In SM4, Slave sub-mode is selected by setting SMODE1,SMODE2 = 01. This mode configures SSYNC and SCLK as inputs to the CS4218. These two signals must be externally derived from CLKIN. Since the CS4218 has no control over the phase relationship of SSYNC and SCLK to CLKIN, the noise performance in Slave sub-mode may be slightly worse than when using Master sub-mode ...
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... MASK bit in the control serial data port. MF5:INT is reset by reading the control serial port Left Right D/A Att. D/A Att. A/D Gain Err Version Figure 20. SM4 - Control Serial Port CS4218 Left Right A/D Gain Err DS135F1 ...
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... A change in sample rate will automatically initiate a calibration cycle. FRAME (n+1) FRAME (n+2) Word A Word B Word A Word B Figure 21. Serial Mode 5 FRAME LSB MSB Word A 32 CLOCKS Figure 22. Detailed Serial Mode 5. CS4218 FRAME (n+4) FRAME (n+3) Word A Word B Word A Word B LSB Word B 32 CLOCKS 25 ...
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... Fig- ure 23. Preferably, it should also have its own power plane. The +5V (or +3.3V) supply must be connected to the CS4218 via a ferrite bead, positioned closer than 1" to the device. If using +5V for VD, the VA supply can be derived from VD, as shown in Figure 8. Alternatively, a sepa- rate +5V analog supply may be used for VA, in which case, the 2 ...
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... Ground Connection CS4218 Power Connection use Ferrite Bead Codec digital signals Figure 23. CS4218 Board Layout Guideline Figure 24. CS4218 Decoupling Layout Guideline CS4218 Analog Note that the CS4218 Ground is oriented with its Plane digital pins towards the digital end of the board. Codec analog signals & ...
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... Digital Supply 1.0 uF Figure 25. CS4218 Surface Mount Decoupling Layout 28 CS4218 + Analog Supply + 10 uF DS135F1 ...
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... MF3:DI3/F3/CCLK 29 MF6:DI2/ DI1 26 SMODE2 25 24 MF7:SFS1/F2 23 MF8:SFS2/F3 22 SMODE1 LIN2 LIN1 RIN2 RIN1 VA AGND MF5 MF6 MF7 DO2 DI2 Tie to DGND Tie to DGND DO2 DI2 SFS1 DO2 DI2 SFS1 INT F1 SFS1 INT F1 F2 CS4218 MF8 SFS2 SFS2 SFS2 F3 29 ...
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... MF3:DI3/F3/CCLK 35 MF6:DI2/ DI1 32 SMODE2 31 30 MF7:SFS1/F2 29 MF8:SFS2/F3 28 SMODE1 LIN2 LIN1 RIN2 RIN1 VA AGND MF5 MF6 MF7 DO2 DI2 tie to DGND tie to DGND DO2 DI2 SFS1 DO2 DI2 SFS1 INT F1 SFS1 INT F1 F2 CS4218 MF8 SFS2 SFS2 SFS2 F3 DS135F1 ...
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... A nominal +2.1V output for setting the bias level for external analog circuits. Serial Digital Audio Interface Signals SDIN - Serial Port Data In, PIN 42(L), 36(Q). Digital audio data to the DACs and level control information is received by the CS4218 via SDIN. SDOUT - Serial Port Data Out, PIN 43(L), 37(Q). ...
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... SSYNC and SCLK. When MF4: the codec is in slave sub-modes and receives SSYNC and SCLK from an external source that must be frequency locked to CLKIN. MF4 - SM5, PIN 36(L), 30(Q). In SM5, this pin is not used and should be tied to VD. 32 CS4218 DS135F1 ...
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... MF7:SFS1 - Sub-Frame Select 1 in SM3/SM4-SL, PIN 31(L), 25(Q). In SM3, MF7:SFS1 helps select the sub-frame that this particular CS4218 is allocated. In slave sub-mode of SM4, this pin is one of two pins used as a sub-frame select when MF6: (128-bit frames). When MF6: this pin is used to select the frame sizes bits. ...
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... SCLK to CLKIN in slave modes, or changing the format pin values (F2-F0) in master modes. PDN - Power Down, PIN 13(L), 7(Q). This pin, when low, causes the CS4218 to go into a power down state. RESET should be held low for 50 ms when exiting the power down state to allow time for the voltage reference to settle. ...
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... R MIN MAX C 0.46 ( 0.018 ) 0.33 ( 0.013 ) DIM CS4218 B 1.14 (0.045) x 45deg. NOM B A 1.35 (0.053) 1.19 (0.047) 44 Pin TQFP 1.4 mm Package Thickness MILLIMETERS INCHES MIN MAX MIN MAX 11.75 12.25 0.463 0.482 9.90 10.10 0.390 0.398 ...
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... For the ADCs, the deviation of the output code from the mid-scale with the selected input at REFBUF. For the DACs, the deviation of the output from REFBUF with mid-scale input code. Units in LSB’s for the ADCs and volts for the DACs. 36 CS4218 DS135F1 ...
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... Out of Band Energy The ratio of the rms sum of the energy from 0. 2.1 Fs compared to the rms full-scale signal value. Tested with 48 kHz Fs giving a out-of-band energy range of 22 kHz to 100 kHz. DS135F1 CS4218 37 ...
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... If this pin is left floating, the codec will not work correctly. The CS4218 adds the pin named FILT. On the CS4216, this pin connect. The FILT pin is only used when employing the SM3 Multiplier sub-mode. When using this sub-mode, a 0.47uF capacitor must be connected from the FILT pin to AGND ...
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... The CS4218 and CS4216 both require that the analog power supply be 5V +/- 0.25V. The CS4218 digital power supply can operate from 5V +/- 0.25V and 3.3V +/- 0.3V. When operated from a 5V supply, the CS4218 is TTL and CMOS compatible inputs & outputs. When operated from a 3.3V power supply, the CS4218 is LVTTL and LVCMOS compatible. ...
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... The control data resets to all zeros, which configures the CS4218 as a simple stereo codec: no gain, no attenuation, line inputs #1, and DAC outputs not muted. Figure B3 illustrates how to use all the CS4218 features with a low cost DSP that cannot support the interrupt rate of SM3. Using SM4 (32 bits per frame, Master sub-mode) reduces the DSP interrupts in half since the control data is split from the audio data ...
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... MF2:CDIN LOAD CS4218 SM4 32 BPF 40 MF1:CDOUT 2 RESET 34 MF6:F1 31 MF7:F2 30 MF8:F3 DS135F1 VD+ HC597 HC597 0 A SCLK ADV B DI1 C LCLK D RCL LCL E AIN ERR0 F ERR1 G HC595 CS^STATUS CS^FS HC574 Figure B3. SM4 - Enhanced DSP Interface CS4218 DSP HC597 DIN CS^CONTROL 24+ bit DSP Data Bus 41 ...
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... The third section is only needed if sample frequencies need to be changed. This section is comprised of an HC574 octal latch that can be replaced by general purpose port pins if available. This section controls the sample frequency selection bits: MF6:F1, MF7:F2, MF8:F3 and the RESET pin. A change in sample rate automatically initiates a calibration cycle. 42 CS4218 DS135F1 ...
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... Appendix C: Setting CLKIN/SCLK Ratio for Desired Sample Rate In Slave sub-modes, the CS4218 detects the ratio between the CLKIN and SCLK rates and sets the internal sample rate accordingly. The following formula can be used to determine the ratio of CLKIN to SCLK for any desired sample rate for both Serial Modes 3 and 4, Slave sub-modes. ...
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TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...