RM7065A-300T PMC-Sierra Inc, RM7065A-300T Datasheet
RM7065A-300T
Specifications of RM7065A-300T
Related parts for RM7065A-300T
RM7065A-300T Summary of contents
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... RM7065A™ Microprocessor with On- Chip Secondary Cache Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet RM7065A Data Sheet Preliminary Issue 2, June 2001 Preliminary ...
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... Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 2 ...
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... April 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Details of Change Changed IP references to INT, page 34. Changed W7 pin name to SysClk. Applied PMC-Sierra template to existing MPD (QED) preliminary FrameMaker document ...
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... All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold typeface. All instruction names, such as MFHI, are in san serif typeface. • Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 4 ...
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... System Interface Operation .........................................................................................28 4.29 Data Prefetch ...............................................................................................................30 4.30 Enhanced Write Modes ................................................................................................31 4.31 External Requests ........................................................................................................31 4.32 Test/Breakpoint Registers ............................................................................................31 4.33 Performance Counters .................................................................................................32 4.34 Interrupt Handling ........................................................................................................34 4.35 Standby Mode ..............................................................................................................36 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 5 ...
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... Boot-Time Interface Parameters ..................................................................................46 11 Timing Diagrams ...................................................................................................................47 11.1 Clock Timing ................................................................................................................47 12 Packaging Information ..........................................................................................................48 13 RM7065A Pinout ...................................................................................................................50 14 Ordering Information .............................................................................................................52 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 6 ...
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... Figure 10 Multiple Outstanding Reads ......................................................................................30 Figure 11 Clock Timing ..............................................................................................................47 Figure 12 Input Timing ...............................................................................................................47 Figure 13 Output Timing ............................................................................................................47 Figure 14 Mechanical Diagram .................................................................................................48 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 7 ...
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... Table 16 Boot Time Mode Stream .............................................................................................37 Table 17 System Interface .........................................................................................................38 Table 18 Clock/Control Interface ...............................................................................................39 Table 19 Interrupt Interface .......................................................................................................40 Table 20 JTAG Interface ...........................................................................................................40 Table 21 Initialization Interface ..................................................................................................40 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 8 ...
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... Fourteen fully prioritized vectored interrupts — 10 external, 2 internal, 2 software • Fully static CMOS design with dynamic power down logic Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 9 ...
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... MultAdd, Add, Sub, Cvt, Div, Sqrt Multiplier Array Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet 256KB Secondary Cache, 4-way Set Associative Secondary Tags Set B DTag ...
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... It has two high-performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit. The RM7065A integrates 16 KB 4-way set associative instruction and data caches along with an integrated 256 KB 4-way set associative secondary. The primary data and secondary caches are write-back and non-blocking ...
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... Superscalar Dispatch The RM7065A incorporates a superscalar dispatch unit that allows it to issue up to two instructions per cycle. For purposes of instruction issue, the RM7065A defines four classes of instructions: integer, load/store, branches, and floating-point. There are two logical pipelines, the function pipeline and the memory pipeline. Note however that the M pipe can execute integer as well as memory type instructions ...
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... W, pipe stage. The physical length of the floating-point execution pipeline is actually seven stages but this is completely transparent to the user. Figure 4 shows instruction execution within the RM7065A when instructions are issuing simultaneously down both pipelines. As illustrated in the figure ten instructions can be executing simultaneously ...
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... Register File The RM7065A has thirty-two general purpose registers with register location 0 (r0) hard wired to a zero value. These registers are used for scalar integer operations and address calculation. In order ...
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... ALU The RM7065A has two complete integer ALUs each consisting of an integer adder/subtractor, a logic unit, and a shifter. Table 3 shows the functions performed by the ALUs for each execution unit. Each of these units is optimized to perform all operations in a single processor cycle. Table 3 ALU Operations ...
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... The floating-point coprocessor is a tightly coupled execution unit, decoding and executing instructions in parallel with, and in the case of floating-point loads and stores, in cooperation with the M pipe of the integer unit. The superscalar capabilities of the RM7065A allow floating-point computation instructions to issue concurrently with integer instructions. ...
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... Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Repeat Rate single/double 4 ...
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... MFC0 and MTC0 instructions, the RM7065A supports the same registers as found in the RM5200 Family. In the control space, which is accessed by the previously unused CTC0 and CFC0 instructions, the RM7065A supports five new registers. The first three of these new 32-bit registers support the enhanced interrupt handling capabilities; Interrupt Control, Interrupt Priority Level Lo (IPLLO), and Interrupt Priority Level Hi (IPLHI) ...
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... The RM7065A processor also supports a supervisor mode in which the virtual address space is 256 32-bit mode), divided into three regions based on the high-order bits of the virtual address. Figure 6 shows the address space layout for 32-bit operations. ...
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... Mapped, 2.0GB 0x00000000 When the RM7065A is configured for 64-bit addressing, the virtual address space layout is an upward compatible extension of the 32-bit virtual address space layout. 4.13 Joint TLB For fast virtual-to-physical address translation, the RM7065A uses a large, fully associative TLB that maps virtual pages to their corresponding physical addresses ...
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... JTLB. The operation of the ITLB is completely transparent to the user. 4.15 Data TLB The RM7065A uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB. Each DTLB entry maps page. The DTLB improves performance by allowing data address translation to occur in parallel with instruction address translation. When a miss occurs on a data address translation, the DTLB is filled from the JTLB. The DTLB refill is pseudo-LRU ...
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... A 32-byte (eight instruction) line size is used to maximize the communication efficiency between the instruction cache and the secondary cache or memory system. The RM7065A supports cache locking on a per line basis. The contents of each line of the cache can be locked by setting a bit in the Tag RAM. Locking the line prevents its contents from being overwritten by a subsequent cache miss ...
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... If the tag matches, then the data is written into the data cache in the next cycle that the data cache is not accessed (the next non-load cycle). The store buffer allows the RM7065A to Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ ...
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... The RM7065A allows entries to be stored in the primary caches that do not necessarily have a corresponding entry in the secondary; the RM7065A does not force the primaries subset of the secondary. For example, if primary cache line A is being filled and a cache line already exists in the secondary for primary cache line B at the location where primary A’ ...
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... Cache Locking The RM7065A allows critical code or data fragments to be locked into the primary and secondary caches. The user has complete control over the locking function. For instruction and data fragments in the primary caches, locking is accomplished by setting either or both of the cache lock enable bits and specifying the set in the CP0 ECC register, then executing either a load instruction for data Fill_I cache operation for instructions ...
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... System Interface The RM7065A provides a high-performance 64-bit system interface which is compatible with the RM5200 Family enhancement to the SysAD bus interface, the RM7065A allows half- Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ ...
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... System Address/Data Bus The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the RM7065A and the rest of the system protected with an 8-bit parity check bus, SysADC[7:0]. The system interface is configurable to allow easy interfacing to memory and I/O systems of varying frequencies ...
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... Handshake Signals There are ten handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are driven by an external device to indicate to the RM7065A whether it can accept a new read or write transaction. The RM7065A samples these signals before deasserting the address on read and write requests ...
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... The external agent retakes control of the bus and begins returning data (out of order) for the second miss to the processor Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Data0 Data1 NData ...
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... PRqst* PAck* 4.29 Data Prefetch The RM7065A is the first PMC-Sierra design to support the MIPS IV integer data prefetch ( PREF ) and floating-point data prefetch ( PREFX ) instructions. These instructions are used by the compiler assembly language programmer when it is known or suspected that an upcoming data reference is going to miss in the cache. By appropriately placing a prefetch instruction, the memory latency can be hidden under the execution of other instructions ...
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... WrRdy*. 4.31 External Requests The RM7065A can respond to certain requests issued by an external device. These requests take one of two forms: Write requests and Null requests. An external device executes a write request when it wishes to update one of the processors writable resources such as the internal interrupt register ...
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... Watch exception. 4.33 Performance Counters To facilitate system tuning, the RM7065A implements a performance counter using two new CP0 registers, PerfCount and PerfControl. The PerfCount register is a 32-bit writable counter which causes an interrupt when bit 31 is set. The PerfControl register is a 32-bit register containing a 5- bit field which selects one of twenty-two event types as well as a handful of bits which control the overall counting function ...
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... The performance counter interrupt only occurs when interrupts are enabled in the Status register, IE=1, and the Interrupt Mask bit 13 (IM[13]) of the coprocessor 0 interrupt control register is set. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 33 ...
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... When a hang occurs the interrupt ultimately triggers, thereby breaking free from the hang-up. 4.34 Interrupt Handling In order to provide better real time interrupt handling, the RM7065A provides an extended set of hardware interrupts, each of which can be separately prioritized and separately vectored. In addition to the standard six external interrupt pins, the RM7065A provides four more interrupt pins for a total of ten external interrupts ...
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... Table 13 and Table 14 above. The priority level registers are located in the coprocessor 0 control register space. In addition to programmable priority levels, the RM7065A also permits the spacing between interrupt vectors to be programmed. For example, the minimum spacing between two adjacent vectors is 0x20 while the maximum is 0x200. This programmability allows the user to either set up the vectors as jumps to the actual interrupt routines or, if interrupt latency is paramount, to include the entire interrupt routine at one vector ...
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... Standby Mode The RM7065A provides a means to reduce the amount of power consumed by the internal core when the CPU is not performing any useful operations. This state is known as Standby Mode. Executing the WAIT instruction enables interrupts and causes the processor to enter Standby Mode ...
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... Reserved: Must be zero Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Mode bit Description 17:16 System configuration identifiers - software visible in processor Config[21..20] register 19:18 Reserved: Must be zero 20 Pclock to SysClock multipliers ...
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... Pin Descriptions The following is a list of control, data, clock, interrupt, and miscellaneous pins of the RM7065A. Table 17 System Interface Pin Name Type ExtRqst* Input Release* Output RdRdy* Input WrRdy* Input ValidIn* Input ValidOut* Output PRqst* Output PAck* Input RspSwap* Input RdType Output ...
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... System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. System Command/Data Identifier Bus Parity For the RM7065A, unused on input and zero on output. Description System clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock ...
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... Allows the system to change the processor addressing mode without rewriting the mode ROM. Vcc is OK When asserted, this signal indicates to the RM7065A that the VccInt power supply has been above the recommended value for more than 100 milliseconds and will remain stable. The assertion of VccOK initiates the reading of the boot-time mode control serial stream ...
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... Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet should not exceed 3 ...
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... As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG test mode. Refer to the RM7065A Family Users Manual, Appendix E. 4. VccP must be connected to VccInt through a passive filter circuit. See RM7000 Family User’s Manual for recommended circuit. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’ ...
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... -0. 1. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Maximum Conditions 0.2V |I OUT 0.4V |I OUT 0.8V VccIO + 0. Maximum Conditions ...
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... Dhrystone 2.1 instruction mix. 3. I/O supply power is application dependant, but typically <20% of VccInt. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet CPU Speed 300 MHz 350 MHz 1 Max ...
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... JTAG Clock t JTAGCKP Period Note 1. Operation of the RM7065A is only guaranteed with the Phase Lock Loop Enabled. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Min Max ...
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... Mode Data Setup t DS Mode Data Hold t DH Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet CPU Speed 300 MHz Min Max Min 5,6 1.0 TBD mode14.. ...
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... System Interface Timing (SysAD, SysCmd, ValidIn*, ValidOut*, etc.) Figure 12 Input Timing SysClock Data Figure 13 Output Timing SysClock Data Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet t t High Low t t Fall Rise t t ...
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... Package Dimensions conform to JEDEC Registration MO-149(BG-2X). 2. "e" represents the basic solder ball grid pitch. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet DETAIL Y ...
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... After surface mount assembly, solder ball will have 0.15 mm (TYP) collapse in "A" dimension. 9. Substrate base material is copper. 10. Package top surface color shall be black. 11. Cavity depth maximum is 0.50 mm. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 49 ...
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... L17 VccInt M1 VSS M17 VccIO N1 SysAD[14] N17 VccInt Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Pin Function Pin A2 VSS A3 A6 VSS A7 A10 SysADC[1] A11 ...
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... VccIO Y5 ValidOutB Y9 VSS Y13 SysCmd[4] Y17 Int[0]* Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet Pin Function Pin P2 RSPSWAPB P3 P18 VccOK P19 R2 Do Not Connect ...
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... Ordering Information RM7065A -123 Valid Combinations RM7065A-300T RM7065A-350T Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2010145, Issue 2 RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet T I Temperature Grade: (blank) = commercial Package Type TBGA Device Maximum Speed Device Type ...