PM4388-RI PMC-Sierra Inc, PM4388-RI Datasheet

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PM4388-RI

Manufacturer Part Number
PM4388-RI
Description
Octal T1 framer
Manufacturer
PMC-Sierra Inc
Datasheet

Specifications of PM4388-RI

Case
QFP
Dc
00+
PM4388 TOCTL
DATA SHEET
PMC-960840
ISSUE 5
OCTAL T1 FRAMER
PM4388
TOCTL
OCTAL T1 FRAMER
DATASHEET
ISSUE 5: NOVEMBER 1998
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

Related parts for PM4388-RI

PM4388-RI Summary of contents

Page 1

... DATA SHEET PMC-960840 OCTAL T1 FRAMER PMC-Sierra, Inc. ISSUE 5 PM4388 TOCTL DATASHEET ISSUE 5: NOVEMBER 1998 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM4388 TOCTL OCTAL T1 FRAMER ...

Page 2

... RDLC FACILITY DATA LINK RECEIVER..................................... 22 9.7 ALARM INTEGRATOR (ALMI) ..................................................... 23 9.8 ELASTIC STORE (ELST) ............................................................ 23 9.9 SIGNALING EXTRACTOR (SIGX)............................................... 24 9.10 RECEIVE PER-DS0 SERIAL CONTROLLER (RPSC) ................ 24 9.11 INGRESS INTERFACE (IIF) ........................................................ 25 9.12 PATTERN DETECTOR/GENERATOR (PRGD) ............................ 27 9.13 BASIC TRANSMITTER (XBAS) ................................................... 28 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER i ...

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... USING THE INTERNAL FDL RECEIVER.................................. 214 14.4 USING THE PRGD PATTERN GENERATOR/DETECTOR ........ 218 14.5 USING THE LOOPBACK MODES............................................. 223 14.5.1 LINE LOOPBACK............................................................ 223 14.5.2 DIAGNOSTIC DIGITAL LOOPBACK ............................... 224 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER ii ...

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... ABSOLUTE MAXIMUM RATINGS........................................................ 243 16 D .C. CHARACTERISTICS .................................................................. 244 17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ...... 246 18 TOCTL I/O TIMING CHARACTERISTICS ............................................ 251 19 ORDERING AND THERMAL INFORMATION ...................................... 263 20 MECHANICAL INFORMATION............................................................. 264 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER iii ...

Page 5

... REGISTER 00BH: TOCTL MASTER TEST ....................................................... 70 REGISTER 00CH: TOCTL REVISION/CHIP ID/GLOBAL PMON UPDATE....... 72 REGISTERS 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH: FRAMER RESET.................................................................................................... 73 REGISTER 00EH: INTERRUPT ID ................................................................... 74 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER iv ...

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... REGISTERS 021H, 0A1H, 121H, 1A1H, 221H, 2A1H, 321H, 3A1H: FRMR INTERRUPT ENABLE ............................................................................ 92 REGISTERS 022H, 0A2H, 122H, 1A2H, 222H, 2A2H, 322H, 3A2H: FRMR INTERRUPT STATUS ............................................................................. 94 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER v ...

Page 7

... REGISTER 034H, 0B4H, 134H, 1B4H, 234H, 2B4H ,334H, 3B4H: TDPR CONFIGURATION ................................................................................ 115 REGISTER 035H, 0B5H, 135H, 1B5H, 235H, 2B5H ,335H, 3B5H: TDPR UPPER TRANSMIT THRESHOLD ....................................................... 117 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER vi ...

Page 8

... REGISTERS 042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H: SIGX SIGNALING STATE CHANGE CHANNELS 9-16 (COSS=1) ................ 135 REGISTERS 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H: SIGX CHANNEL INDIRECT DATA BUFFER (COSS = 0) .............................. 136 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER vii ...

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... REGISTERS 04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH: PMON COFA COUNT ...................................................................................... 155 REGISTERS 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H: RPSC CONFIGURATION ................................................................................ 156 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER viii ...

Page 10

... REGISTER 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H: PRGD CONTROL ............................................................................................ 175 REGISTER 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H: PRGD INTERRUPT ENABLE/STATUS ............................................................ 177 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER ix ...

Page 11

... REGISTER 06EH, 0EEH, 16EH, 1EEH, 26EH, 2EEH, 36EH, 3EEH: PRGD PATTERN DETECTOR #3 .................................................................... 189 REGISTER 06FH, 0EFH, 16FH, 1EFH, 26FH, 2EFH, 36FH, 3EFH: PRGD PATTERN DETECTOR #4 .................................................................... 190 REGISTER 00BH: TOCTL MASTER TEST ..................................................... 192 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER x ...

Page 12

... FIGURE 18- INGRESS INTERFACE: 1.544MHZ CLOCK SLAVE MODES .... 202 FIGURE 19- EGRESS INTERFACE : 1.544 MHZ CLOCK SLAVE: EFP ENABLED MODE ................................................................................. 202 FIGURE 20- EGRESS INTERFACE : 1.544 MHZ CLOCK SLAVE: EXTERNAL SIGNALING MODE .............................................................................. 203 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER xi ...

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... FIGURE 39- XCLK=37.056 MHZ INPUT TIMING ........................................... 251 FIGURE 40- EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP ENABLED MODE................................................................................................... 252 FIGURE 41- EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL SIGNALING MODE .............................................................................. 253 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER xii ...

Page 14

... FIGURE 48- JTAG PORT INTERFACE TIMING DIAGRAM ............................ 261 FIGURE 49- 128 PIN COPPER LEADFRAME PLASTIC QUAD FLAT PACK (R SUFFIX):............................................................................................... 264 FIGURE 50- 128 PIN CHIP ARRAY BALL GRID ARRAY (N SUFFIX):........... 265 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER xiii ...

Page 15

... TABLE 19 - XCLK=37.056 MHZ INPUT (FIGURE 39)................................... 251 TABLE 20 - EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP ENABLED MODE (FIGURE 40) ............................................................................. 252 TABLE 21 - EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL SIGNALING (FIGURE 41) .................................................................... 253 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER xiv ...

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... TABLE 27 - RECEIVE LINE INTERFACE TIMING (FIGURE 47)................... 259 TABLE 28 - JTAG PORT INTERFACE TIMING (FIGURE 48) ........................ 260 TABLE 29 - TOCTL ORDERING INFORMATION .......................................... 263 TABLE 30 - TOCTL THERMAL INFORMATION............................................. 263 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER xv ...

Page 17

... Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring. Low power 3.3V CMOS technology with 5V tolerant inputs. Supports standard 5 signal P1149.1 JTAG boundary scan. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 1 ...

Page 18

... SF and ESF formats. Provides a digital phase locked loop for generation of a low jitter transmit clock. Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 2 ...

Page 19

... PMC-960840 2 APPLICATIONS High density Internet T1 interfaces for multiplexers, switches, routers and digital modems. Frame Relay switches and access devices (FRADS) SONET/SDH Add Drop Multiplexers PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 3 ...

Page 20

... AT&T - Requirements For Interfacing Digital Terminal Equipment To Services Employing The Extended Superframe Format, TR 54016, September, 1989. 11. AT&T, TR 62411 - Accunet T1.5 - "Service Description and Interface Specification" December, 1990. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 4 ...

Page 21

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM4388-RI TOCTL PM4388-RI TOCTL PM4388-RI TOCTL PM4388-RI TOCTL Channelized /Unchannelized HDLC Processor(s) PM4388-RI TOCTL # PM4388-RI TOCTL # PM4388 TOCTL OCTAL T1 FRAMER Packet Router Core or Packet Switch Core 5 ...

Page 22

... Extraction RBOC Bit Oriented Alarm Code Integrator Detector RDLC Performance HDLC Monitor Receiver Counters * These signals are shared between all eight framers. PM4388 TOCTL OCTAL T1 FRAMER TOPS Timing Options TJAT TLCLK[1:8] Digital Jitter TLD[1:8] Attenuator XCLK* RAM RLCLK[1:8 RJAT Digital Jitter ...

Page 23

... DATA SHEET PMC-960840 6 DESCRIPTION The PM4388 Octal T1 Framer (TOCTL feature-rich device for use primarily in systems carrying data (frame relay, Point to Point Protocol, or other protocols) over DS-1 facilities. Each of the framers and transmitters is independently software configurable, allowing feature selection without changes to external wiring ...

Page 24

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4388 Top V iew PM4388 TOCTL OCTAL T1 FRAMER P IN 103 P IN 102 SIG [ SIG [ ...

Page 25

... ICLK/ ISIG[6] ICLK/ ISIG[7] A[9] A[7] PHA[1] D[4] INTB A[6] A[3] A[0] D[5] D[2] A[4] A[1] ALE PHD[1] D[7] A[5] A[2] PLD[1] PLA[2] D[ PM4388 TOCTL OCTAL T1 FRAMER CTCLK TCK RLD[1] RLD[3] CECLK TMS RLD[2] RLD[4] TDO RLCLK[1] RLCLK[3] TLCLK[1] TDI RLCLK[2] TLD[1] TLCLK[2] RLCLK[4] TLD[2] TLCLK[4] TLD[4] TLD[3] TLCLK[3] PLA[0] ...

Page 26

... Receive Line Clocks (RLCLK[1:8]). Each input externally recovered 1.544 MHz line clock 6 C2 that samples the RLD[x] inputs on its active 8 E4 edge. RLCLK[x] may be a gapped clock 32 K2 subject to the timing constraints in the Timing section of this datasheet PM4388 TOCTL OCTAL T1 FRAMER 10 ...

Page 27

... When Clock Master: Full DS1 mode is active, 71 L12 IFP[x] is updated on the active edge of the 68 J10 associated ICLK[x]. When Clock Master: NxDS0 mode is active, ICLK[x] is gapped during the pulse on IFP[x]. When the Clock Slave ingress modes are active, IFP[x] is updated on the active edge of CICLK. PM4388 TOCTL OCTAL T1 FRAMER 11 ...

Page 28

... MHz rate is selected). If ingress signaling alignment is required, ingress signaling alignment must be enabled, and a pulse at least 1 CICLK cycle wide must be provided on CIFP every frame times. CIFP is sampled on the active edge of CICLK. PM4388 TOCTL OCTAL T1 FRAMER 12 ...

Page 29

... ESIG[8:1] inputs contain the signaling bits for each channel in the transmit data frame, repeated for the entire superframe. Each channel's signaling bits are in bit locations 5,6,7,8 of the channel and are frame-aligned by the common egress frame pulse, CEFP . ESIG[x] is sampled on the active edge of CECLK. PM4388 TOCTL OCTAL T1 FRAMER 13 ...

Page 30

... When the Clock Slave: EFP Enabled mode is active, CEFP and ED[x] are sampled on the active edge of CECLK, and EFP[x] is updated on the active edge of CECLK. When the Clock Slave: External Signaling mode is active, CEFP , ESIG[x] and ED[x] are sampled on the active edge of CECLK. PM4388 TOCTL OCTAL T1 FRAMER 14 ...

Page 31

... Transmit Line Data (TLD[1:8]). TLD[1: contain the transmit stream for each of the 13 F4 eight DS-1 line interface units, or for the higher 15 E1 order multiplex interface. These outputs are 22 G3 updated on the active edge of the 24 H1 corresponding TLCLK[1:8 PM4388 TOCTL OCTAL T1 FRAMER 15 ...

Page 32

... L11 Active low read enable (RDB). This signal is pulsed low to enable a TOCTL register read access. The TOCTL drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are both low. PM4388 TOCTL OCTAL T1 FRAMER 16 ...

Page 33

... B3 Test Mode Select (TMS). The test mode select (TMS) signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. PM4388 TOCTL OCTAL T1 FRAMER 17 ...

Page 34

... K12 decoupled +3.3V DC supply together with the 92 D10 core power pins PHD3:0] . 107 Core power pins (PHD[3:0]). These pins must connected to a common, well decoupled 85 F11 +3.3V DC supply together with the pad ring 116 A6 power pins PHA[4:0]. PM4388 TOCTL OCTAL T1 FRAMER 18 ...

Page 35

... M6 together with the core ground pins PLD[3:0]. 75 H10 93 E9 108 Core ground pins (PLD[3:0]). These pins must connected to a common ground together 86 F10 with the pad ring ground pins PLA[5:0]. 118 C6 PM4388 TOCTL OCTAL T1 FRAMER 19 ...

Page 36

... FRAM and uses it to find frame; when frame synchronization is determined, the FRMR relinquishes control of FRAM to ELST which buffers the incoming PCM data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 20 ...

Page 37

... The Bit Oriented Code detection function is provided by the RBOC block. This block detects the presence the possible 64 bit oriented codes transmitted in the Facility Data Link channel in ESF framing format, as defined in PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 21 ...

Page 38

... FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 th code (111111) is similar to the PM4388 TOCTL OCTAL T1 FRAMER 22 ...

Page 39

... CEFP and CIFP are tied together, and the CICLKRISE and CECLKFALL register bits are either both logic 1 or both logic 0. CICLKRISE and CECLKFALL are found in registers 3 and 4 of each octant, respectively. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER -3 bit error rate. 23 ...

Page 40

... The RPSC allows data and signaling trunk conditioning to be applied on the receive DS-1 stream on a per-DS0 basis. It also allows per-DS0 control of data inversion, the extraction of clock and data on ICLK[x] and ID[x] (when the Clock PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 24 ...

Page 41

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 FRAM Framer/ Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction PM4388 TOCTL OCTAL T1 FRAMER RLCLK[1:8] RJAT Digital Jitter RLD[1:8] Attenuator RECEIVER 25 ...

Page 42

... Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction FRAM Framer/ ELST Slip Buffer Elastic RAM Store FRMR Framer: Frame Alignment, Alarm Extraction PM4388 TOCTL OCTAL T1 FRAMER RLCLK[1:8 RJAT Digital Jitter RLD[1:8] Attenuator RECEIVER RLCLK[1:8] RJAT Digital Jitter RLD[1:8] Attenuator RECEIVER 26 ...

Page 43

... Revision/Chip ID/Global PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 FRAM Framer/ ELST Slip Buffer Elastic RAM Store FRMR Framer: Frame Alignment, Alarm Extraction PM4388 TOCTL OCTAL T1 FRAMER RLCLK[1:8 RJAT Digital Jitter RLD[1:8] Attenuator RECEIVER 27 ...

Page 44

... CRC-6 bit from the egress stream can be by-passed to the output PCM stream. Finally, the transmitter can be by-passed completely to provide an unframed operating mode. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 28 ...

Page 45

... The transmitted bit oriented codes have priority over any data transmitted on the FDL PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 29 ...

Page 46

... Abort characters can be continuously transmitted at any time by setting a control bit. During packet transmission, an underrun situation can occur if data is not written to the TDPR Transmit Data register before the previous byte has been PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 30 ...

Page 47

... For low frequency wander, below 10 Hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. The DJAT blocks meet the stringent low frequency jitter tolerance PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 31 ...

Page 48

... Hz UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK divided by 24 and that of the input data clock. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 32 ...

Page 49

... If TJAT is left to free-run without a reference, or referenced to a derivative of XCLK, then XCLK accuracy must be ±32 ppm. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 10 100 0.3k 1k Jitter Frequency, Hz PM4388 TOCTL OCTAL T1 FRAMER DJAT minimum tolerance acceptable unacceptable 10k 100k ...

Page 50

... Jitter Gain (dB) -30 -40 -50 1 6.6 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 200 250 0 32 62411 max DJAT response 10 100 Jitter Frequency, Hz PM4388 TOCTL OCTAL T1 FRAMER 300 354 Hz 100 ± ppm 43802 max 1k 10k 34 ...

Page 51

... CTCLK or XCLK. The CEFP input is unused in this mode, and has no effect. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunk Conditioning Line Coding PM4388 TOCTL OCTAL T1 FRAMER TRANSMITTER RLCLK[1:8] TJAT TLCLK[1:8] Digital PLL TLD[1:8] 35 ...

Page 52

... Frame Generation, Alarm Insertion, Signaling Trunk Conditioning I i Line Coding XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunk Conditioning I i Line Coding PM4388 TOCTL OCTAL T1 FRAMER TRANSMITTER RLCLK[1:8] TJAT TLCLK[1:8] Digital PLL TLD[1:8] TRANSMITTER TJAT RLCLK[1:8] Digital PLL TLCLK[1:8] TJAT FIFO TLD[1:8] ...

Page 53

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunk Conditioning I i Line Coding PM4388 TOCTL OCTAL T1 FRAMER TRANSMITTER RLCLK[1:8 TJAT TLCLK[1:8 Digital PLL TJAT FIFO TLD[1:8] 37 ...

Page 54

... TJAT Reference Clock Divisor (N1) Control 21A 29A 31A 39A TJAT Output Clock Divisor (N2) Control 21B 29B 31B 39B TJAT Configuration 21C 29C 31C 39C ELST Configuration 21D 29D 31D 39D ELST Interrupt Enable/Status PM4388 TOCTL OCTAL T1 FRAMER 38 ...

Page 55

... TDPR Transmit Data 23A 2BA 33A 3BA TDPR Reserved 23B 2BB 33B 3BB TDPR Reserved 23C 2BC 33C 3BC IBCD Configuration 23D 2BD 33D 3BD IBCD Interrupt Enable/Status 23E 2BE 33E 3BE IBCD Activate Code PM4388 TOCTL OCTAL T1 FRAMER 39 ...

Page 56

... RDLC Primary Address Match 259 2D9 359 3D9 RDLC Secondary Address Match 25A 2DA 35A 3DA RDLC Reserved 25B 2DB 35B 3DB RDLC Reserved 25C 2DC 35C 3DC XBOC Reserved 25D 2DD 35D 3DD XBOC Code PM4388 TOCTL OCTAL T1 FRAMER 40 ...

Page 57

... PRGD Pattern Detector #1 26D 2ED 36D 3ED PRGD Pattern Detector #2 26E 2EE 36E 3EE PRGD Pattern Detector #3 26F 2EF 36F 3EF PRGD Pattern Detector #4 270- 2F0- 370- 3F0- Reserved 27F 2FF 37F 3FF Reserved for Test PM4388 TOCTL OCTAL T1 FRAMER 41 ...

Page 58

... Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted. 5. Writing into read-only normal mode register bit locations does not affect TOCTL operation unless otherwise noted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 42 ...

Page 59

... Setting the IBCD_IDLE bit gaps the data to the IBCD block during the framing bit. This allows the IBCD to be used to detect the idle code in the receive PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default FIFOBYP 0 UNF 0 IBCD_IDLE 0 Reserved 0 AUTOYELLOW 0 AUTORED 0 AUTOOOF 0 AUTOUPDATE 0 PM4388 TOCTL OCTAL T1 FRAMER 43 ...

Page 60

... The results will then be available for reading for the next second, until they are overwritten by the next update. The OVR bit in the PMON Interrupt/Enable register indicates such an overwrite by going to logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 44 ...

Page 61

... PRGD may be initiated by the microprocessor via the Revision/Chip ID/Global PMON Update register, and care must be taken to avoid initiating an update while another update is in progress. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 45 ...

Page 62

... RLCLK[x]. When ICLKSEL is a logic 0, ICLK[ kHz timing reference that is generated by dividing the jitter attenuated version of RLCLK[x] by 193. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default IMODE[1] 1 IMODE[0] 1 ICLKSEL 0 CICLK2M 0 Reserved 0 ISFP 0 ALTIFP 0 IMTKC 0 PM4388 TOCTL OCTAL T1 FRAMER 46 ...

Page 63

... When IMTKC is set to logic 0, the data and signaling signals are modified on a per-DS0 basis in accordance with the control bits contained in the per-DS0 control registers within the RPSC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 47 ...

Page 64

... EDI and ESIGI status bits but are not indicated on the INTB output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default EPTYP 0 EPRTYE 0 EDI X ESIGI X PTY_EXTD 0 Unused X IPTYP 0 IPRTYE 0 PM4388 TOCTL OCTAL T1 FRAMER 48 ...

Page 65

... The IPRTYE bit enables ingress parity insertion. When set a logic one, parity is inserted into the F-bit position of the ID[x] and ISIG[x] streams. When set to logic zero, the F-bit passes through transparently. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 49 ...

Page 66

... CICLK edge. This bit must be set to the same value in all eight registers for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X ICLKRISE 0 RLCLKFALL 0 CIFPFALL 0 CICLKRISE 0 PM4388 TOCTL OCTAL T1 FRAMER 50 ...

Page 67

... CICLK edge. When CICLKRISE is set to logic 0, ID[x], ISIG[x] and IFP[x] are updated on the falling CICLK edge. This register bit has no effect when the Clock Master ingress modes are enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 51 ...

Page 68

... CECLK edge. When CECLKFALL is set to logic 1, ED[x], ESIG[x] and CEFP are sampled on the falling CECLK edge. When CECLKFALL is set to logic 0, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default FIFOBYP 0 TAISEN 0 Unused X Unused X CECLKFALL 0 EFPRISE 0 ECLKFALL 0 TLCLKRISE 0 PM4388 TOCTL OCTAL T1 FRAMER 52 ...

Page 69

... The TLCLKRISE bit enables the transmit line interface to be updated on the rising TLCLK[x] edge. When TLCLKRISE is set to logic 1, TLD[x] is updated on the rising TLCLK[x] edge. When TLCLKRISE is set to logic 0, TLD[x] is updated on the falling TLCLK[x] edge. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 53 ...

Page 70

... ABCD expected to contain the A and B bits duplicated in the lower nibble (i.e. ABAB). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default EMODE[1] 1 EMODE[0] 1 Unused X ABXXEN 0 Unused X CECLK2M 0 CESFP 0 ESFP 0 PM4388 TOCTL OCTAL T1 FRAMER 54 ...

Page 71

... EFP[x] output pulses high during the first framing bit of the 12 frame SF or the 24 frame ESF. When ESFP is set to logic 0, the EFP[x] output pulses high during each framing bit (i.e. every 193 bits). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 55 ...

Page 72

... XBAS is disabled from generating framing. When FDIS is set to logic 0, XBAS is enabled to generate and insert the framing into the transmit data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X SIGAEN 0 TXSIGA 0 FDIS 0 FBITBYP 0 CRCBYP 0 FDLBYP 0 PM4388 TOCTL OCTAL T1 FRAMER 56 ...

Page 73

... When FDLBYP is set to logic 1, the input FDL bit is re- inserted into the output data stream. When FDLBYP is set to logic 0, the XBAS is allowed to generate the output FDL bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 57 ...

Page 74

... TJAT FIFO output clock is driven with the internal smooth 1.544MHz clock selected by the CTCLKSEL and SMCLKO bits. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default HSBPSEL 0 Unused X Unused X OCLKSEL 0 PLLREF1 0 PLLREF0 1 CTCLKSEL 0 SMCLKO 0 PM4388 TOCTL OCTAL T1 FRAMER 58 ...

Page 75

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Source of PLL Reference Transmit clock used by XBAS when the Clock Slave egress modes are active. (either the 1.544MHz CECLK or the gapped clock derived from the 2.048MHz CECLK as selected by CECLK2M) CECLK input RLCLK[x] input CTCLK input PM4388 TOCTL OCTAL T1 FRAMER 59 ...

Page 76

... SMCLKO =0 CECLK2M =0 EMODE[1: HSBPSEL =0 OCLKSEL =0 CTCLKSEL =0 SMCLKO =0 CECLK2M =0 PM4388 TOCTL OCTAL T1 FRAMER Transmit Line Clock Options When PLLREF[1:0]=0X, TLCLK[ jitter- attenuated clock referenced to CECLK. This is the default. When PLLREF[1:0]=10, TLCLK[ jitter- attenuated clock referenced to RLCLK[x] When PLLREF[1:0]=11, TLCLK[ jitter- ...

Page 77

... SMCLKO =0 CECLK2M =1 EMODE[1: HSBPSEL =1 OCLKSEL =0 CTCLKSEL =0 SMCLKO =0 CECLK2M =0 PM4388 TOCTL OCTAL T1 FRAMER Transmit Line Clock Options When PLLREF[1:0]=00, TLCLK[ jitter- attenuated clock referenced to the internally gapped CECLK. See note 1. When PLLREF[1:0]=01, TLCLK[ jitter- attenuated clock referenced to CECLK. See note 2. ...

Page 78

... See note 3 EMODE[1: HSBPSEL =0 FIFOBYP =1 OCLKSEL =X PLLREF[1:0] =XX CTCLKSEL =0 SMCLKO =0 CECLK2M =0 PM4388 TOCTL OCTAL T1 FRAMER Transmit Line Clock Options When OCLKSEL = 1, TLCLK[x] = CTCLK. When OCLKSEL = 0, SMCLKO = 1, and CTCLKSEL =0, then TLCLK[x] = CTCLK÷8. When OCLKSEL = 0, SMCLKO = 1, and CTCLKSEL =1, then TLCLK[x] = XCLK÷24. 62 ...

Page 79

... OCLKSEL =0 CTCLKSEL =0 SMCLKO =0 CECLK2M =0 EMODE[1: HSBPSEL =0 FIFOBYP =0 CECLK2M =0 PLLREF[1:0] =XX PM4388 TOCTL OCTAL T1 FRAMER Transmit Line Clock Options The setting PLLREF[1:0]=00 is reserved and should not be used. When PLLREF[1:0]=01, TLCLK[ jitter- attenuated clock referenced to CECLK. When PLLREF[1:0]=10, TLCLK[ jitter- attenuated clock ...

Page 80

... If internal gapping of CECLK is desired, CECLK2M must be set as well. Figure 13 illustrates the various bit setting options, with the reset condition highlighted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 64 ...

Page 81

... Smooth 1.544MHz 00 TJAT 01 PLL PLLREF[1:0] 10 24X reference clock for jitter attenuation 11 0 ÷ CTCLKSEL 0 1 HSBPSEL PM4388 TOCTL OCTAL T1 FRAMER 1 TLCLK[x] 0 FIFOBYP OCLKSEL "Jitter-free" 1 SMCLKO 1.544MHz "High-speed" clock for FRMR (=12.352MHz) "High-speed" clock for ELST, SIGX, TPSC & RPSC (•6x ...

Page 82

... Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default PMON 0 IBCD 0 FRMR 0 PRGD 0 ELST 0 RDLC 0 RBOC 0 ALMI 0 PM4388 TOCTL OCTAL T1 FRAMER 66 ...

Page 83

... Reading these registers does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X PRTY 0 TJAT 0 RJAT 0 Unused X Unused X TDPR 0 SIGX 0 PM4388 TOCTL OCTAL T1 FRAMER 67 ...

Page 84

... When TXMFP is set to logic 1, the mimic PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X LINELB 0 Reserved 0 DDLB 0 TXMFP 0 TXDIS 0 PM4388 TOCTL OCTAL T1 FRAMER DDLB and LINELB are 68 ...

Page 85

... The TXDIS bit provides a method of suppressing the output of the basic transmitter. When TXDIS is set to logic 1, the digital output of XBAS is disabled by forcing it to logic 0. When TXDIS is set to logic 0, the digital output of XBAS is not suppressed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 69 ...

Page 86

... The PMCTST bit is logically "ORed" with the IOTST bit, and is cleared by setting CSB to logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default A_TM[9] X A_TM[8] X A_TM[7] X PMCTST X DBCTRL 0 IOTST 0 HIZDATA 0 HIZIO 0 PM4388 TOCTL OCTAL T1 FRAMER 70 ...

Page 87

... The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is also held in a high- impedance state which inhibits microprocessor read cycles. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 71 ...

Page 88

... The chip identification bits, TYPE[2:0], are set to binary 010 representing the TOCTL. Writing to this register causes all performance monitor and pattern generator/detector counters to be updated simultaneously. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default TYPE[2] 0 TYPE[1] 1 TYPE[0] 0 ID[4] 0 ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 0 PM4388 TOCTL OCTAL T1 FRAMER 72 ...

Page 89

... A hardware reset clears the RESET bit, thus deasserting the software reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X RESET 0 PM4388 TOCTL OCTAL T1 FRAMER 73 ...

Page 90

... The INTx bit will be high if the xth T1 framer (the T1 framer corresponding to the input pin RLCLK[x]) causes the INTB pin to transition low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default INT8 0 INT7 0 INT6 0 INT5 0 INT4 0 INT3 0 INT2 0 INT1 0 PM4388 TOCTL OCTAL T1 FRAMER 74 ...

Page 91

... T1 loopback codes in an Nx56kbps fractional T1 signal. This bit has no effect when UNF_DET is set to logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Nx56k_GEN 0 Nx56k_DET 0 RXPATGEN 0 UNF_GEN 0 UNF_DET 0 PM4388 TOCTL OCTAL T1 FRAMER 75 ...

Page 92

... PRGD will search for the pattern in all 193 bits of the egress or receive stream, depending on the setting of RXPATGEN. The UNF_DET bit overrides any per-DS0 pattern detection specified in the TPSC or RPSC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 76 ...

Page 93

... FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. The UNDI bit is cleared after this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X OVRI 0 UNDI 0 PM4388 TOCTL OCTAL T1 FRAMER 77 ...

Page 94

... Configuration register is high, will also reset the FIFO. Upon reset of the TOCTL, the default value set to decimal 47 (2FH). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default N1[7] 0 N1[6] 0 N1[5] 1 N1[4] 0 N1[3] 1 N1[2] 1 N1[1] 1 N1[0] 1 PM4388 TOCTL OCTAL T1 FRAMER 78 ...

Page 95

... Writing to this register will reset the PLL and, if the SYNC bit is high, will also reset the FIFO. Upon reset of the TOCTL, the default value set to decimal 47 (2FH). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default N2[7] 0 N2[6] 0 N2[5] 1 N2[4] 0 N2[3] 1 N2[2] 1 N2[1] 1 N2[0] 1 PM4388 TOCTL OCTAL T1 FRAMER 79 ...

Page 96

... INTB pin. When OVRE or UNDE is set to logic 0, the FIFO error events are disabled from generating an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Reserved 1 CENT 0 UNDE 0 OVRE 0 SYNC 1 LIMIT 1 PM4388 TOCTL OCTAL T1 FRAMER 80 ...

Page 97

... This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 1, the PLL jitter attenuation is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 81 ...

Page 98

... FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. The UNDI bit is cleared after this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X OVRI 0 UNDI 0 PM4388 TOCTL OCTAL T1 FRAMER 82 ...

Page 99

... Configuration register is high, will also reset the FIFO. Upon reset of the TOCTL, the default value set to decimal 47 (2FH). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default N1[7] 0 N1[6] 0 N1[5] 1 N1[4] 0 N1[3] 1 N1[2] 1 N1[1] 1 N1[0] 1 PM4388 TOCTL OCTAL T1 FRAMER 83 ...

Page 100

... Writing to this register will reset the PLL and, if the SYNC bit is high, will also reset the FIFO. Upon reset of the TOCTL, the default value set to decimal 47 (2FH). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default N2[7] 0 N2[6] 0 N2[5] 1 N2[4] 0 N2[3] 1 N2[2] 1 N2[1] 1 N2[0] 1 PM4388 TOCTL OCTAL T1 FRAMER 84 ...

Page 101

... INTB pin. When OVRE or UNDE is set to logic 0, the FIFO error events are disabled from generating an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Reserved 1 CENT 0 UNDE 0 OVRE 0 SYNC 1 LIMIT 1 PM4388 TOCTL OCTAL T1 FRAMER 85 ...

Page 102

... This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 1, the PLL jitter attenuation is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 86 ...

Page 103

... T1 frame format output from the ELST. SETTING OR TO LOGIC RESERVED SETTING AND SHOULD NOT BE USED. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Reserved 0 Unused X Unused X Unused X Unused X Unused PM4388 TOCTL OCTAL T1 FRAMER 87 ...

Page 104

... If a slip has occurred and the SLIPD bit is a logic 0 then the slip was due to the frame buffer becoming empty. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X SLIPE 0 SLIPD 0 SLIPI 0 PM4388 TOCTL OCTAL T1 FRAMER 88 ...

Page 105

... One channel of trouble code data will always be corrupted if the register is written while the receiver is out of frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default PM4388 TOCTL OCTAL T1 FRAMER 89 ...

Page 106

... The ESF bit selects either extended superframe format or standard superframe format. A logic 1 in the ESF bit position selects ESF; a logic 0 selects SF. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default M2O[1] 0 M2O[0] 0 ESFFA 0 ESF 0 Reserved 0 Reserved 0 Unused X Unused X PM4388 TOCTL OCTAL T1 FRAMER 90 ...

Page 107

... DATA SHEET PMC-960840 Reserved: The reserved bits must be written with logic 0 for proper operation.. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 91 ...

Page 108

... When FERE is set to logic 0, any error in the framing bits does not generate an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X ACCEL 0 COFAE 0 FERE 0 BEEE 0 SFEE 0 MFPE 0 INFRE 0 PM4388 TOCTL OCTAL T1 FRAMER 92 ...

Page 109

... When INFRE is set to logic 1, the assertion or deassertion of the "inframe" state is allowed to generate an interrupt. When INFRE is set to logic 0, a change in the "inframe" state is disabled from generating an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 93 ...

Page 110

... INFRI status bit position indicates that no state change occurred. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default COFAI 0 FERI 0 BEEI 0 SFEI 0 MFPI 0 INFRI 0 MFP 0 INFR 0 PM4388 TOCTL OCTAL T1 FRAMER 94 ...

Page 111

... The interrupt and the status bit positions (COFAI, FERI, BEEI, SFEI, MFPI, and INFRI) are cleared to logic 0 when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 95 ...

Page 112

... CICLKA is set high on a rising edge of CICLK, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X XCLKA 0 CECLKA 0 CTCLKA 0 CICLKA 0 RLCLKA 0 PM4388 TOCTL OCTAL T1 FRAMER 96 ...

Page 113

... The CECLK active bit monitors for low to high transitions on the CECLK input. CECLKA is set high on a rising edge of CECLK, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 97 ...

Page 114

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X IDLE 0 AVC 0 BOCE 0 PM4388 TOCTL OCTAL T1 FRAMER 98 ...

Page 115

... BOC[0] corresponds to the LSB. An all-ones setting indicates that no valid BOC has been received. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default IDLEI 0 BOCI 0 BOC[5] 1 BOC[4] 1 BOC[3] 1 BOC[2] 1 BOC[1] 1 BOC[0] 1 PM4388 TOCTL OCTAL T1 FRAMER 99 ...

Page 116

... A logic 1 in the ESF bit position selects ESF; a logic 0 bit selects SF. Reserved: The reserved bits must be written with logic 0 for proper operation.. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X ESF 0 Reserved 0 Reserved 0 Unused X Unused X PM4388 TOCTL OCTAL T1 FRAMER 100 ...

Page 117

... Yellow, Red, and AIS CFA's can be enabled to generate an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X FASTD 0 ACCEL 0 YELE 0 REDE 0 AISE 0 PM4388 TOCTL OCTAL T1 FRAMER 101 ...

Page 118

... CFA state are cleared to logic 0 when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X YELI 0 REDI 0 AISI 0 YEL 0 RED 0 AIS 0 PM4388 TOCTL OCTAL T1 FRAMER 102 ...

Page 119

... When AISD is logic 1, a valid AIS signal was present during the last 60 ms interval. When AISD is logic 0, the AIS signal was absent during the last 60 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X REDD X YELD X AISD X PM4388 TOCTL OCTAL T1 FRAMER 103 ...

Page 120

... PCM data stream is not logic 0 for 126 or fewer times. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 104 ...

Page 121

... SIGNALING Control byte are enabled. When the PCCE bit is set to logic 0, the per-DS0 functions are disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X IND 0 PCCE 0 PM4388 TOCTL OCTAL T1 FRAMER 105 ...

Page 122

... Register should be polled until the BUSY bit goes low before another µP access request is initiated. A µP access request is typically completed within 640 ns. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default BUSY 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X PM4388 TOCTL OCTAL T1 FRAMER 106 ...

Page 123

... R/WB is set to a logic 1, a read from the internal TPSC register is requested; when R/WB is set to a logic 0, a write to the internal TPSC register is requested. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default R/ PM4388 TOCTL OCTAL T1 FRAMER 107 ...

Page 124

... Egress Control byte for Channel 23 18H Egress Control byte for Channel 24 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default PM4388 TOCTL OCTAL T1 FRAMER 108 ...

Page 125

... SIGNALING Control byte for Channel 23 48H SIGNALING Control byte for Channel 24 The bits within each control byte are allocated as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 109 ...

Page 126

... Effect on PCM Channel Data PCM Channel data is unchanged All 8 bits of the PCM channel data are inverted Only the MSB of the PCM channel data is inverted (SIGN bit inversion) All bits EXCEPT the MSB of the PCM channel data is inverted (Magnitude inversion) PM4388 TOCTL OCTAL T1 FRAMER 110 ...

Page 127

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 X Channel data is not included in test pattern 1 Channel data is routed to PRGD and compared against expected test pattern 0 Channel data is overwritten with PRGD test pattern PM4388 TOCTL OCTAL T1 FRAMER 111 ...

Page 128

... GTE Zero Code Suppression (Bit all zero channel byte is replaced by a one, except in signaling frames where bit 7 is forced to a one.) Bell Zero Code Suppression (Bit all zero channel byte is replaced by a one.) PM4388 TOCTL OCTAL T1 FRAMER 112 ...

Page 129

... ED[x] when the IDLE_DS0 bit in the Egress Control byte is set to a logic 1. The IDLE Code is transmitted from MSB (IDLE7) to LSB (IDLE0). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default IDLE7 IDLE6 IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0 PM4388 TOCTL OCTAL T1 FRAMER 113 ...

Page 130

... Signaling Control byte or ESIG[x], respectively, are inserted into the A and B signaling bit positions of every second superframe that is transmitted assumed that C=A and D=B. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default SIGC0 SIGC1 Unused Unused PM4388 TOCTL OCTAL T1 FRAMER 114 ...

Page 131

... Transmit Data register is transmitted. The FIFO is then reset. All data in the FIFO will PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default FLGSHARE 1 FIFOCLR 0 Reserved 0 Unused X EOM 0 ABT 0 CRC PM4388 TOCTL OCTAL T1 FRAMER 115 ...

Page 132

... If FLGSHARE is logic 1, then the opening and closing flags between successive frames are shared. If FLGSHARE is logic 0, then separate closing and opening flags are inserted between successive frames. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 116 ...

Page 133

... The value of UTHR[6:0] must always be greater than the value of LINT[6:0] unless both values are equal to 00H. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X UTHR[6] 1 UTHR[5] 0 UTHR[4] 0 UTHR[3] 0 UTHR[2] 0 UTHR[1] 0 UTHR[0] 0 PM4388 TOCTL OCTAL T1 FRAMER 117 ...

Page 134

... The value of LINT[6:0] must always be less than the value of UTHR[6:0] unless both values are equal to 00H. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X LINT[6] 0 LINT[5] 0 LINT[4] 0 LINT[3] 0 LINT[2] 1 LINT[1] 1 LINT[0] 1 PM4388 TOCTL OCTAL T1 FRAMER 118 ...

Page 135

... INTB. If FULLE is a logic 0, a transition to logic 1 on FULLI will not generate an interrupt on INTB. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Reserved 0 FULLE 0 OVRE 0 UDRE 0 LFILLE 0 PM4388 TOCTL OCTAL T1 FRAMER 119 ...

Page 136

... DATA SHEET PMC-960840 Reserved: This bit should be set to logic 0 for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 120 ...

Page 137

... Transmit Data register. OVRI will assert INTB logic 1 if OVRE is programmed to logic 1. OVRI is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X FULL X BLFILL X Reserved X FULLI X OVRI X UDRI X LFILLI X PM4388 TOCTL OCTAL T1 FRAMER 121 ...

Page 138

... The FULL bit reflects the current condition of the TDPR FIFO. If FULL is a logic 1, the TDPR FIFO already contains 128-bytes of data and can accept no more. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 122 ...

Page 139

... The TD[7:0] bits contain the data to be transmitted on the data link. Data written to this register is serialized and transmitted (TD[0] is transmitted first). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default TD[7] X TD[6] X TD[5] X TD[4] X TD[3] X TD[2] X TD[1] X TD[0] X PM4388 TOCTL OCTAL T1 FRAMER 123 ...

Page 140

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Reserved 0 Unused X Unused X Unused X DSEL1 0 DSEL0 0 ASEL1 0 ASEL0 0 ACTIVATE Code ASEL1 ASEL0 PM4388 TOCTL OCTAL T1 FRAMER CODE LENGTH 5 bits 6 (or 3*) bits 7 bits 8 (or 4*) bits 124 ...

Page 141

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default LBACP 0 LBDCP 0 LBAE 0 LBDE 0 LBAI 0 LBDI 0 LBA 0 LBD 0 PM4388 TOCTL OCTAL T1 FRAMER 125 ...

Page 142

... A logic 1 in these bit positions indicate the presence of that code has been detected; a logic 0 in these bit positions indicate the absence of that code. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 126 ...

Page 143

... Note that bit ACT7 corresponds to the first code bit received. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default ACT7 0 ACT6 0 ACT5 0 ACT4 0 ACT3 0 ACT2 0 ACT1 0 ACT0 0 PM4388 TOCTL OCTAL T1 FRAMER 127 ...

Page 144

... Note that bit DACT7 corresponds to the first code bit received. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default DACT7 0 DACT6 0 DACT5 0 DACT4 0 DACT3 0 DACT2 0 DACT1 0 DACT0 0 PM4388 TOCTL OCTAL T1 FRAMER 128 ...

Page 145

... The ESF bit selects either extended superframe format standard superframe formats. A logic 1 in the ESF bit position selects ESF; a logic 0 bit selects SF. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Reserved 0 COSS 0 SIGE 0 Reserved 0 Reserved 0 ESF 0 IND 0 PCCE 0 PM4388 TOCTL OCTAL T1 FRAMER 129 ...

Page 146

... The PCCE bit enables the per-DS0 functions. When the PCCE bit is set to a logic 1, bit fixing and signaling debouncing are performed on a per-DS0 basis. When the PCCE bit is logic 0, the per-DS0 functions are disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 130 ...

Page 147

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X COSS 0 Unused X Unused X Unused X Unused X Unused X Unused X PM4388 TOCTL OCTAL T1 FRAMER 131 ...

Page 148

... A µP access request is typically completed within 640 ns. The bits in this register are valid when the COSS bit is a logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default BUSY 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X PM4388 TOCTL OCTAL T1 FRAMER 132 ...

Page 149

... These bits are cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default COSS[24] X COSS[23] X COSS[22] X COSS[21] X COSS[20] X COSS[19] X COSS[18] X COSS[17] X PM4388 TOCTL OCTAL T1 FRAMER 133 ...

Page 150

... The bits in this register are valid when the COSS bit is a logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default R/ PM4388 TOCTL OCTAL T1 FRAMER 134 ...

Page 151

... These bits are cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default COSS[16] X COSS[15] X COSS[14] X COSS[13] X COSS[12] X COSS[11] X COSS[10] X COSS[9] X PM4388 TOCTL OCTAL T1 FRAMER 135 ...

Page 152

... Address/Control register, initiating the request. After 640 ns, this register will contain the requested data bits. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default PM4388 TOCTL OCTAL T1 FRAMER 136 ...

Page 153

... The channel registers are allocated within the SIGX as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default COSS[8] X COSS[7] X COSS[6] X COSS[5] X COSS[4] X COSS[3] X COSS[2] X COSS[1] X PM4388 TOCTL OCTAL T1 FRAMER 137 ...

Page 154

... Channel 23 Per-DS0 Configuration Data 57H Channel 24 Per-DS0 Configuration Data 58-5FH Ignored The bits within each channel register byte are allocated as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 138 ...

Page 155

... If the state was not the same, the current state (accessible via these registers) is not changed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Unused Unused Unused Unused PM4388 TOCTL OCTAL T1 FRAMER 139 ...

Page 156

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Bit Timeslot Mask F0H 17 F0H F0H F0H PM4388 TOCTL OCTAL T1 FRAMER SIGX Bit Address Mask 10H 0FH 11H 0FH   16H 0FH 17H 0FH Reserved 140 ...

Page 157

... Debouncing requires that the signaling bits be in the same state for two successive superframes before the signaling bits are changed to that state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Unused Unused Unused Unused Unused FIX POL DEB PM4388 TOCTL OCTAL T1 FRAMER 141 ...

Page 158

... Egress Control byte. The bits are encoded as follows: ZCS1 ZCS0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default MTRK 0 Reserved 0 Reserved 0 ESF 0 Reserved 0 Reserved 0 ZCS1 0 ZCS0 0 Zero Code Suppression Format 0 None PM4388 TOCTL OCTAL T1 FRAMER 142 ...

Page 159

... GTE Zero Code Suppression (Bit all zero channel byte is replaced by a one, except in signaling frames where bit 7 is forced to a one.) 0 Reserved (do not use) 1 Bell Zero Code Suppression (Bit all zero channel byte is replaced by a one.) PM4388 TOCTL OCTAL T1 FRAMER 143 ...

Page 160

... ESF format. When XYEL is set to logic 0, XBAS is disabled from generating the Yellow alarm. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X XYEL 0 Reserved 0 PM4388 TOCTL OCTAL T1 FRAMER 144 ...

Page 161

... EN bit is set, and should be cleared to logic 0 when the EN bit is cleared. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X CL1 0 CL0 0 PM4388 TOCTL OCTAL T1 FRAMER 145 ...

Page 162

... Codes bits in length may be accommodated by treating them as half of a double-sized code (i.e. a 3-bit code would use the 6-bit code length setting). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Code Length PM4388 TOCTL OCTAL T1 FRAMER 146 ...

Page 163

... When the TOCTL is reset, the contents of this register are not affected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default IBC7 X IBC6 X IBC5 X IBC4 X IBC3 X IBC2 X IBC1 X IBC0 X PM4388 TOCTL OCTAL T1 FRAMER 147 ...

Page 164

... The XFER bit is cleared (acknowledged) by reading this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X INTE 0 XFER 0 OVR 0 PM4388 TOCTL OCTAL T1 FRAMER 148 ...

Page 165

... When the TOCTL is reset, the contents of the PMON count registers are unknown until the first latching of performance data is performed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 149 ...

Page 166

... Bit Error event is defined as a CRC-6 error in ESF format framing bit error in SF format. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default BEE7 X BEE6 X BEE5 X BEE4 X BEE3 X BEE2 X BEE1 X BEE0 X PM4388 TOCTL OCTAL T1 FRAMER 150 ...

Page 167

... A Bit Error event is defined as a CRC-6 error in ESF format framing bit error in SF format. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X BEE11 X BEE10 X BEE9 X BEE8 X PM4388 TOCTL OCTAL T1 FRAMER 151 ...

Page 168

... These registers contain the lower eight bits of the 9-bit Framing Bit Error event counter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default FER7 X FER6 X FER5 X FER4 X FER3 X FER2 X FER1 X FER0 X PM4388 TOCTL OCTAL T1 FRAMER 152 ...

Page 169

... These registers contain the upper bit of the 9-bit Framing Bit Error event counter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X FER8 X PM4388 TOCTL OCTAL T1 FRAMER 153 ...

Page 170

... Bit 0 R These registers contain the value of the 5 bit Out Of Frame event counter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X OOF4 X OOF3 X OOF2 X OOF1 X OOF0 X PM4388 TOCTL OCTAL T1 FRAMER 154 ...

Page 171

... These registers contain the value of the 3 bit counter accumulating Change of Frame Alignment events. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X COFA2 X COFA1 X COFA0 X PM4388 TOCTL OCTAL T1 FRAMER 155 ...

Page 172

... The RPSC per-channel functions overwrite the data after the ELST, and thus overwrite the ELST trouble code when the framer is OOF. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X IND 0 PCCE 0 PM4388 TOCTL OCTAL T1 FRAMER 156 ...

Page 173

... Register should be polled until the BUSY bit goes low before another µP access request is initiated. A µP access request is typically completed within 640 ns. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default BUSY 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X PM4388 TOCTL OCTAL T1 FRAMER 157 ...

Page 174

... R/WB is set to a logic 1, a read from the internal RPSC register is requested; when R/WB is set to a logic 0, a write to the internal RPSC register is requested. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default R/ PM4388 TOCTL OCTAL T1 FRAMER 158 ...

Page 175

... The functions are allocated within the registers as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default PM4388 TOCTL OCTAL T1 FRAMER 159 ...

Page 176

... Signaling Trunk Conditioning byte for Channel 23 48H Signaling Trunk Conditioning byte for Channel 24 The bits within each control byte are allocated as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 160 ...

Page 177

... Effect on PCM Channel Data 0 PCM Channel data is unchanged 0 All 8 bits of the PCM channel data are inverted 1 Only the MSB of the PCM channel data is inverted (SIGN bit inversion) 1 All bits EXCEPT the MSB of the PCM channel data is inverted (Magnitude inversion) PM4388 TOCTL OCTAL T1 FRAMER 161 ...

Page 178

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 X Channel data is not included in test pattern 0 Channel data is routed to PRGD and compared against expected test pattern 1 Channel data is overwritten with PRGD test pattern PM4388 TOCTL OCTAL T1 FRAMER 162 ...

Page 179

... ID[x] when the DTRKC bit in the Ingress Control Byte is set to a logic 1. The Data Trunk Conditioning Code is transmitted from MSB (DTRK7) to LSB (DTRK0). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function DTRK7 DTRK6 DTRK5 DTRK4 DTRK3 DTRK2 DTRK1 DTRK0 PM4388 TOCTL OCTAL T1 FRAMER 163 ...

Page 180

... ISIG[x] when the STRKC bit is set to a logic 1. The Signaling Trunk Conditioning Code is placed in least significant nibble of the channel byte. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default STRKC Unused Unused Unused PM4388 TOCTL OCTAL T1 FRAMER 164 ...

Page 181

... Setting the Match Enable (MEN) bit to logic 1 enables the detection and storage in the RDLC FIFO of only those packets whose first data byte PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Reserved 0 MEN PM4388 TOCTL OCTAL T1 FRAMER 165 ...

Page 182

... Match Register, and the two least significant bits of the universal all ones address when performing the address comparison. Reserved: This register bit should be set to logic 0 for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 166 ...

Page 183

... The contents of the Interrupt Control Register should only be changed when the EN bit in the RDLC Configuration Register is logic 0. This prevents any erroneous interrupt generation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default INTE 0 INTC[6] 0 INTC[5] 0 INTC[4] 0 INTC[3] 0 INTC[2] 0 INTC[1] 0 INTC[0] 0 PM4388 TOCTL OCTAL T1 FRAMER 167 ...

Page 184

... INTR may always be forced low by setting the EN bit low in the RDLC Configuration register, disabling the RDLC setting the TR bit high in the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default FE X OVR X COLS X PKIN X PBS[2] X PBS[1] X PBS[0] X INTR X PM4388 TOCTL OCTAL T1 FRAMER 168 ...

Page 185

... CRC error. The packet was received in error. The data byte read from the FIFO is the last byte of a normally terminated packet with a CRC error and a non-integer number of bytes. The packet was received in error. PM4388 TOCTL OCTAL T1 FRAMER 169 ...

Page 186

... The FIFO buffer empty (FE) bit is set to logic 1 when the last RDLC FIFO buffer entry is read. The FE bit goes to logic 0 when the FIFO is loaded with new data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 170 ...

Page 187

... When an overrun is detected, an interrupt is generated and the FIFO buffer is held cleared until the RDLC Status Register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default RD[7] X RD[6] X RD[5] X RD[4] X RD[3] X RD[2] X RD[1] X RD[0] X PM4388 TOCTL OCTAL T1 FRAMER 171 ...

Page 188

... FIFO. PA[0] corresponds to the first received bit of the data link message. The MM bit in the Configuration Register is used mask off PA[1:0] during the address comparison. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default PA[7] 1 PA[6] 1 PA[5] 1 PA[4] 1 PA[3] 1 PA[2] 1 PA[1] 1 PA[0] 1 PM4388 TOCTL OCTAL T1 FRAMER 172 ...

Page 189

... FIFO. SA[0] corresponds to the first received bit data link message. The MM bit in the Configuration Register is used mask off SA[1:0] during the address comparison. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default SA[7] 1 SA[6] 1 SA[5] 1 SA[4] 1 SA[3] 1 SA[2] 1 SA[1] 1 SA[0] 1 PM4388 TOCTL OCTAL T1 FRAMER 173 ...

Page 190

... HDLC packets currently being transmitted. When the register is written with 111111, the XBOC is disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X BC[5] 1 BC[4] 1 BC[3] 1 BC[2] 1 BC[1] 1 BC[0] 1 PM4388 TOCTL OCTAL T1 FRAMER 174 ...

Page 191

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default PDR[1] 0 PDR[0] 0 QRSS TINV 0 RINV 0 AUTOSYNC 1 MANSYNC 0 PDR#2 Pattern Receive Error Count Bit Count PM4388 TOCTL OCTAL T1 FRAMER PDR#3 PDR#4 Pattern Pattern Receive Receive (MSB) Error Error Count Count (MSB) Bit Bit Count Count (MSB) 175 ...

Page 192

... PRGD will not initiate a search for the new pattern alignment. MANSYNC: The MANSYNC bit is used to manually initiate a resynchronization of the pattern detector. A low to high transition on MANSYNC initiates the resynchronization. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 176 ...

Page 193

... When SYNCV is a logic 1 the pattern detector is synchronized (the pattern detector has observed at least 48 consecutive error free bit periods). When PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default SYNCE 0 BEE 0 XFERE 0 SYNCV X SYNCI X BEI X XFERI X OVR X PM4388 TOCTL OCTAL T1 FRAMER 177 ...

Page 194

... OVR is set to logic 0 when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4388 TOCTL OCTAL T1 FRAMER 178 ...

Page 195

... PL[4:0] determine the length of the generated pseudo random or repetitive pattern. The pattern length is equal to the value of PL[4: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X PL[4] 0 PL[3] 0 PL[2] 0 PL[1] 0 PL[0] 0 PM4388 TOCTL OCTAL T1 FRAMER 179 ...

Page 196

... PT[4:0] determine the feedback tap position of the generated pseudo random pattern. The feedback tap position is equal to the value of PT[4: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X PT[4] 0 PT[3] 0 PT[2] 0 PT[1] 0 PT[0] 0 PM4388 TOCTL OCTAL T1 FRAMER 180 ...

Page 197

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X EVENT 0 EIR[2] 0 EIR[1] 0 EIR[0] 0 PM4388 TOCTL OCTAL T1 FRAMER 181 ...

Page 198

... PRGD in only a few channels, this delay can be significant, since PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 7 error rate at 64kbps is one error every 156 seconds. PM4388 TOCTL OCTAL T1 FRAMER 182 ...

Page 199

... Register 068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H: PRGD Pattern Insertion #1 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default PI[7] 0 PI[6] 0 PI[5] 0 PI[4] 0 PI[3] 0 PI[2] 0 PI[1] 0 PI[0] 0 PM4388 TOCTL OCTAL T1 FRAMER 183 ...

Page 200

... Register 069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H: PRGD Pattern Insertion #2 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default PI[15] 0 PI[14] 0 PI[13] 0 PI[12] 0 PI[11] 0 PI[10] 0 PI[9] 0 PI[8] 0 PM4388 TOCTL OCTAL T1 FRAMER 184 ...

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