SDA5550M Micronas, SDA5550M Datasheet
SDA5550M
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SDA5550M Summary of contents
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... MICRONAS Edition Sept. 10, 2004 6251-556-3DS DATA SHEET SDA 55xx TVText Pro MICRONAS ...
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... FC Check Select 16 2.2.4.2. Interrupts 16 2.2.4.3. VBI Buffer and Memory Organization 18 2.2.5. Related Registers 18 2.2.5.1. RAM Registers 18 2.2.5.1.1. Field Parameters 19 2.2.5.1.2. Line Parameters 19 2.2.6. Recommended Parameter Settings 20 2.2.7. Microcontroller 20 2.2.8. Architecture 20 2.2.8.1. CPU Hardware 20 2.2.8.1.1. Instruction Decoder 20 2.2.8.1.2. Program Control Section 20 2.2.8.1.3. Internal Data RAM 20 2.2.8.1.4. Arithmetic/Logic Unit (ALU) 21 2.2.8.1.5. Boolean Processor 2 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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... Interrupt Return 42 2.3.13. Interrupt Nesting 42 2.3.14. External Interrupts 43 2.3.15. Extension of Standard 8051 Interrupt Logic 44 2.3.16. Interrupt Task Function 44 2.3.17. Power Saving Modes 44 2.3.18. Power-Save Mode Registers 45 2.3.19. Idle Mode 45 2.3.20. Power-down Mode 45 2.3.21. Power-save Mode 45 2.3.22. Slow-Down Mode 46 2.4. Reset 46 2.4.1. Reset Sources 46 2.4.2. Reset Filtering 46 2.4.3. Reset Duration 46 2.4.4. Registers Micronas Sept. 10, 2004; 6251-556-3DS SDA 55xx 3 ...
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... Timing 50 2.5.4.6. Interfacing Extended Memory 50 2.5.4.7. Application Examples 51 2.5.4.7.1. Sample Code 51 2.5.4.8. ROM and ROMless Version 51 2.6. UART 51 2.6.1. Operation Modes of the UART 51 2.6.1.1. Mode 0 51 2.6.1.2. Mode 1 51 2.6.1.3. Mode 2 52 2.6.1.4. Mode 3 52 2.6.2. Multiprocessor Communication 53 2.7. General Purpose Timers/Counters 53 2.7.1. Timer/Counter 0: Mode Selection 53 2.7.1.1. Mode 0 4 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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... PWM 60 2.9.5. Cycle Time 61 2.9.6. Power-Down, Idle and Power-save Mode 61 2.9.7. Timer 62 2.9.8. Control Registers 63 2.10. Watchdog Timer 63 2.10.1. Input Clock 63 2.10.2. Starting 63 2.10.3. Refresh 63 2.10.4. WDT Reset 63 2.10.5. Power-down Mode 63 2.10.6. Time Period 64 2.10.7. WDT as General Purpose Timer 65 2.11. Analog Digital Converter (CADC) 65 2.11.1. Power-down and Wake-up Micronas Sept. 10, 2004; 6251-556-3DS SDA 55xx 5 ...
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... DRCS Characters 96 2.13.8.1. Memory Organization of DRCS Characters 100 2.13.9. Memory Organization 102 2.13.9.1. Character Display Area 102 2.13.9.2. CLUT Area 102 2.13.9.3. Global Display Word/Cursor 102 2.13.9.4. 1-bit/2-bit/4-bit DRCS Character 103 2.13.9.5. Overview on the SFR Registers 6 to 767 1023 d d Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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... Absolute Maximum Ratings 164 4.10.2. Recommended Operating Conditions 165 4.10.3. Characteristics 169 4.10.4. Timings 169 4.10.4.1. Sync 170 4.10.4.2. Program Memory Read Cycle 171 4.10.4.3. Data Memory Read Cycle 172 4.10.4.4. Data Memory Write Cycle 173 4.10.4.5. Blank/Cor 174 5. Applications 176 6. Data Sheet History Micronas Sept. 10, 2004; 6251-556-3DS SDA 55xx 7 ...
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... Hitex, Kleinhenz, iSystems, the Keil C51 Com- piler and TEDIpro OSD development SW by Tara Sys- tems. This support provided by Micronas leads to: – Shorter time to market – Re-usability of the SW also for future Micronas products – Target independent SW development based on ANSI C. – Verification and validation of SW before targeting and improved SW test concept – ...
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... Support of progressive and 100 Hz double scan – 3 × 4 bits RGB-DACs on chip – Free programmable pixel clock from 10 MHz to 32 MHz Micronas – Pixel clock independent from CPU clock – Multinorm H/V-display synchronization in master or slave mode 1.1.5. Acquisition Features – Multistandard digital data slicer – ...
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... Extension Unit M8051S Counter 0 Core Counter 1 Interrupt Controller Sept. 10, 2004; 6251-556-3DS DATA SHEET ADC Slicer Acquisition Acquisition interface XRAM SRAM 16Kx8bit Bus Arbiter Character ROM 16KX8 RAM/ROM Interface V Display logic H Display Generator CLUT BLANK/COR Display Regs FIFO DAC's Imran Hajimusa Micronas ...
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... ROM fix-programmed with the software P116 Note: Micronas delivers two types of PSDIP52 packages (-1, -2). The packages have slightly different outline dimensions, but are considered identical. See Outline Dimensions for PSDIP52-1 Package on page 144 and Outline Dimensions for PSDIP52-1 Package on page 144 ...
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... See Section 2.3.17. on page 44. 33. uC-Periph. 3MHz f Ports sys 33.33 MHz Sync 33. ADC 3MHz or 8.33 Slicer MHz ext.clk DG CLK_src CLUTs Display-FIFO DTO DAC f PIX (10 .. 32MHz) CLKE Sept. 10, 2004; 6251-556-3DS DATA SHEET ) is provided to the CPU Micronas ...
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... Related Registers Table 2–1: Related registers and bits Register Name Bit Name 7 6 PCLK1 PCLK0 PF[7:0] PCON SMOD PDS PSAVEX See Section 3. on page 110 for detailed register description. Micronas ), which PIX IDLS SD GF1 Sept. 10, 2004; 6251-556-3DS SDA 55xx PF[10:8] ...
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... The H/V synchronization for the slicer – The acquisition interface Sync Separation H/V-Sync Separation & Timing Data Separation Acquisition Interface FC-Check & D-PLL Ser/Par Converter Sept. 10, 2004; 6251-556-3DS DATA SHEET HS1_IR VS1_IR H-PLL L23_IR CC_IR to Memory Address Decoder Parameter Buffer Micronas ...
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... The teletext framing code (E4 measurement reference. The delay of the edges inside this code can be used to measure the group delay dis- Micronas tortion. The measurement is done during every teletext line and filtered over several lines. It can be detected whether the signal has positive, negative or no group delay distortions ...
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... Bytes should be reserved for every sliced data line lines of data (in full channel mode 314) have been send to memory no further data acquisition will take place until the next vertical pulse appears and the H-PLL is still locked. Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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... Send to memory ACQLP0 ACQLP1 Send to slicer after H-pulse ACQLP2 ACQLP3 ACQLP4 Send to memory Fig. 2–3: VBI Buffer: General Structure Micronas Field Parameters Field Parameters Field Parameters Field Parameters Field Parameters Field Parameters Field Status Information Field Status Information Field Status Information ...
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... See Section 3. on page 110 for detailed register description. 18 Bit Name ACQSTA VBIADR WTmr AVS DVS Bit Name ANOON GDPON GDNON STAB VDOK FIELD LEOFLI[11:8] Sept. 10, 2004; 6251-556-3DS DATA SHEET PWtmr AHS DHS IEX[1: FREON NOION FULL NOISE(1) GRDON GRDSIGN Micronas ...
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... FREON 0 NOION 0 DINCR 54559 FC1E 0 MLENGTH 1 ALENGTH 2 CLKDIV 0 NORM 0 FCSEL 0 VCR 0 MATCH 0 FC1 228 FC3 don’t care FC3MASK don’t care Micronas Bit Name FCSEL[1:0] ALENGTH[1:09 VPS WSS 39321 39321 ...
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... The ALU performs the arithmetic operations of add, subtract, multiply, divide, increment, decrement, BCD-decimal-add adjust and compare, and the logic operations like and, or, Sept. 10, 2004; 6251-556-3DS DATA SHEET instructions listed Micronas ...
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... PSW CY AC See Section 3. on page 110 for detailed register description. Micronas and OV flags generally reflect the status of the latest arithmetic operations. The CY flag is also the Boolean accumulator for bit operations. The P-flag always reflects the parity of the register ACC. F0 and F1 are general purpose flags which are pushed onto the stack as part of a PSW save (see Table 2– ...
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... Register Addressing R0 … R7 ACC (bit), DPTR Direct Addressing RAM (low part) Special Function Registers Register-indirect Addressing RAM (@R1, @R0, SP) Immediate Addressing Program Memory Base Register plus Index-Register Indirect Addressing Program Memory (@DPTR + A, @ Sept. 10, 2004; 6251-556-3DS DATA SHEET DPSEL[2:0] Micronas ...
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... PC) and index register, ACC. This mode facilitates accessing to look- up table resident in program memory. Micronas 2.2.9. Ports and I/O-Pins There are 34 Port pins available, out of which 24 are I/ O pins configured as three 8-bit wide ports P0, P1, and P3 ...
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... Port output TXD mode – – – – – – – – – – Port input RXD mode – – Micronas ...
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... MOV PX. CLR PX.Y 1) SET PX.Y 1) The instruction reads the port Byte (all 8 bits), modifies the addressed bit, then writes the new Byte back to the latch. Micronas Alternate Function 2 Function Function Port pin Read signal Write signal Port pin VS output voltage level at the pin. For example, a port bit might be used to drive the base of a transistor ‘ ...
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... Destination address for ACALL & AJMP will be within the same 2 KByte of the following instruction. rel – SJMP and all conditional jumps include an 8-bit offset Byte. Range is +127/-128 Bytes relative to first Byte of the follow- ing instruction. 26 RAM-location data memory Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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... INC DPTR MUL AB DIV Micronas Description Add register to Accumulator Add direct Byte to Accumulator Add indirect RAM to Accumulator Add immediate data to Accumulator Add register to Accumulator with Carry flag Add direct Byte to A with Carry flag Add indirect RAM to A with Carry flag ...
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... Rotate Accumulator left Rotate A left through the Carry flag Rotate Accumulator right Rotate A right through Carry flag Swap nibbles within the Accumulator Sept. 10, 2004; 6251-556-3DS DATA SHEET Byte Micronas ...
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... ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C Micronas Description Clear Carry flag Clear direct bit Set Carry flag Set direct bit Complement Carry flag Complement direct bit AND direct bit to Carry flag AND complement of direct bit to Carry OR direct bit to Carry flag ...
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... Exchange register with Accumulator Exchange direct Byte with Accumulator Exchange indirect RAM with Accumulator Exchange low-order digital indirect RAM with A Sept. 10, 2004; 6251-556-3DS DATA SHEET Byte Micronas ...
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... A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP Micronas Description Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative addr) Jump indirect relative to the DPTR ...
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... ADD ADD ADD ADD ADD ADD ADD JNB bit addr, code addr 2 ACALL code addr 1 RETI – 1 RLC A 2 ADDC A, #data 2 ADDC A, data addr 1 ADDC A, @R0 1 ADDC A, @R1 1 ADDC ADDC A, R1 Micronas ...
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... JNC 51 2 ACALL 52 2 ANL 53 3 ANL 54 2 ANL 55 2 ANL 56 1 ANL 57 1 ANL Micronas Table 2–16: Instruction opcodes in hexadecimal order Operands Hex Code code addr 5E code addr 5F data addr ...
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... MOV C, bit addr 1 INC DPTR 1 MUL AB – reserved – 2 MOV @R0, data addr 2 MOV @R1, data addr 2 MOV R0, data addr 2 MOV R1, data addr 2 MOV R2, data addr 2 MOV R3, data addr 2 MOV R4, data addr 2 MOV R5, data addr 2 MOV R6, data addr 2 MOV R7, data addr Micronas ...
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... C1 2 AJMP C2 2 CLR C3 1 CLR C4 1 SWAP C5 2 XCH C6 1 XCH C7 1 XCH Micronas Table 2–16: Instruction opcodes in hexadecimal order Operands Hex Code C, /bit addr C8 code addr C9 bit addr #data, code CC addr CD A, data addr, CE code addr CF @R0, #data, ...
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... FE 1 MOV FF 1 MOV 36 Operands A A, data addr A, @ @DPTR, A code addr – – A data addr, A @R0, A @R1, A R0, A R1, A R2, A R3, A R4, A R5, A R6, A R7, A Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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... IP1.x IEN0. 7 Note Fig. 2–4: Interrupt Handling Overview Micronas ing change of channel, two interrupts are generated by the WDT and PWM overflow in timer mode. Timer 0 and Timer 1 overflows are indicated by TCON(TF0) and TCON.(TF1). Interrupts are gener- ated following a rollover in their respective registers (except in Mode 3 when TCON(TH0) controls the Timer 1 interrupt) ...
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... ET1 EDV EAV EXX1 EDH EAH ECC EADW E24 EX21 Bit Name WTmr AVS DVS Sept. 10, 2004; 6251-556-3DS DATA SHEET EX1 ET0 EX0 EWT EXX0 EX6 EPW EX13 EX12 EX20 EX19 EX18 PWtmr AHS DHS IEX1 IEX0 Micronas ...
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... IP0 bit addressable IP1 See Section 3. on page 110 for detailed register description. Micronas different priority occur at the same time, the higher level interrupt will be serviced first. An interrupt cannot be interrupted by another interrupt of the same or a lower priority level. If two interrupts of the same priority level occur simul- taneously, the order in which the interrupts are ser- viced is determined by the scan order shown below ...
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... EADW 00CB Sept. 10, 2004; 6251-556-3DS DATA SHEET Interrupt Request Flag IE0 (TCON.1) TF0 (TCON.5) IE1 (TCON.3) TF1 (TCON.7) R1(SCON.0) and T1(SCON.1) ADC(CISR0.6) Reserved CISR1(IEX0) WTmr(CISR0.5) CISR1(IEX1) AVS(CISR0.4) DVS(CISR0.3) Reserved Reserved PWtmr(CISR0.2) CC(CISR1.7) AHS(CISR0.1) DHS(CISR0.0) Reserved Reserved Reserved Reserved L24(CISR0.7) ADW(CISR1.6) Micronas ...
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... The current instruction is neither a RETI nor a write either to one of Interrupt Enable registers or to one of the Interrupt Priority registers. Micronas Note: Active interrupts are only stored for one machine cycle result interrupt was active for one or more polling cycles but not ser- viced for one of the reasons given above, the interrupt will not be processed ...
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... Control of the external inter- rupts is provided in the TCON register. Table 2–22: Related register Register Name 7 6 TCON TF1 TR1 See Section 3. on page 110 for detailed register description. 42 Bit Name TF0 TR0 IE1 Sept. 10, 2004; 6251-556-3DS DATA SHEET IT1 IE0 IT0 Micronas ...
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... Minimum delay between the interrupts should be ensured by the software. If both the EXXxR and EXXxF are reset to 0, interrupt is disabled. External extra interrupts EX1 and EX2 are edge triggered interrupts only. Micronas Table 2–23: Interrupt combinations IT0 EX0R ...
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... Power-Save Mode Registers. The Table 3-25 lists the respective registers which con- trol or reflect the Power-Save Modes. A description is given below. Bit Name CADC WAKUP IDLS SD GF1 Sept. 10, 2004; 6251-556-3DS DATA SHEET SLI_ACQ DISP PERI Clk_src PLL_res PLLS GF0 PDE IDLE Micronas ...
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... ORL PCON,#01000000 B PDE must not be set. Micronas The instruction that sets bit PDS is the last instruction executed before going into power-down mode. Concurrent setting of the enable and the start bits does not set the device into the respective power sav- ing mode ...
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... After reset the DACs will output a fix value as defined by En_DGOut, which is reset to ‘0’. COR_BL is reset to a level indicating COR = ‘0’ and BLank = ‘1’. The microcontroller should initialize the display mem- ory and set the En_DGOut (OCD_Ctrl) bit. Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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... Long Jump instruction to the initialization routine. Fol- lowing reset, the CPU always begins execution at loca- tion ‘0000’. Locations ‘0003’ through ‘00CB’ are can be reserved for the interrupt-request service routines if required. Micronas Table 2–26: Program memory Interrupt Source External Interrupt 0 Timer 0 Overflow ...
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... Extended data memory. This decoding method has the advantage, that when copying data back and forth between on-chip RAM and off-chip RAM, there is no need to switch the memory banks Sept. 10, 2004; 6251-556-3DS DATA SHEET . 16 KBytes are implemented as on Note that this decoding H Micronas ...
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... MEXSP Reserved See Section 3. on page 110 for detailed register description. . Micronas These registers can be read and written through MOV instructions like any other SFR register. Except for the CB bits in MEX1 - which are read only - and can be written only by the MMU. During normal operation user must not write to the MEXSP register ...
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... A15 … A0. Stack operation signals, SAdd[6:0], SDataI[7:0], SDataO[7:0], SRd and SWr have the same timing as internal RAM signals. 2.5.4.6. Interfacing Extended Memory The address bits A19, A18, A17, A16 are used to decode extended memory. 2.5.4.7. Application Examples MOVC Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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... External ROM only. In the ROM version this pin is internally pulled high, indicat- ing that no external ROM is available. Fig. 2–6: Program Code Micronas 2.6. UART The serial port is full duplex, meaning it can transmit and receive simultaneously also receive-buffered, ...
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... SM2 bit can be used to check the validity of the stop bit mode 1 reception, if SM2 = 1, the receive inter- rupt will not be activated unless a valid stop bit is received. Bit Name SM2 REN TB8 Sept. 10, 2004; 6251-556-3DS DATA SHEET RB8 Ti RI Micronas ...
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... The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are not valid and should be ignored. Setting the run flag TR0 does not clear the registers. Micronas 2.7.1.2. Mode 1 Mode 1 is the same as mode 0, except that all 16 bits of the timer/counter 0 register are being used. ...
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... Register Name 7 6 TCON TF1 TR1 See Section 3. on page 110 for detailed register description. 54 Bit Name GATE Timer 1 Bit Name TF0 TR0 IE1 Sept. 10, 2004; 6251-556-3DS DATA SHEET C Timer IT1 IE0 IT0 Micronas ...
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... This is achieved by a divide by 4 chain, which divides the incoming frequency by 4 when and feeds the incoming signal directly to the counter when Micronas 2.8.3.3. Run When the counter is started (RUN bit reload value is automatically loaded into the 16 bit counter. ...
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... TCON (IE1 or IE0). While using this mode TCON (IT0 or IT1) must be set to 1 (edge triggered) and IRCON (EX1R or EX0R) must be set to 1 and IRCON(EX1F or EX0F) must be set to 0. For further information on interrupts please refer to Section 2.3. on page 37. Sept. 10, 2004; 6251-556-3DS DATA SHEET be switched to CRT Micronas ...
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... CRT_mincapl CRT_mincaph CRT_con0 OV PR CRT_con1 Reserved Reserved See Section 3. on page 110 for detailed register description. Micronas 2.8.5. Registers The CRT_rell and CRT_relh are the reload registers (SFR address B7 CRT_capl are the corresponding capture registers (SFR address BA CRT_mincaph (SFR Address BC mum capture registers ...
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... SD Ctr Ctr RISE FALL CAPTURE Int Compare Min_Cap Spike Supression Unit First Start Sept. 10, 2004; 6251-556-3DS DATA SHEET Time Res. Max Pulse Width 240 ns 15.73 ms 480 ns 31.46 ms 1920 ns 125.83 ms 3840 ns 251.66 ms 240 ns 15.73 ms 480 ns 31.46 ms 1920 ns 125.83 ms 3840 ns 251.66 ms Micronas ...
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... PWM14_0 and PWM14_1. PWM channels can be individually enabled by corresponding bits in the PWME register provided the PWM_Tmr bit is not set (timer mode start bit). Micronas 2.9.4. Functional Description 2.9.4.1. 8-bit PWM The base frequency bit resolution DA converter channel is derived from the overflow of a six bit counter ...
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... PWM_ f Counting Rate sys direct [MHz] [MHz] 0 33.33 16.66 0 8.33 8.33 0 33.33 8.33 0 8.33 4.16 1 33.33 33.33 1 8.33 8.33 0 33.33 16.66 0 8.33 8.33 0 33.33 8.33 0 8.33 4.16 1 33.33 33.33 1 8.33 8.33 Sept. 10, 2004; 6251-556-3DS DATA SHEET Base Cycle Full Cycle Time Time [µs] [µs] 3.84 15.37 7.68 30.73 7.68 30.73 15.37 61.46 1.92 7.68 7.68 30.73 15.37 983.4 30.7 1967 30.7 1967 61.4 3934 7.68 492 30.7 1967 Micronas ...
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... On reset the CISR0 (PWtmr) bit is initialized to 0, however if the counter overflows this bit might be set along with OV bit. However clearing OV bit does not clear the CISR0 (PWtmr) bit. There- fore the software must clear this bit before enabling the corresponding interrupt. Micronas Sept. 10, 2004; 6251-556-3DS SDA 55xx 61 ...
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... When any of the PWM channels is not used associ- ated compare register can be used as general purpose registers, except PWM_En and PWCOMPEXT14_0 bit 0 and 1. Bit Name PE[7:0] PC80_[7:0] PC81_[7:0] PC82_[7:0] PC83_[7:0] PC84_[7:0] PC85_[7:0] PC140_[7:0] PC141_[7:0] PCX140_[7:0] PCX141_[7:0 PWC_[7:0] Sept. 10, 2004; 6251-556-3DS DATA SHEET ) of 8 bit counter PWC_[13:8] Micronas ...
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... This double instruc- tion refresh minimize the chances of an unintentional reset of the watchdog timer. Once set, the WDT_ref bit is reset by the hardware after three machine cycles. Micronas A refresh causes WDT_low to reset to 00 the reload value to from WDT_rel to WDT_high. 128. The current wdt/ 2 ...
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... WDT_tmr bit, either timer is stopped (WTmr_strt). However it is possible to stop the timer (WTmr_strt) and toggle the bit (WDT_tmr) with the same instruc- tion. Sept. 10, 2004; 6251-556-3DS DATA SHEET P WDT 184.3 µ WDT_Rst WTmr__Ov/Int WDT_Tmr WDTREl_2 WDTREl_1 WDTREl_0 --- --- --- --- --- --- Micronas ...
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... PCON SMOD PDS See Section 3. on page 110 for detailed register description. Micronas 2.11.1. Power-down and Wake-up During idle mode it is required to reduce the power consumption dramatically. In order to do this for the controller ADC a special wake-up unit has been included. ...
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... SDV) and the size of the character dis- play area. The color and transparency of this area is defined by a color look up vector. See Section 2.13.7. on page 79). Border Character Display Area Variable count of character columns (33..64) t (HPR) H-period Sept. 10, 2004; 6251-556-3DS DATA SHEET V-Sync Delay (SDV) Variable Height (25 rows) Micronas ...
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... Hz 40 × 25 100 Hz 64 × 25 100 Hz Micronas Note that the Pixel clock (Pclk) must be appropriately selected to the nearest value in the registers Pclk 0 and Pclk 1. Table 2–42 serves as an example,. The freely pro- grammable Pixel clock between MHz makes it possible to adjust and fine tune the display as per application requirement ...
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... HPR[7:0] SDV[7:0] SDH[7:0] EHCR[7:0] BHCR[7:0] BVCR[7:0] EVCR[7:0] SND_V[2:0] ENETCLK ENERCLK H period - frame n H pulse Sept. 10, 2004; 6251-556-3DS DATA SHEET VSU[3:0] INT SNC VCS DVS PWtmr AHS VLR[9:8] HPR[11:8] SDV[9:8] SDH[11:8] BVCR[9:8] EVCR[9:8] SND_H[2:0] PA_7_Alt VS_OE O_E_P3_0 0 MAST DHS O_E_Pol Micronas ...
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... H 24 DISPOINT H + B40 × Micronas – Parallel Display Attributes – Single/Double Width/Height of Characters – Variable Flash Rate – Programmable Screen Size (25 Rows × 33 … 64 Columns) – Flexible Character Matrixes (HxV) 12 × 9 … 16 – 256 Dynamically Redefinable Characters in standard mode; ...
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... Remark DRCS characters are defined by the user different colors can be used within one DRCS; see also see Section 2.13.4.1. See also Section 2.13.4.4. See also Section 2.13.4.5. See also Section 2.13.4.5. See also Section 2.13.4.6. See also Section 2.13.7.4. See also Section 2.13.7.5. Micronas ...
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... CHAAC Description 0 Normal mode: Address range 0 - 767 d access ROM characters. 1 Enhanced mode: Address range 0 - 767 d access 1-bit DRCS characters. Micronas see also to 767 d is used used to d Sept. 10, 2004; 6251-556-3DS SDA 55xx Remark See also Section 2.13.7.5. See also Section 2.13.7.5. Only used for ROM characters and 1-bit DRCS characters ...
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... Boundary1 set to 816 d … Boundary1 set to 992 d Boundary1 set to 1008 d Description Boundary1 set to 768 d Boundary1 set to 784 d Boundary1 set to 800 d Boundary1 set to 816 d … Boundary1 set to 992 d Boundary1 set to 1008 d must be set to Sept. 10, 2004; 6251-556-3DS DATA SHEET a greater or a equal value Micronas than ...
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... To 768 927 2-bit DRCS characters d d 928 1023 4-bit DRCS characters d d Micronas 2.13.4.4. Flash The bit FLASH inside the character display word (CDW; see also Section 2.13.4.) is used to enable flash for a character. FLASH Description 0 Steady (flash disabled) 1 Flash See also Section 2.13.4. on page 70 / Character ...
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... Table 2–50: Character individual double width DW Bit Left Right Character Character See also Section 2.13.4. on page 70 / Character Display Word (CDW) Sept. 10, 2004; 6251-556-3DS DATA SHEET Display Micronas ...
Page 75
... CURHOR0 2 CURHOR1 3 CURHOR2 1 4 CURHOR3 5 CURVER0 6 CURVER1 7 CURVER2 Micronas see also Function Count of display columns in horizontal direc- tion Used to enable progressive scan mode. Reserved. Reserved. Enables cursor function. Horizontal pixel shift of cursor to character position Vertical pixel shift of cursor to character posi- tion Sept. 10, 2004 ...
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... Box1. Reserved. Color vector of border Used to define the overruling transparency levels for Box1. Sept. 10, 2004; 6251-556-3DS DATA SHEET Cross Reference See also Section 2.13.7. on page 79 See also Section 2.13.7.4. on page 86 --- See also Section 2.13.7.1. on page 83 See also Section 2.13.7.4. on page 86 Micronas ...
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... DRCSB1_3 7 4 DRCSB2_0 5 DRCSB2_1 6 DRCSB2_2 7 DRCSB2_3 Micronas Function Double height of the full screen Used to enable transparency of Box0. CLUT transparency of subCLUT0 can be overruled for destined pixels inside Box0. Used to define the overruling transparency levels for Box0. Defines vertical resolution of DRCS charac- ters. ...
Page 78
... CLUT. Defines the level of BLANK for the colors of the hardwired CLUT. Reserved. Sept. 10, 2004; 6251-556-3DS DATA SHEET Cross Reference See also Section 2.13.7.7. on page 95 See also Section 2.13.7. on page 79 See also Section 2.13.7.3. on page 85 See also Section 2.13.7.5. on page 88 See also Section 2.13.7.5. on page 88 --- Micronas ...
Page 79
... Cursor-Pixels which are shifted to a non-visible row are also not displayed on the screen. Micronas DISALH2 DISALH1 0 0 ...
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... Horizontal shift Not allowed CURVER1 CURVER0 Description 0 0 Vertical shift Vertical shift Vertical shift Vertical shift of 3 … Vertical shift Vertical shift of 15 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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... Table 2–57: Vertical character position of the cursor within the character matrix POS POS VER4 VER3 … See also Section 2.13.5. on page 75-Global Display Word (GDW) Micronas POS POS POS HOR2 HOR1 HOR0 ...
Page 82
... See also Section 2.13.5. on page 75-Global Display Word (GDW) For detailed information of CLUT access see Section 2.13.7.5. on page 88 82 column Description Used to select the subCLUT which is used for color look up of the cursor (0 … 7) Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 83
... In double height mode the user may want to start the processing of the display at row 12 and not at row 0. To decide this, three bits are used as a global attribute. Micronas BRDCOL2 BRDCOL1 BRDCOL0 0 ...
Page 84
... Row-No. 23 Row-No. 24 Row-No. 24 Full Screen Double Height: Rows 1-12 are displayed in double height. Row 0 is settled on top of display in normal height. Display Appearance: Memory organization: Row-No. 0 Row-No. 0 Row-No. 1 Row-No. 1 .... Row-No. 11 Row-No. 2 Row-No. 12 .... ... ... ... ... Row-No. 23 Row-No. 12 Row-No. 24 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 85
... X See also Section 2.13.5. on page 75-Global Display Word (GDW) Micronas Description Slow flash rate. The flash rate is derived from display V pulse. For 50 Hz systems Flash rate is approximately 0.5 Hz. Duty cycle is approximately 50%. Medium flash rate. The flash rate is derived from the V pulse. ...
Page 86
... Box transparency is enabled for BOX0 for following pixels: Background pixels of ROM characters 0 Box transparency is enabled for BOX0 for following pixels: Background pixels of 1-bit DRCS characters 1 Box transparency is enabled for BOX0 for following pixels: Background pixels of ROM characters Background pixels of 1-bit DRCS characters Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 87
... See also Section 2.13.5. on page 75-Global Display Word (GDW) Micronas GLBT0_BOX1 Description 0 Box transparency is disabled for BOX1. 1 Box transparency is enabled for BOX1 for following pixels: Foreground pixels of ROM characters 0 Box transparency is enabled for BOX1 for following pixels: Foreground pixels of 1-bit DRCS characters ...
Page 88
... Section 2.12.1. on page 66): COR = 1 BLANK = 0 Decides the polarity for COR and BLANK output for the hardwired CLUT entries 0-15 and the polarity of COR and BLANK during black clamp phase (See also Section 2.12.1. on page 66): COR = 1 BLANK = 1 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 89
... CLUTadress+0 CLUTadress+1 Fig. 2–13: RGB/Transparency Memory Format of CLUT Micronas The CLUT is divided in 8 subCLUTs with 8 entries for 1-bit DRCS and ROM characters. For 2-bit DRCS characters the CLUT is divided in 8 subCLUTs with 4 entries. For 4-bit DRCS characters the CLUT is divided in 4 subCLUTs with 16 different entries. ...
Page 90
... 07d Micronas ...
Page 91
... CLUTPOINT + CLUTPOINT + CLUTPOINT + CLUTPOINT + CLUTPOINT + Micronas CLUT No for Cursor CLUT No for 2-bit DRCS Character Entry No. Entry No ...
Page 92
... Software programmable 0 4 Software programmable 1 5 Software programmable 2 6 Software programmable 3 7 Software programmable Software programmable 1 9 Software programmable 2 10 Software programmable 3 11 Software programmable 0 12 Software programmable 1 13 Software programmable 2 14 Software programmable 3 15 Software programmable Micronas ...
Page 93
... Section 2.13.4.). 1 out of 8 color vectors can be selected as a foreground and background color vector by the character display word (CDW; see also Section 2.13.4. on page 70). Please notice Table 2–68 on page 90. Micronas CLUT No for Cursor CLUT No for 2-bit DRCS Character Entry No. ...
Page 94
... ROM characters are filled up 12 lines with background colored pixels. 13 lines 14 lines 15 lines 16 lines Sept. 10, 2004; 6251-556-3DS DATA SHEET CHAROM CHAROM Description lines lines lines lines lines lines lines lines Micronas ...
Page 95
... See also Section 2.13.5. on page 75-Global Display Word (GDW) Micronas Example for a “A” displayed in shadow mode: Within one character matrix shadowing is only pro- cessed for the pixels which are belonging to that char- acter matrix. Pixels of one character matrix can not generate a shadow inside a neighbored character matrix ...
Page 96
... The memory organization behaves the same for any other count of lines. 96 LINE0 LINE1 LINE2 LINE3 LINE4 LINE5 LINE6 LINE7 LINE8 LINE9 Fig. 2–15: Allocation of Pixels Inside the Character Matrix the CLUT, see Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 97
... CHAR 1 LINE 10 DRC1POINT PIXEL 8 H BIT 0 CHAR 2 LINE 0 DRC1POINT PIXEL 0 H BIT 0 … … … Micronas Bit6 Bit5 Bit4 CHAR 1 CHAR 1 CHAR 1 LINE 0 LINE 0 LINE 0 PIXEL 1 PIXEL 2 PIXEL 3 BIT 0 BIT 0 BIT 0 CHAR 1 CHAR 1 CHAR 1 LINE 0 LINE 0 LINE 0 ...
Page 98
... PIXEL 7 BIT 1 BIT 0 BIT 1 CHAR 1 CHAR 1 CHAR 1 LINE 0 LINE 0 LINE 0 PIXEL 10 PIXEL 11 PIXEL 11 BIT 1 BIT 0 BIT 1 CHAR 1 CHAR 1 CHAR 1 LINE 10 LINE 10 LINE 10 PIXEL 10 PIXEL 11 PIXEL 11 BIT 1 BIT 0 BIT 1 CHAR 2 CHAR 2 CHAR 2 LINE 0 LINE 0 LINE 0 PIXEL 2 PIXEL 3 PIXEL 3 BIT 1 BIT 0 BIT 1 Micronas ...
Page 99
... CHAR 1 LINE 10 DRC4POINT PIXEL 10 H BIT 0 CHAR 2 LINE 0 DRC4POINT PIXEL 0 H BIT 0 … … … Micronas Bit6 Bit5 Bit4 CHAR 1 CHAR 1 CHAR 1 LINE 0 LINE 0 LINE 0 PIXEL 0 PIXEL 0 PIXEL 0 BIT 1 BIT 2 BIT 3 CHAR 1 CHAR 1 CHAR 1 LINE 0 LINE 0 LINE 0 ...
Page 100
... XRAM as shown in Table 2–78 Display-Memory Cursor matrix GDW CLUT CLUT GDWCURPOINTh CLUTPOINTh DISPOINTh 1-bit DRCS matrices 4-bit DRCS matrices 2-bit DRCS matrices DRC4POINTh DRC2POINTh DRC1POINTh User Data VBI Sept. 10, 2004; 6251-556-3DS DATA SHEET Function Pointer to pointer array 0 Pointer to pointer array 1 Micronas ...
Page 101
... H 5 (HByte) H Micronas User has to take care for a pointer definition so that memory areas do not overlap each other on the one hand and that the definition is optimized in a way, so that no memory is wasted on the other hand. The length of the global display word is fixed to 10 Byte and the length of the CLUT is fixed to 2 × ...
Page 102
... For further infor- mation on the memory format refer to Section 2.13.8. on page 96. The length of these areas depends on the settings of DRCSB1_3 … DRCSB1_0 DRCSB2_3 … DRCSB2_0. Sept. 10, 2004; 6251-556-3DS DATA SHEET word (GDW; see also depends on the settings and the settings Micronas of of ...
Page 103
... F5 POINTARRAY No H 0_1 F6 POINTARRAY No H 0_0 Micronas Width Purpose 1 bit Used to avoid the download of the parameter settings of the GDW from the RAM to the local display generator register bank. See also Section : 0: Download disabled. 1: Download enabled. Initial value bit Used to disable/enable the output of the display gener- ator ...
Page 104
... SDA 55xx 2.13.10. TVText Pro Characters Fig. 2–17: ROM Character Matrices 104 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 105
... DATA SHEET Fig. 2–18: ROM Character Matrices Micronas Sept. 10, 2004; 6251-556-3DS SDA 55xx 105 ...
Page 106
... SDA 55xx Fig. 2–19: ROM Character Matrices 106 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 107
... DATA SHEET Fig. 2–20: ROM Character Matrices Micronas Sept. 10, 2004; 6251-556-3DS SDA 55xx 107 ...
Page 108
... SDA 55xx Fig. 2–21: ROM Character Matrices 108 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 109
... Related Registers Table 2–81: Related registers Register Name 7 6 SCR1 Reserved PSAVE bit addressable PCON SMOD PDS See Section 3. on page 110 for detailed register description. Micronas Bit Name RGB_G[1:0] CORBL CADC WAKUP IDLS SD Sept. 10, 2004; 6251-556-3DS SDA 55xx 2 ...
Page 110
... EAV Sept. 10, 2004; 6251-556-3DS DATA SHEET Page 120 133 133 133 119 118 129 128 128 128 128 126 126 119 124 129 131 120 120 124 135 135 129 117 117 117 124 121 121 121 121 121 121 Micronas ...
Page 111
... EWT EX0 EX0F EX0R EX1 EX12 EX13 EX18 EX19 EX1F EX1R EX20 EX21 EX6 EXX0 EXX0F EXX0R EXX1 Micronas Table 3–2: SFR register bits index, continued Page Name 121 EXX1F 121 EXX1R 121 F0 132 F1 135 FALL 135 First 136 FREQSEL(1) 135 ...
Page 112
... RB8 Sept. 10, 2004; 6251-556-3DS DATA SHEET Page 117 117 135 127 127 127 127 127 127 127 127 127 127 118 117 128 129 130 130 126 129 129 135 135 135 135 126 126 127 127 127 124 120 Micronas ...
Page 113
... SDV[7:0] SDV[9:8] SEL SLI_ACQ SM0 SM1 SM2 SMOD SNC SND_H[2:0] SND_V[5:3] SP_[7:0] Start TAP TAP TB8 TF0 TF1 Micronas Table 3–2: SFR register bits index, continued Page Name 126 TH0[7:0] 126 TH1[7:0] 126 TI 120 TL0[7:0] 130 TL1[7:0] 130 TR0 131 TR1 ...
Page 114
... Micronas ...
Page 115
... ACQON Reserved IntSrc1 IntSrc0 DF HYS E0 E1 Reserved RGB_G[1:0] E2 RGB_D[1: Micronas Data Bits WTmr AVS DVS PC80[7:0] PC81[7:0] PC82[7:0] PC83[7:0] PC84[7:0] PC85[7:0] PC140[7:0] PC141[7:0] PCX140[7:2] PCX141[7:2] PWC[7:0] PWC[13:8] PE[7:0] F0 RS[1:0] CADC0[7:0] CADC1[7:0] CADC2[7:0] CADC3[7:0] ADWULE CADC ...
Page 116
... Data Bits EVCR[7:0] VSU2[3:0] VL[7:0] B[7:0] HPR[7:0] Point1[13:8] Point1[7:0] Point0[13:8] Point0[7:0] En_Ld_Cur 4) OSCPD 3) MSIZ[7:0] MSIZ[7:0] Sept. 10, 2004; 6251-556-3DS DATA SHEET EVCR[9:8] VL[9:8] HPR[11:8] En_DGOut Dis_Cor Dis_Blank Reset h00 h04 h02 h71 h00 h08 h55 h00 h06 h00 h00 h00 - h80 - h0F Micronas ...
Page 117
... SP_[7:0] h81[7:0] DPL h82 DPL[7:0] h82[7:0] DPH h83 DPH[7:0] h83[7:0] DPSEL h84 DPSEL[2:0] h84[2:0] PCON h87 SMOD h87[7] PDS h87[6] Micronas Dir Reset Range Function PORT RW hFF Port 0 RW 255 0..255 Port 0 RW hFF Port 1 RW 255 0..255 Port 1 RW ...
Page 118
... Timer/Ctr Mode RW 0 0..1 Gating control when set. Timer/counter ëxí is enabled only while ëINTxí pin is high and ëTRxí control pin is set. When cleared, timer ëxí is enabled, whenever ëTRxí control bit is set. Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 119
... UB3 h96[6] UB4 h96[5] MX[19] h96[4] MXM h96[3] MX[18:16] h96[2:0] MEXSP h97 MEXSP[6:0] h97[6:0] Micronas Dir Reset Range Function RW 0 0..1 Timer or counter selector. Cleared for timer operation (input from inter- nal system clock). Set for Counter operation (input from ëTxí input pin 0..3 Timer Operating Mode 00: 8048 timer: ë ...
Page 120
... Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through stop bit time in the other modes, in any serial reception. Must be cleared by software. RW h00 RW 0 0..255 Serial Data Buffer Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 121
... IEN3 hAB EADW hAB[5] E24 hAB[4] EX21 hAB[3] EX20 hAB[2] EX19 hAB[1] EX18 hAB[0] Micronas Dir Reset Range Function INTERRUPT RW h00 Interrupt Enable 0..1 Enable All Interrupts When set to ë0í, all interrupts are disabled. When set to ë1í, interrupts are individually enabled/disabled according to their respective bit selection ...
Page 122
... ExternalX 0-interrupt detection on falling edge at Pin P3 0..1 if set, External 1-interrupt detection on rising edge at Pin P3 0..1 if set, External 1-interrupt detection on falling edge at Pin P3 0..1 if set, External 0-interrupt detection on rising edge at Pin P3 0..1 if set, External 0-interrupt detection on falling edge at Pin P3.2 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 123
... G1P1 hB8[1] G0P1 hB8[0] CISR0 hC0 L24 hC0[7] ADC hC0[6] WTmr hC0[5] Micronas Dir Reset Range Function RW h00 Interrupt Priority 0..1 Interrupt Group Priority Level as follows Interrupt Group x is set to priority level 0 (lowest Interrupt Group x is set to priority level 1. ...
Page 124
... Set by hardware when external interrupt edge detected. Must be cleared by software. Port P3.1 must be in input mode to use this interrupt. RW Sandcastle RW Definition of Hysteresis (slave mode/sandcastle input) Defines the voltage range for the Hysteresis: 0: Hysteresis set to 0.325 V. 1: Hysteresis set to 0.150 V. Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 125
... WTmr_strt hB3[5] WTmr_ov hB3[4] WDT_low hB4 WDTlow[7:0] hB4[7:0] Micronas Dir Reset Range Function RW Slicing Level Vertical Sync-Pulses (slave mode/sandcastle input) To fit the requirements of various applications the input circuit of the sandcastle decoder is free programmable. The slicing levels for the vertical pulses can be varied in a range from 0. 1. steps of about 0 ...
Page 126
... Controller sets this bit enter the SSU mode and to indicate it is expecting a new telegram. When an event occurs CAPUTR unit sets First bit. Upon next event, hardware resets the first bit and interrupt is generated based on MIN_CAP register. 0: Not SSU mode. Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 127
... PCX140[7:2] hCA[7:2] PWM_compext14_1 hCB PCX141[7:2] hCB[7:2] PWM_cl hCC PWC[7:0] hCC[7:0] PWM_ch hCD PWM_Tmr hCD[7] OV hCD[6] PWC[13:8] hCD[5:0] Micronas Dir Reset Range Function PWM RW h00 PWM 8 bit Compare 0..255 PWM 8bit compare 0 RW h00 PWM 8 bit Compare 0..255 ...
Page 128
... In voltages that is 2 0.156 V = 2.344 0..15 Defines whether the corresponding port-pin is used as analog input or as digital input. 0: Port pin is digital input (the analog value has less precision). 1: Port pin is analog input (the digital value is always 0). Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 129
... PLLS hD7[0] PSAVE hD8 CADC hD8[4] WAKUP hD8[3] SLI_ACQ hD8[2] DISP hD8[1] PERI hD8[0] Micronas Dir Reset Range Function SFRIF RW h00 Power Save Extra Register RW h00 0 ..1 Clock Source 0:200 MHz PLL (33.33 MHz system clock) selected. 1: PLL is bypassed oscillator clock 6 MHz (3 MHz system clock selected) ...
Page 130
... Attention: Register values greater then 983d generate pixel frequencies which are outside of the specified boundaries. DSYNC RW h00 DSync Control 1 Reserved for internal use. Must be set to 1 (see Section 2.14. on page 109). RW Used for DAC setup purpose (see Section 2.14. on page 109) Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 131
... SCR0 hE2 RGB_D[1:0] hE2[7:6] HP hE2[5] VP hE2[4] INT hE2[3] Micronas Dir Reset Range Function RW 3-Level Contrast Reduction Output By means of COR_BL the user is able to switch the COR signal to a three level signal providing BLANK and contrast reduction information on pin BLANK/COR. 0: Two level signal for contrast reduction. ...
Page 132
... This register defines the end of the horizontal clamp phase from the positive edge of the horizontal sync impulse (at normal polarity). The end of clamp phase can be calculated by the following formula: tH_clmp_e = 480 ns * EHCR If EHCR is smaller than BHCR the clamp phase will appear during Hsync. Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 133
... EVCR1 hEC EVCR[9:8] hEC[1:0] EVCR0 hED EVCR[7:0] hED[7:0] VLR1 hEE Odd_Ev hEE[6] Micronas Dir Reset Range Function RW h00 DSync H Clamp Begin RW 0 0..255 Beginning of Horizontal Clamp Phase (master and slave mode) This register defines the delay of the horizontal clamp phase from the positive edge of the horizontal sync impulse (normal polarity is assumed) ...
Page 134
... This register allows to adjust the period of the horizontal sync signal. The horizontal period is independent from the pixel frequency and can be adjusted with the following resolution: tH-period = Sept. 10, 2004; 6251-556-3DS DATA SHEET ................ ................ VSU VSU2 VSU ................ ................ VSU2 VSU VSU2 VSU VSU2 ................ Micronas ...
Page 135
... TAP hFA Optimized OPTI0 hFD FREQSEL(1) hFD[7] FREQSEL(2) hFD[6] OSCPD hFD[5] CSCR0 hDD ENETCLK hDD[5] ENERCLK hDD[4] P4_7_Alt hDD[3] Micronas Dir Reset Range Function DISPLAY RW h00 Display Pointer 1 High Byte RW 0 0..255 Display Pointer 1 high byte RW h06 Display Pointer 1 Low Byte RW 6 ...
Page 136
... Port P4.2 and P4.3 function as port pins 1: Port 4.2 and P4.3 function as RD and WR signal outputs. RW h00 0: Pin functions as address line 1: Pin function as port RW h00 0: Pin functions as address line 1: Pin function as port RW h00 0: Pin functions as address line 1: Pin function as port Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 137
... AGDON AFRON ANOON GDPON GDNON FREON NOION FULL NOISE(0) FREATTF STAB VDOK FIELD NOISE(1) GRDON GRDSIGN LEOFLI[11:8] Micronas Table 3–6: ACQ register bits index, continued Name LEOFLI[7:0] Page DINCR[15:8] 139 DINCR[7:0] 141 NORM[2:0] FCSEL[1:0] FC1ER VCR MLENGTH[7:5] ALENGTH[4:3] Page CLKDIV[2:0] 139 ...
Page 138
... GDPON GDNON STAB VDOK FIELD FCSEL[1:0] ALENGTH[4:3] Sept. 10, 2004; 6251-556-3DS DATA SHEET FREON NOION FULL NOISE(1) GRDON GRDSIGN FC1ER VCR Reserved CLKDIV[2:0] TLDE FCOK Reset h0000 h0000 h0000 h0000 h0000 h0000 h0000 h0000 h0000 h0000 h0000 h0000 h0000 h0000 Micronas ...
Page 139
... ACQFP4 h0004 FC1[7:0] h0004[7:0] ACQFP5 h0005 AGDON h0005[7] AFRON h0005[6] ANOON h0005[5] GDPON h0005[4] GDNON h0005[3] FREON h0005[2] NOION h0005[1] Micronas Dir Sync Reset Range Function FIELD_PARAMETER RW VS h0000 0..255 RW VS h0000 0..255 Programmable 16-bit Framing code ...
Page 140
... Group delay distortion detected (Written to memory by ACQ_interface) Sept. 10, 2004; 6251-556-3DS DATA SHEET 0: Full channel mode off 1: Full channel mode on 0000: +/- 1.92us 0001: +/- 3.84us ... 1111: +/- 30.072us 0: any error acepted 1: 11 errors accepted ... 10: 2 errors accepted 11: 1 error accepted 12: no error accepted Micronas ...
Page 141
... DINCR[15:8] h000D[7:0] ACQLP1 h000E DINCR[7:0] h000E[7:0] ACQLP2 h000F NORM[2:0] h000F[7:5] FCSEL[1:0] h000F[4:3] Micronas Dir Sync Reset Range Function RW 0 Group delay detector group delay distortion has been detected, it was positive group delay distortion has been detected, it was negative. ...
Page 142
... CLKDIVSL 0001 × f 0011/2 × f 0101/3 × f 0111/4 × f 1001/5 × f 1011/6 × f 1101/7 × f 1111/8 × f Note: f Sept. 10, 2004; 6251-556-3DS DATA SHEET and 0.13 × SL (SL is the actual filter CLK CLK CLK CLK 33.33 MHz s Micronas ...
Page 143
... DATA SHEET Table 3–8: ACQ register description, continued Name Addr ACQLP4 h0011 PERR[7:2] h0011[7:2] TLDE h0011[1] FCOK h0011[0] Micronas Dir Sync Reset Range Function RW HS h0000 Phase Error Watch Dog (detection of test line CCIR331a or b) The value shows how often in a line the internal PLL found strong phase deviations between PLL and sliced data ...
Page 144
... SDA 55xx 4. Specifications 4.1. Outline Dimensions for PSDIP52-1 Package Fig. 4–1: PSDIP52-1: Plastic Shrink Dual In-line Package, 52 leads, 600 mil Ordering code: PO Weight approximately 5.13 g 144 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 145
... DATA SHEET 4.2. Outline Dimensions for PSDIP52-2 Package Fig. 4–2: PSDIP52-2: Plastic Shrink Dual In-line Package, 52 leads, 600 mil Ordering code: PO Weight approximately 5.92 g Micronas Sept. 10, 2004; 6251-556-3DS SDA 55xx 145 ...
Page 146
... SDA 55xx 4.3. Outline Dimensions for PMQFP64-1 Package Fig. 4–3: PMQFP64-1: Plastic Metric Quad Flat Package, 64 leads, 14 × 14 × Ordering code: BS Weight approximately 0.95 g 146 3 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 147
... DATA SHEET 4.4. Outline Dimensions for PLCC84-1 Package Fig. 4–4: PLCC84-1: Plastic Leaded Chip Carrier, 84 leads, 29.4 × 29.4 × 3.8 mm Ordering code: WA Weight approximately 6.72 g Micronas 3 Sept. 10, 2004; 6251-556-3DS SDA 55xx 147 ...
Page 148
... SDA 55xx 4.5. Outline Dimensions for PMQFP100-1 Package Fig. 4–5: PMQFP100-1: Plastic Metric Quad Flat Package, 100 leads, 14 × 20 × 2.7 mm Ordering code: QB Weight approximately 1.7 g 148 3 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 149
... Micronas Pin Name Type Connection (If not used) D1 I/O D4 I/O D2 I/O D3 I/O XROM I/O VDD 2.5 PS VSS2.5 PS VDD 3.3 PS P0.0 PS P0.1 I/O P0.2 I/O P0.3 I/O P0.4 I/O P0.5 I/O P0.6 I/O P0.7 I/O ENE I STOP I Sept. 10, 2004; 6251-556-3DS ...
Page 150
... In master mode HS or VCS output Vertical sync input/ouput for display synchronization. ---------- It also can be used as digital input P4.7. See Section on page 155. ---------- Furthermore, this pin can be selected as an ODD/EVEN indicator alternatively to P3.0. See Section on page 155. Micronas ...
Page 151
... Micronas Pin Name Type Connection (If not used) P3.0 I/O P3.1 I VSS PS VDD 3 P1.4 I/O P1.5 I/O P1.6 I/O P4.2 I/O P4.3 I/O RST ...
Page 152
... Port 1.7 has an alternated function. See Section on page 155. Not connected. Control output. Indicates a write access to the internal XRAM. ---------- It can be used as a write strobe for writing data into an external data RAM by a MOVX instruction. ---------- This signal is also available as P4.3 See Section on page 155. Micronas ...
Page 153
... Micronas Pin Name Type Connection (If not used A19 I/O A18 I/O A17 I/O A16 O A15 O FL_PGM I VDD 2.5 PS VSS PS VDD 3.3 PS A14 O A12 O A13 FL_RST I A8 ...
Page 154
... RAM. All the pins prefix by FL_ are test pins that must be left open. Data bus for external mem- ory or data RAM. Address bus for external program memory or data RAM. Data bus for external mem- ory or data RAM. Micronas ...
Page 155
... Micronas Pin Name Type Connection (If not used) CADCCO(AD0) I CADCCO(AD1) I CADCCO(AD2) I CADCCO(AD3) I CSCR0(O_E_P3_0) I/O PORT INPUT I/O MODE PORT OUTPUT I/O MODE PORT INPUT I/O MODE PORT INPUT I/O MODE PORT INPUT I MODE ...
Page 156
... Output 14-bit pulse PWM channel 0 Alternate function of P1.7: Output 14-bit pulse PWM channel 1 Alternate function of P4.2: Read signal Alternate function of P4.3: Write signal Alternate function of P1.7: VS output Alternate function of P1.7: OddEven output Alternate function of P4.4: Port pin Alternate function of P4.1: Port pin Alternate function of P4.0: Port pin Micronas ...
Page 157
... Pin 28, NC − Pin not connected. Pin 29, HS/SSC − In slave mode horizontal sync input or sandcastle input for display synchronisation. In mas- ter mode HS or VCS output. Micronas Pin 30, VS/P4.7 − Vertical sync input/output for diaplay synchronisation. Can also be used as digital input P4.7 Furthermore this pin can be selected as an ODD/ EVEN indicator alternatively to P3 ...
Page 158
... Pin 88, PSEN − Program Store Enable. PSEN is a control output signal which is usually connected to OE input line of the external program memory to enable the data output. Pin 96, 98, 99, 100, D7, D6, D0, D5 − Data bus for external memory or data RAM. 158 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
Page 159
... FL_CE 100 XROM VDD 2.5 V VSS 2.5 V VDD 3.3 V Fig. 4–6: PMQFP100-1 package Micronas NC RD A19 WR A18 NC A16 P1.7 A17 A15 SDA 55xx P0.0 P0.1 P0.2 P0.3 OCF P0.4 STOP P0.5 ENE P0.6 P0.7 Sept. 10, 2004 ...
Page 160
... NC P0.7 VDD 2.5 V VSS VDD 3 VSSA CVBS VDDA 2.5 V Sept. 10, 2004; 6251-556-3DS DATA SHEET VDDA 2.5 V VSSA XTAL1 XTAL2 NC 32 RST 31 P4.3 30 P4.2 29 VDD 3 VSS 27 P3 P3.5 22 P3.4 21 P3.3 20 P3.2 19 P3 HS/SSC P2.3 P2.2 P2.1 P2.0 Micronas ...
Page 161
... VDDA 2 VSSA HS/SSC Fig. 4–8: PSDIP52-1 /PSDIP 52-2 package Micronas P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 VDD 3.3 V VSS VDD 2.5 V BLANK/COR VDDA 2.5 V VSSA XTAL1 XTAL2 RST P4.3 P4.2 VDD 3.3 V VSS P3.7 P3.6 Sept. 10, 2004; 6251-556-3DS SDA 55xx 161 ...
Page 162
... SDA 55xx A11 A4 PSEN A3 D7 A10 A1 VSS A2 VDD 3.3 Sept. 10, 2004; 6251-556-3DS DATA SHEET P3.5 P3.4 P3.3 P3.2 P3.1 P3 HS/SSC 31 P2.3 P2.2 30 P2 VSA 26 VDDA 2.5 25 CVBS 24 P0.7 P0.6 23 P0 P0.3 19 P0.2 18 P0.1 17 P0.0 VDD 3 VSS VDD 2.5 14 XROM Micronas ...
Page 163
... P Maximum Power Dissipation max PSDIP52-1, PSDIP52-2 PMQFP64-1 PLCC84-1 PMQFP100-1 VDD33 Supply Voltage 3.3 V 1..7 VDD25 Supply Voltage 2.5 V 1..2 VDDA Analog Supply Voltage 1..4 1) Single chip. Not applicable for Flash version (SDA 555xFL) Micronas Pin Name Min 1) −10 −10 −10 − − 2.25 2.25 Sept. 10, 2004; 6251-556-3DS ...
Page 164
... Single chip. Not applicable for Flash version (SDA 555xFL) 164 Pin No. Min 3.0 2.25 2.25 −0.4 All All 2.0 Sept. 10, 2004; 6251-556-3DS DATA SHEET Limit Values Unit Typ Max 70 °C 70 °C 70 °C 70 ° ° ° ° °C W 0.6 0.6 0.6 0.6 3.3 3.6 V 2.5 2.75 V 2.5 2.75 V 0.8 V 3.6 V Micronas ...
Page 165
... Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH I Leakage Current L I Pull-up Low Current IL I Pull-up High Current IH Crystal Oscillator C Crystal Oscillator Frequency FB Micronas Limit Values Pin Name Min. Typ. Max 0 <4 −0.4 All 0 ...
Page 166
... A11, A12, A13 A14, A15, ALE, PSEN, RD, WR P4.0, P4. P4.2, P4. P4 Sept. 10, 2004; 6251-556-3DS DATA SHEET Unit Test Conditions pF - 1/MΩ Available: 0.5 V, 0.7 V, 1 kΩ LSB LSB % 1.2 V Output Voltage Swing (10% - 90%) ns (10 (10% - 90%) ns (10 Micronas ...
Page 167
... V Input Hysteresis 1 HYST1 V Input Hysteresis 2 HYST2 T Input Pulse Width IPWH C Pin Capacitance I I Leakage Current I V Input Low Voltage IL V Input High Voltage IH Micronas Limit Values Pin Name Min. Typ. Max. D0, D1, D2 D3, D4 BLANK CORBLA 8 ...
Page 168
... Pin Name Min. Typ. Max. HSYNC - 200 - 200 2/ -0.4 0.8 2.0 2.6 4.59 4,59 31.98 31.98 2.31 2.31 27.39 27. P1.x, P3. P4 Sept. 10, 2004; 6251-556-3DS DATA SHEET Unit Test Conditions ns (10% - 90%) ns (10 (10% - 90%) ns (10 µs - µs - µs - µs - µs Depends on register HPR ns (10% - 90%) ns (10 Micronas ...
Page 169
... Fig. 4–10: H/V-Sync-Timing (Sync Master Mode) Equalizing pulses VCS Horizontal pulse VCS T T HPVCS DEP T T HPR HPR Fig. 4–11: VCS-Tming (Sync Master Mode) Micronas T OPWV T OPWH Line Line Equalizing pulses Field sync pulses i Horizontal pulses Equalizing pulses Field sync pulses ...
Page 170
... Address to valid instruction in Fig. 4–12: Program Memory Read Cycle 170 t CYC PLPH t PHIX t PLIV valid Symbol Min f SYS t CYC t 80 ns PLPH t 57.5 ns PLIV t PHIX t 115 ns AVIV Sept. 10, 2004; 6251-556-3DS DATA SHEET 3 4 valid Max 0 ns Micronas ...
Page 171
... Data Memory Read Cycle State Parameter Frequency of internal clock Data read cycle time RD Pulse width RD to valid data in Data hold after RD Address to valid data in Fig. 4–13: Data Memory Read Cycle Micronas t CYC RLRH t RLDV t AVDV Symbol Min ...
Page 172
... WR to data out Data hold after WR Address to valid data out Fig. 4–14: Data Memory Write Cycle 172 t CYC WLWH t WLDV Symbol Min f SYS t CYC t 170 ns WLWH t WLDV t 12,5 ns WHDX t AVDV Sept. 10, 2004; 6251-556-3DS DATA SHEET WHDX Max 15 ns 135 Micronas ...
Page 173
... VSS3 .3 Fig. 4–15: Output Voltage of the Combined BLAN/COR Reduction Signal Signal Range VDD 3.3 blank on; contrast reduction don't care 2.4 V undefined 0.4 blank off; contrast reduction don't care VSS3.3 Fig. 4–16: Output Voltage for Blanking Signal Micronas Ideal Signal ideal Signal t r Sept. 10, 2004 ...
Page 174
... SDA 5550 only Up to 1Mbyte Program Memory (115 ns BLANK/ COR 8 8 TVTEXT PRO 4 SDA 55xx 8 3...6 CVBS 100 nF Sept. 10, 2004; 6251-556-3DS DATA SHEET R (0.5 Vpp ...1.2 Vpp) G (0.5 Vpp ...1.2 Vpp) B (0.5 Vpp ...1.2 Vpp) BLANK (3.3V) Port 0 Port 1 Port 2 (max. 2.5 V) Port 3 Port 4 CVBS (1.2 Vpp) Micronas ...
Page 175
... DATA SHEET Micronas Intentionally Vacant Sept. 10, 2004; 6251-556-3DS SDA 55xx 175 ...
Page 176
... By this publication, Micronas GmbH does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. ...