DAC3550A Micronas, DAC3550A Datasheet
DAC3550A
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DAC3550A Summary of contents
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... MICRONAS MICRONAS MICRONAS MICRONAS Edition July 23, 1999 6251-109-4E 6251-467-1DS DAC 3550A Stereo Audio DAC MICRONAS ...
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... Recommended Operating Conditions 20 3.7.3. Characteristics 25 4. Applications 25 4.1. Line Output Details 25 4.2. Recommended Low-Pass Filters for Analog Outputs 26 4.3. Recommendations for Filters and Deemphasis 26 4.4. Recommendations for MegaBass Filter without Deemphasis plus 1st-order low-pass 27 4.5. Power-up/down Sequence 27 4.5.1. Power-up Sequence 27 4.5.2. Power-down Sequence 28 4.6. Typical Applications 32 5. Data Sheet History 2 Micronas ...
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... The DAC 3550A is a single-chip, high-precision, dual digital-to-analog converter designed for audio applica- tions. The employed conversion technique is based on oversampling with noise-shaping. With Micronas’ unique multibit sigma-delta technique, less sensitivity to clock jitter, high linearity, and a supe- rior S/N ratio has been achieved. The DAC 3550A is 2 controlled via I C bus ...
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... Postfilter Op Amps Deemphasis Op Amps Line-Out Analog Volume Headphone Amplifier 5 7 OUTL OUTR 18 Vdd Digital Supply 17 Vss 9 AVDD0 10 AVDD1 3 AVSS0 Analog 2 AVSS1 Supply 44 VREF 1 AGNDC 16 SDA SCL 27 TESTEN 26 PORQ 21 DEECTRL Control 19 MCS1 20 MCS2 32 AUX1R 30 AUX2R 35 DEEMR 42 FOPR 41 FOUTR 43 FINR Micronas ...
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... WSI left 32-bit audio sample Fig. 2– 32-bit mode (LR_SEL=0) Micronas Automatic Detection control is required to switch between 16- and 32-bit mode recommended to switch the DAC 3550A into mute position during changing between 16- and 32-bit mode. For high-quality audio recommended to use the 32-bit mode of the I dynamic range (if more than 16 bits are available) ...
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... Postfilter Op Amps, Deemphasis Op Amps, and Line-Out This block contains the active components for the ana- log postfilters and the deemphasis network. The op amps and all I/O-pins for this block are shown in Fig. 2–5. FOUTL D/A FOUTR - - - - AUX_MS INSEL_AUX2 INSEL_AUX1 INSEL_DAC Micronas ...
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... Please note, that if a speaker is connected, it should strictly be connected as shown in Fig. 2–5. Never use a separate connector for the speaker, because electro- static discharge could damage the output transistors. Micronas optional line-out , OUTL + - ...
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... As in standard mode, the sample rate detection allows a tolerance of 200 ppm at WSI. Subaddressing is not possible in MPEG mode; this means, in multi-DAC systems, only one DAC 3550A can run in MPEG mode control automati control set- Micronas ...
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... AVOL 1 1 GCFG The mnemonics used in the DAC 3550A demo soft- ware of Micronas are given in the last column. Micronas The registers of the DAC 3550A have 8- or 16-bit data size; 16-bit registers are accessed by writing two 8-bit 2 C bus slave data words. ...
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... Not connected LV Audio Output: Headphone left or Speaker + LV Not connected LV Audio Output: Headphone right or Speaker LV Not connected X VDD 0 for audio output amplifiers X VDD 1 for audio back-end LV Not connected X Quartz oscillator pin 1 X Quartz oscillator pin 2 LV Clock Output clock Micronas ...
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... FOUTL OUT 38 FOPL IN/OUT 39 FINL IN/OUT FOUTR OUT 42 FOPR IN/OUT 43 FINR IN/OUT 44 VREF IN Micronas Connection Short Description (if not used data X Digital VSS X Digital VDD Chip Select Chip Select 2 VSS Deemphasis on/off Control LV Not connected ...
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... The digital audio data is transmitted ble format. Audio word lengths of 16 and 32 bits are supported, as well as SONY and Philips I SCL (15) SDA (16) SCL (serial clock) and SDA (serial data) provide the connection to the serial control interface (I 2 S-compati protocol. 2 C). Micronas ...
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... DEECTRL-pin. DEECTRL (21 C-control is used, deemphasis can be switched on and off with this pin. MCS1 (19) MCS2 (20) Mode select pins to select MPEG, Standard Mode, and subaddress. Micronas 3.4. Pin Configuration AUX2L AUX2R AUX1L AUX1R DEEML 34 DEEMR 35 ...
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... Fig. 3–9: Input/Output Pins XTI, XTO sel/nonsel AUXnL mono/stereo AGNDC mono/stereo AUXnR sel/nonsel Fig. 3–10: Input Pins AUX1R, AUX1L, AUX2R, AUX2L, AGNDC OUTn AGNDC Fig. 3–11: Output Pins OUTL, OUTR VDD VSS Fig. 3–12: Input Pins MCS1, MCS2, DEECTRL AGNDC Micronas ...
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... Fig. 2–1 and Fig. 2–2 on page 2) don’t care Micronas not used, set to 0 L/R-bit 1) 0 (WSI = 0 left channel (WSI = 0 right channel) Delay-Bit 0 No Delay ...
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... AUX2 select 0 AUX2 off 1 AUX2 on AUX1 select 0 AUX1 off 1 AUX1 on DAC select 0 DAC off 1 DAC on (default) aux-mono/stereo 0 stereo 1 mono invert right power amplifier 0 not inverted 1 inverted Default Name Values (hex) 4H SEL_53V PWMD INSEL_AUX2 INSEL_AUX1 INSEL_DAC AUX_MS IRPA Micronas ...
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... Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. Micronas Pin Min. Name ...
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... Please refer to Section 4.1. “Line Output Details” on page 25. 18 Pin Name Min AVDD0/1 3.0 VDD 2.7 AVDD0/1 V SUPD 0.25 V AGNDC 1.0 AGNDC 3) AUXnL/R 3) AUXnL/R 4) FOUTL/R 7.5 4) FINL/R 5.0 FINL/R 10 OUTL/R OUTL/R Typ. Max. Unit 70 C 3.3 5.5 V 3.3 5.5 V 5 0.35 0.7 V rms 0.525 1.05 V rms 7 1 400 100 pF Micronas ...
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... DAC 3550A tested in extended temperature range on request 2) typically operable down to 2.7 V, without loss in performance Please refer to Section 4.2. “Recommended Low-Pass Filters for Analog Outputs” on page 25. 5) Please refer to Section 4.1. “Line Output Details” on page 25. Micronas Pin Name Min active SCL 2 S inactive CLI, ...
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... mA, load V = 2.7 V SUPD mA PWMD = 0, Mute mA PWMD = 1, Mute mA PWMD = 0, Mute mA PWMD = 1, Mute dB 1 kHz sine at 100 mV rms dB 100 kHz sine at 100 mV rms dB 1 kHz sine at 100 mV rms dB 100 kHz sine at 100 mV rms VSUP 2 Micronas ...
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... GA2 E Analog Output Gain Error GA3 E Analog Output Gain dGA Step Size Error SNR Signal-to-Noise Ratio from AUX Analog Input to Line Output Signal-to-Noise Ratio from Analog Input to Headphone Output Micronas Pin Name Min. Typ. Max. OUTL/R, 0.65 0.7 0.75 FOUTL/R, FINL/R 1.0 1.05 1.1 AUXnL/R, ...
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... Hz...22 kHz, unweighted, R > Input 1 kHz at 0.5 V rms R 612 dec % Hz...0.5 fs, unweighted, R > Input 1 kHz at 3 dBFS R 612 dec % Hz...0.5 fs, unweighted (47 series resistor required), Analog Gain = 0 dB, Input 1 kHz at 3 dBFS Micronas ...
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... Total Harmonic Distortion SP (Speaker) XTALK Cross-Talk LO Left/Right Channel (Line Output) XTALK Crosstalk HP Left/Right Channel (Headphone) XTALK Crosstalk between 2 Input Signal Pairs V Analog Reference Voltage AGNDC Micronas Pin Name Min. Typ. Max. OUTL/R 0.5 AUXnL/ FOUTL/R, FINL/R OUTL AUXnL AGNDC 1.5 2 ...
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... Input not selected referred to VREF PWMD = 200 A, referred to VREF k PWMD = 1, Mute referred to VREF mV referred to AGNDC mV Mute referred to AGNDC mV PWMD = 0, referred to AGNDC mV PWMD = 0, referred to AGNDC mV Analog Gain = Mute, PWMD switched from Micronas ...
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... FOUTL(R) FOPL(R) - Fig. 4–2: 1st-order low-pass filter Table 4–2: Attenuation of 1st-order low-pass filter Frequency Gain 24 kHz 2 kHz 3 without deemphasis circuit Micronas 2nd-order 11 k 1.0 nF AVSS FOUTL(R) Fig. 4–3: 2nd-order low-pass filter Table 4–3: Attenuation of 2nd-order low-pass filter in Frequency 24 kHz from 30 kHz 3rd-order 7 ...
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... Fig. 4–6: General circuit schematic Table 4–6: Resistor and Capacitor values 3rd order 7.5 560 7.5 C1 (nF) 270 7 (nF) 1.0 C3 (pF OFF C3 FINL(R) FOPL(R) - DC-Gain = 10 dB fc1 = 100 Hz fc2 = 330 180 Micronas ...
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... AVDD0/1, simply by using a 10-k tor to AVDD0/1 and a 2.2-nF capacitor to ground. No further control on PORQ is needed. VDD 90% VDD AVDD 90% AVDD PORQ 0.7 AVDD <0.2 VDD <30 ms Fig. 4–7: Power-up sequence Micronas 4.5.2. Power-down Sequence 1. Stop I2S data. 2. Send I2C: LOW POWER. 3. Switch VDD, AVDD0 pull-up resis- DAC 3550A 27 ...
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... DRP BCLK 34xx 3510 A LRCLK 32 kHz 18.432 MHz Fig. 4–12: ADR Receiver MAS DAC 3507D 3550A 14.725 MHz CLKOUT DEMOD line out I S DAC DAC 3550A 3550A 384 fs CLKOUT 2 line-out I S DAC DAC 3550A 3550A line out Micronas ...
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... Micronas DAC 3550A 31 ...
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... By this publication, Micronas GmbH does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. ...
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... New Package for DAC 3550A: 49-Ball Plastic Ball Grid Array (PBGA49) 1. Outline Dimensions Fig. 1: 49-Ball Plastic Ball Grid Array (PBGA49) Dimensions in mm MICRONAS INTERMETALL Preliminary Data Sheet Supplement New Package for DAC 3550A DAC 3550A 6251-467-1PD, Edition April 23, 1999 No. 2/ 6251-467-1PDS ...
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... SUPPLY X Digital VSS SUPPLY X Digital VDD chip sSelect chip select 2 IN VSS Deemphasis on/off control LV Not connected 2 VSS I S bit clock 2 IN VSS I S data 2 IN VSS I S frame identification IN VDD Power-on-reset, active-low MICRONAS INTERMETALL ...
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... E7 FINL FOUTR 42 C6 FOPR 43 C7 FINR 44 A7 VREF MICRONAS INTERMETALL Type Connection Short Description (If not used Test enable LV Not connected IN LV AUX2 left input for external analog signals (e.g. tape AUX2 right input for external analog signals (e.g. tape) ...