SDA9488X Micronas, SDA9488X Datasheet
SDA9488X
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SDA9488X Summary of contents
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Edition Feb. 28, 2001 6251-561-1PD PRELIMINARY DATA SHEET SDA 9488X PIP IV Basic SDA 9588X OCTOPUS Cost-effective Picture-In-Picture ICs ...
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... The transfer functions of the decimation filters are optimally matched to the selected picture size reduction and can furthermore be adjusted to the viewer’s requirements by a selectable peaking. A maximum of 216 luminance and 2x54 chrominance pixels per line are stored in the memory. Type SDA 9488X SDA 9588X Micronas Preliminary Data Sheet P-DSO28-1 Package P-DSO28-1 P-DSO28-1 -2 ...
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... DA-Conversion And RGB / YUV Switch . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.9.1 Contrast, Brightness and Peak Level Adjustment . . . . . . . . . . . . . . . . . .32 4.9.2 Pedestal Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 4.10 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.10.1 Closed Caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.10.2 Widescreen Signalling (WSS .34 4.10.3 Indication Of New Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.10.4 Violence Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 5 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 6 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 6.1 I2C Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 6.2 I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Micronas Preliminary Data Sheet -3 ...
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... SDA 9488X SDA 9588X 6.3 I2C bus Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.4 I2C Bus Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9 Recommended Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Micronas Preliminary Data Sheet -4 ...
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... Fine positioning at steps of 4 pixels and 2 lines • Output signal processing: – 7 Bit DAC – RGB or YUV switch: insertion of an external source without PIP processing – Digital interpolation for anti-imaging 1) available with SDA 9588X only Micronas Preliminary Data Sheet 1) , multistandard color decoding, PLL for limited to 40kHz) H 1-5 ...
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... Several filter for XDS data extraction 2 • I C-Bus control (400 kHz) • High stability clock generation • PDSO 28-1 package (SMD) • Full SDA 9489X and SDA 9589X upward compatibility • SDA 9388X / SDA 9389X pinout compatibility • 3.3V supply voltage (5V input capable) Micronas Preliminary Data Sheet 1-6 Features ...
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... SDA 9488X SDA 9588X 2 Pin Configuration XIN XQ HSP VSP SDA SCL VDD VSS I2C INT IN1 IN2 IN3 FSW Figure 2-1 Pinning Figure 2-2 Package Outlines Micronas CVBS1 1 28 VREFM 2 27 CVBS2 3 26 VREFL 4 25 CVBS3 5 24 VSSA1 6 23 VDDA1 7 22 VREFH 8 21 ...
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... CVBS2 I/ana 27 VREFM I/O 28 CVBS1 I/ana I= Input / ana=analog / O= Output / TTL=Digital (TTL) / S=Supply voltage Table 2-1 Pin Description Micronas Description crystal oscillator (input) or external clock input crystal oscillator (output) horizontal sync for parent channel vertical sync for parent channel 2 I C-bus data 2 I C-bus clock ...
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... SDA 9488X SDA 9588X 3 Block Diagram DEMUX MUX Figure 3-1 Block Diagram Micronas DUV/DCHR DCVBS/DY 3-9 Preliminary Data Sheet Block Diagram ...
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... All signal are clamped and AD-converted with an amplitude resolution of 8bit. CVBS and Y signals are clamped to the sync bottom whereas U/V and C signals are clamped to their mid-level during blanking. Inset Video HD CLMPIST CLAMPI CLMPID Figure 4-1 Clamping timing Micronas 2 C bus (CVBSEL). CVBS2 and CVBS3 Input CVBS1 CVBS2 CVBS3 CVBS CVBS Y (VBS) C ...
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... Its levels correspond to the CVBS levels except for the missing color and burst. After A/D conversion the video part is clamped to its black value and is amplified to 224 digital steps. The nominal signal levels ensure correct brightness and saturation. The YUV signal levels conform to the ITU 601 recommendation. Micronas Automatic Gain Control Characteristic 4 6 ...
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... Conversion Range 0.5V ... 1.2V ... 1.5V Table 4-2 ADC conversion range and required input signal voltage Micronas 255 224 128 32 0 255 240 212 75% V 128 Signal Signal Range Range CRYC SRY SRC 0.42V pp pp ... ... ...
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... For getting the chrominance information the digitized video signal is multiplied with the regenerated color subcarrier once in-phase and once phase-shifted by 90°. After lowpass filtering digital UV is available for PAL and NTSC. The subcarrier is regenerated Micronas Preliminary Data Sheet PAL-N PAL-M ...
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... Alternatively the color-killer can be bypassed and the color can be switched on or off under all conditions (COLON). By setting ACCFIX, the automatic chroma control is disabled and set to a default value. Micronas 5 2.5 IFCOMP = ’00’ ...
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... IRE’). As for some applications a black offset is not desired, controlling may be done using LMOFST. The positive or negative offset is added to the Y signal before scaling. Micronas color killed at damping ...
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... SIZEHOR and SIZEVER. A fine adjustment in steps of 4 pixel and 2 lines is possible by HSHRINK and VSHRINK, which allows correct aspect ratio for multistandard applications (50/60 Hz mixed mode, (S)VGA). For main decimation factors, the stored number of pixel and lines are listed in the following tables. Micronas Preliminary Data Sheet Processed signal BLACK value BLANK value ...
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... SDA 948xX/958xX types Table 4-6 Number of stored lines per field Micronas Preliminary Data Sheet System Description PIP Pixel per line Y (B-Y) 216 54 216 54 160 40 108 27 PIP lines 625 lines source 525 lines source ...
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... Table 4-7 Number of stored pixel per line dependent on HSHRNK Micronas 3,00 216 0 3 6,00 3,04 212 1 3 6,23 3,11 208 2 3 6,48 3,17 204 3 3 6,75 3,23 200 4 3 7,04 3,29 196 5 3 7,35 3,37 192 6 3 7,70 3,44 188 ...
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... Multi Display Mode SDA 9488X and SDA 9588X offer the feature to display a sub-picture more than once. The picture size and arrangement depends on the display mode (DISPMOD) and not on SIZEHOR or SIZEVER. Hence variable scaling is not possible in these modes. Micronas 525 lines 625 lines 88 ...
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... For some VCRs in trick mode, often no interlace is detected also. • The number of lines is within a predefined range for inset (FMACTI) or parent (FMACTP) channel (assuming standard signals according to ITU) Micronas Size Picture configuration single PIP mode, ...
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... HSPINV or VSPINV respectively allow an inversion of the expected signal polarity. HSP VSP VSPDEL VSPD field 0 window (internal) tH (16) ←s values in brackets () apply for 100Hz systems Figure 4-7 Field detection and phase adjustment of vertical pulse (VSP) Micronas number of FMACTI 310...315 0 290...325 1 260...265 0 250...275 1 =151 (75) ←s ...
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... Please refer to Chapter 4.7.1 Table 4-11 Available Features with varying inset and parent standards Micronas frame correct aspect correct aspect 1) mode ratio (single pip) (multi display) 4-22 Preliminary Data Sheet System Description vertical ...
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... Table 4-12 Examples of supported parent signals Micronas lines Hact dot ( ← s) ← s) active (MHz) 64.0 52.0 625/ 13.5 576 63.6 52.7 525/ 13.5 488 32.0 26.0 625/ 27 576 31.8 26.4 ...
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... For a single-PiP, the number of displayed lines depends on the selected picture size and on the signal standard. For multi picture display, the number of displayed lines depends on the selected picture size and on the signal standard of the parent signal. Additionally, a standard can be forced by DISPSTD. Micronas Preliminary Data Sheet Expected input signal signal interlace ...
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... The pixel width on the screen depends on the selected HZOOM factor. Even POP-positions (Picture Outside Picture) in 16:9 applications are possible. Micronas Display Standard PIP depends on detected inset standard (single pip) PIP depends on detected parent standard (multi display) ...
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... The characteristic for all possible settings is shown in fig. (4- 0.1 Figure 4-9 Characteristics of selectable peaking factors Micronas POSHOR CPOS='01' CPOS='11' POSHOR 0.2 0.3 0.4 normed frequency 4-26 Preliminary Data Sheet System Description POSVER YPEAK = ’111’ YPEAK = ’110’ YPEAK = ’101’ ...
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... Table 4-16 RGB matrices characteristics The color saturation can be adjusted with SATADJ register in 16 steps between 0 and 1.875. Values above 1.0 may clip the chrominance signals. 4.8.3 Framing And Colored Background Figure 4-10 Normal frame and 3D frame Micronas Angles (G-Y) (B-Y) (R-Y) (G-Y) 0 0.608 0 95 ...
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... BGY, BGU, BGV, 2 bits for each component. Alternatively BGFRC sets the background to frame color. 4.8.4 16:9 Inset Picture Support To remove dark stripes at 16:9 inset pictures the vertical display area is reducable with VPSRED. The number of omitted lines depends on the vertical decimation factor. Micronas PiP Picture b ackground p icture ...
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... HZOOM. The horizontal and vertical scaling can be used for all display frequencies. display inset format picture format 4:3 4:3 4:3 4:3 16:9 4:3 16:9 16:9 Table 4-17 Format conversion using HZOOM Micronas displayed displayed lines (50Hz) lines (60Hz) with reduction 214 216 35 36 desired required PiP format parent frequency 4:3 27 16:9 20 ...
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... The FSW input signal is passed through to the SEL output. The setting of RGBINS determines wether an RGB insertion is possible and which source, the external picture or the PiP, gets priority. Micronas Preliminary Data Sheet System Description frame ...
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... Parent Video HSP allowed HSP range BLANKP a c CLAMPP Figure 4-16 PIP horizontal blanking timing Micronas RGBINS='10' RGBINS='11' PIPON='1' PIPON='1' OSD OSD OSD OSD 256 ...
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... YUV mode (OUTFOR = ’1’) the action depends on the setting of BLKINVR and BLKINVB. If BLKINVR (BLKINVB) is active the offset applies to the blank level of the RV (BU) channel during the clamping interval for shifting the setup level to the negative direction. In RGB mode (OUTFOR = ’0’) BLKINVR and BLKINVB have no effect. Micronas CLPLEN a ( ← ← s) ...
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... CC3, CC4, text T3, T4 and the XDS data are transmitted. For more information please refer to the above mentioned standards. Raw CC as well as prefiltered data is provided alternatively. With the built-in programmable XDS-Filter (XDSCLS), the program-rating information (’V-chip’) as well Micronas Preliminary Data Sheet System Description BLKINVR = BLKINVB = 1 ...
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... SLFIELD. If one or more XDS-class filter are activated, SLFIELD contains always ’1’. Additionally pin 10 (INT) may flag that new data is received. Default this pin is in tri-state mode to be compatible with Micronas' SDA9388X/9389X PIP devices. It can also be configured by IRQCON to output a single short pulse when new data is available or behave equal to DATAV ...
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... Message” THIS PROGRAM CONTAINS VIOLENT SCENES Figure 4-19 Possibilities of PiP blocking The Mosaic mode (MOSAIC) hides details of the picture by reduced sharpness and increased aliasing. The picture looks scrambled and is less perceptible. Micronas Preliminary Data Sheet “Blue Screen” 4-35 System Description “Mosaic” ...
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... SDA 9588X 5 Application Examples The following two figures show 100/120Hz applications with the Micronas Featurebox SDA 9400/01. As the chip supports two I2C addresses and owns a RGB switch dual-PiP applications are easy to implement. The arrangement for best possible performance is shown in the fig. (5-1). ...
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... WRITE S 1101x110 A Subaddress A READ S 1101x110 A Subaddress A Sr 1101x111 A Data Byte Start condition / Sr Repeated start condition / A: Acknowledge / P: Stop condition / Write operation is possible at registers 00h-21h only, read operation is possible at registers 28, 2Ah-2Ch only. An automatic address increment function is implemented. Micronas ...
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... CONADJ3 CONADJ2 CONADJ1 CONADJ0 12h BRTADJ3 BRTADJ2 13h TRIOUT REFINT 14h PKLR7 PKLR6 15h PKLG7 PKLG6 16h PKLB7 PKLB6 Micronas Data Byte CPOS0 YUVSEL READD VFP1 VFP0 HFP3 FREEZE MOSAIC SIZEHOR1 SIZEHOR0 SIZEVER1 SIZEVER0 PIPBG1 PIPBG0 FMACTP VSPNSRQ VSPDEL4 ...
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... FRMMD PIPSTAT 2Ah DATAA7 DATAA6 2Bh DATAB7 DATAB6 2Ch After power on the grey marked data bits are set to '1', all other to ‘0‘. Micronas Data Byte BGY1 BGY0 FRY3 BGU1 BGU0 FRU3 BGV1 BGV0 FRV3 SATADJ1 SATADJ0† ...
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... READD D3 double read frequency for compatibility with systems that use 2fH (e.g.100 Hz, progressive) 0 PIP display with single read frequency and 2x oversampling 1 PIP display with double read frequency Micronas Preliminary Data Sheet PiP on Coarse position YUV Select Read Double Mode 6-40 I2C Bus ...
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... Subaddress 02h POSVER D7-D0 vertical position adjustment of the PIP in steps of 1 lines shift direction depends on the coarse positioning of the picture Micronas Preliminary Data Sheet Progressive Scan Enable Field Select Horizontal Picture Position Vertical Picture Position ...
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... PIP depends on detected inset standard 0 1 PIP display is always in 625 line mode 1 0 PIP display is always in 525 line mode 1 1 freeze last detected display standard and size Micronas Preliminary Data Sheet Horizontal Fine Positioning Vertical Fine Positioning Display Standard 6-42 I2C Bus Note values refer to the ...
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... SIZEHOR D3 D2 horizontal decimation 0 0 reduction = reduction = reduction = reduction = 6 SIZEVER D1 D0 vertical decimation 0 0 reduction = reduction = reduction = reduction = 6 Micronas Preliminary Data Sheet Freeze Picture Mosaic Mode Horizontal Size Vertical Size 6-43 I2C Bus ...
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... D1 D0 selects the parent (display) clock frequency 27.34 MHz 20.25 MHz 35.27 MHz 25.43 MHz 26.67 MHz 20.63 MHz 34.17MHz 28.04 MHz Micronas Force Parent Standard PIP Background Display Frame Mode Activation Parent Horizontal Zoom 6-44 Preliminary Data Sheet I2C Bus ...
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... FRSEL D7 selects between the normal frame and the shaded frame 0 normal frame 1 shaded frame with 3D impression Micronas Horizontal Sync Pulse Inversion Vertical Sync Pulse Inversion Vertical Sync Pulse Noise Reduction Vertical Sync Pulse Delay D0 delay of the vertical sync pulse in steps of 128 parent clocks ...
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... FSW possible (priority of FSW input external insertion with FSW possible (priority of PIP) Micronas Inner Frame activation Vertical Picture Size Reduction Frame Width Horizontal Frame Width Vertical RGB Insertion 6-46 Preliminary Data Sheet I2C Bus ...
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... Subaddress 09h POSCOR D7 activates correction of display position 0 position correction disabled 1 position correction enabled Micronas Preliminary Data Sheet Vertical Blanking Select Down Select Delay Position Correction 6-47 I2C Bus ...
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... ADC overflow only 1 1 AGC fixed (gain depends on AGCVAL) Micronas Display Mode Clamping Delay delay of the clamping pulse for the external RGB/YUV inputs in steps of 8 parent clock periods no delay (0) maximum delay, 256 clock periods of parent ...
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... CVBS2 1 0 Y/C (Y@CVBS2 / C@CVBS3 CVBS3 CLMPID D5 D4 adjusts duration of clamping pulse for ADC (inset channel 0.5← 0.9← 1.2← 1.5←s Micronas Preliminary Data Sheet Automatic Gain Control Value No Signal Behavior CVBS Select Clamping Duration 6-49 I2C Bus ...
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... Micronas Preliminary Data Sheet Clamping Pulse Start Luminance Offset Inset PLL Time Constant Noise Reduction Inset PLL Note may cause trouble for VCR signals 6-50 I2C Bus ...
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... SECAM, PAL B/G, PAL60, NTSC4 ignore PAL-M /PAL-N / NTSC ignore PAL-M / PAL-N / NTSC4.4 / PAL60 LOCKSP D2 sets the speed of the color standard recognition 0 medium 1 fast Micronas Y/C Delay Color Standard Color Standard Exclusion Standard Identification Speed 6-51 Preliminary Data Sheet I2C Bus ...
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... Filter2 1 1 Filter3 COLON D3 disable color killer 0 color killer active 1 color forced on Micronas Preliminary Data Sheet Color Killer Threshold Note only valid if color killer active (COLON=’0’), values are approximative Burst Gate Position SECAM Identification Level Deemphase Selection Color On 6-52 ...
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... HUE Micronas Disable Automatic Chroma Control Chroma Bandwidth SECAM remark small adjusts chroma bandwidth medium wide IF-Compensation Filter Hue Control D0 phase of color subcarrier for NTSC 0 -44.8° 0° 43.4° 6-53 Preliminary Data Sheet ...
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... OUT1-OUT3 nominal contrast .. +30% contrast increase Micronas Satellite Noise Reduction Frame Mode Activation Inset Chroma PLL Off Color Subcarrier Adjustment D0 color subcarrier frequency fine adjustment 0 max. negative deviation (-150 ppm) ... 1 default (for nominal crystal frequency ...
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... Subaddress 13h TRIOUT D7 sets OUT1-OUT3 to tristate mode (high resistance) 0 normal operation, outputs are active 1 pins OUT1-3 are in tri-state mode Micronas Preliminary Data Sheet Blanking Level Red Brightness Adjustment Blanking Level Green Tristate Output 6-55 I2C Bus ...
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... adjusts the pedestal level of the OUT3 channel in steps of 0.5LSB pedestal .. +7.5LSB offset Micronas Preliminary Data Sheet Refresh Intervall Note let it to this default value Blanking Inversion Red Blanking Inversion Blue Blanking Level Blue 6-56 I2C Bus ...
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... Subaddress 15h PKLG Micronas Peak Level Red peak to peak output voltage of the OUT1 channel 0 ... ... 1 Peak Level Green peak to peak ...
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... BGY D5-D4 adjusts the Y background color component the values gives the two MSBs of the Y background signal FRY D3-D0 adjusts the Y frame color component the value gives the 4 MSBs of the Y frame signal Micronas Peak Level Blue peak to peak output voltage of the OUT2 channel ...
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... BGY, BGU, BGV 1 background color according to FRY, FRU, FRV BGV D5-D4 adjusts the V background color component the values gives the two MSBs of the V background signal Micronas Preliminary Data Sheet Output Format UV Polarity Background Color U Frame Color U Background Frame Color ...
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... YPEAK adjusts luminance peaking peaking recommended value strongest peaking YCOR D0 suppresses noise introduced by peaking 0 coring off 1 1LSB coring Micronas Preliminary Data Sheet Frame Color V Color Saturation Adjustment Y Peaking Adjustment Y Coring Enable 6-60 I2C Bus ...
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... UVSEQ D7 changes the UV multiplex sequence (valid only if YUVSEL=’1’ and V are correct 1 U and V are exchanged Micronas XDS Class Select Closed Caption XDS-Primary Filter (Class) transparent, no filtering ’Current’ class selected ’Future’ class selected ’Channel’ class selected ’ ...
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... V-pulse (50ns inset field inset clamping pulse Micronas Preliminary Data Sheet Multi-PIP Background Data Service Select Select Line Number remark WSS Closed Caption Closed Caption WSS Interrupt Request Pin Configuration remark pulse length is approximately 2←s ...
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... POSOFH ... ... Micronas PIP Blank PAL ID Level Position Offset Vertical Position Offset Horizontal horizontal position offset in steps of 16 pixel -256 pixel 0 pixel +240 pixel 6-63 Preliminary Data Sheet I2C Bus ...
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... Micronas Vertical Shrink changes the vertical size in steps of 2 lines no shrink, picture size according to SIZEVER max. possible shrink Horizontal Shrink changes the horzontal size in steps of 4 pixel no shrink, picture size according to SIZEHOR max. possible shrink ...
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... PLL not locked to CVBS signal locked to CVBS signal (60 Hz locked to CVBS signal (50 Hz) CKSTAT D3 chroma is 0 off 1 on Micronas Frame Mode Indication PIP Status Inset Synchronization Status Color Killer Status 6-65 Preliminary Data Sheet I2C Bus ...
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... D7 = MSB LSB Subaddress 2Ch DEVICE D5 D4 PIP SDA 9488X (PIP IV Basic SDA 9489X (PIP IV Advanced SDA 9588X (OCTOPUS SDA 9589X (SOPHISTIUS) Micronas Preliminary Data Sheet Standard Detection First Data Byte Second Data Byte Device Identification 6-66 I2C Bus ...
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... I 1 new data received and available in DATAA and DATAB SLFIELD D0 DATAA and DATAB are from 0 first field 1 second field Micronas Parent Standard Detection PAL Identification Note not valid if STDET= ’000’ Data Valid data available Sliced Data Field Number 6-67 ...
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... SDA 9488X SDA 9588X 7 Pin Description pin 1 (XIN) 2 (XQ) XIN 3 (HSP) 4 (VSP VSP 5 (SDA) 6 (SCL) SDA SCL 9 (I2C) Micronas schematic VDD VDD VDD VDD slope contr ol VDD I2C 7-68 Preliminary Data Sheet Pin Description remark crystal oscillator, input can be used for ...
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... SDA 9488X SDA 9588X pin 10 (INT) 11 (IN1) VDD 12 (IN2) IN1 13 (IN3) IN2 IN3 14 (FSW) FSW 15 (SEL) Micronas schematic VDD INT + - VDD VDD SEL 7-69 Preliminary Data Sheet Pin Description remark clamped RGB/YUV video inputs, if not used let open or connect with 10nF to ...
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... SDA 9488X SDA 9588X pin 16 (OUT3) 17 (OUT2) 18 (OUT1) 21 (VREFH) VDD 25 (VREFL) 27 (VREFM) VREFH 24 (CVBS3) VDD VDD 26 (CVBS2) CVBS1 28 (CVBS1) CVBS2 CVBS3 Micronas schematic UT1 O UT2 O UT3 + - VDD VDD VREFM VREFL 7-70 Preliminary Data Sheet Pin Description remark RGB/YUV video outputs reference voltage for ...
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... Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Micronas Symbol Limit Values min. ...
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... Inset Input: CVBS1, CVBS2, CVBS3 Horizontal Frequency Horizontal Frequency Amplitude of synchronization pulse length of horizontal synchronization puls length of vertical synchronization puls chroma amplitude Input Coupling Capacitors CVBS Source Resistance Micronas Recommended Operating Range Limit Values min. typ. 3.15 3.3 DDxx 15.000 15.625 ...
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... This specification of the bus lines need not be identical with the I/O stages specification because of optional series resistors between bus lines and I/O pins. SCL Clock Frequency Inactive Time Before Start Of Transmission Set-Up Time Start t Condition Hold Time Start t Condition SCL Low Time Micronas Recommended Operating Range Limit Values min. typ 1.05 1.11 REFL 1 ...
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... Spike Duration At Inputs Low-Level Output Current Digital To Analog Converters (7-bit):OUT1, OUT2, OUT3 Load resistance Load capacitance Crystal Specification: XIN, XQ Frequency Maximum Permissible Frequency Deviation αf/f Recommended Permissible Frequency Deviation Micronas Recommended Operating Range Limit Values min. typ. t 0.6 HIGH 100 20 ...
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... SDA 9488X SDA 9588X Parameter Symbol Load Capacitance Series resonance resistance Motional capacitance Parallel capacitance In the operating range the functions given in the circuit description are fulfilled. Micronas Recommended Operating Range Limit Values min. typ 9-75 Preliminary Data Sheet ...
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... Low-Level Input Voltage High-Level Input Voltage Delay FSW in -> SEL out I²C Inputs: SDA/SCL Schmitt Trigger Hysteresis I²C Input / Output: SDA (Referenced to SCL; Open Drain Output) Low-Level Output Voltage Low-Level Output Voltage Micronas Limit Values min. typ. I 180 210 DDtot ...
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... Current deviation Reference Voltage V Difference D.C. Differential Nonlinearity Crosstalk between CVBS Inputs Digital To Analog Converters (7-bit): Outputs OUT1, OUT2, OUT3 D.C. Differential Nonlinearity Full Range Output Voltage Full Range Output Voltage Micronas Limit Values min. typ. t 20+0. / -100 αCLE ...
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... Input Voltage Range Bandwith (-3dB) Gain Gain Difference RGB Crosstalk Between Inputs Isolation (off state) αCLPE Clamping Level Difference at Output Colordecoder/Synchronization and Luminance Processing Horizontal PLL pull-in- range Horizontal PLL pull-in- range Micronas Limit Values min. typ αAMP 400 α ...
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... Co Channel Distortion Max. permissible Noise The listed characteristics are ensured over the operating range of the integratd circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T voltage. Micronas Limit Values min. typ ...
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... SDA 9488X SDA 9588X 11 Diagrams Figure 11-1 Displaymode 0 with picture sizes 1/9 and 1/16 Figure 11-2 Displaymode 0 with picture size 1/36 and with scaling Micronas Preliminary Data Sheet 11-80 Diagrams ...
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... SDA 9488X SDA 9588X Figure 11-3 Display mode 2 (3 pictures with same content) and Display mode 3 (4 pictures with same content) Micronas Preliminary Data Sheet 11-81 Diagrams ...
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... SDA 9488X SDA 9588X CVBS 1 TUNER1 CVBS 2 CVBS 3 CVBS 1 TUNER2 Figure 11-4 General Application with 3 CVBS sources and Teletext-Processor CVBS 1 TUNER2 Figure 11-5 General Application with YUV source from DVD Micronas Teletext or OSD processor optional PIP FSW SEL R(V) G (Y) B(U) HSP ...
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... YPEAK = '111' 1/36 PiP frequency [MHz] YPEAK = '010' YPEAK = '100' YPEAK = '111' Figure 11-6 Characteristic (PAL) of luminance decimation filter for different peaking factors Micronas YPEAK = '010' YPEAK = '100' YPEAK = '111 ...
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... YPEAK = '111' 1/36 PiP frequency [MHz] YPEAK = '010' YPEAK = '100' YPEAK = '111' Figure 11-7 Characteristic (NTSC) of luminance decimation filter for different peaking factors Micronas YPEAK = '010' YPEAK = '100' YPEAK = '111 ...
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... PiP 1/16 PiP 1/36 PiP 0.25 0.5 0.75 1 1.25 1.5 frequency [MHz] 1/9 PiP 1/16 PiP 1/36 PiP Figure 11-8 Characteristic of chrominance decoder filter (small, medium and narrow) Micronas 1.75 2 2.25 2.5 0 0.25 0.5 1/9 PiP 1/16 PiP 1/36 PiP 3 6 1.75 2 2.25 2.5 11-85 Preliminary Data Sheet Diagrams 3 6 0.75 1 1.25 1.5 1 ...
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... L1 10← 10n 10← J1 DEh I2C Address D6h C5 10n RVIN C6 10n GYIN C7 10n BUIN FSW exact value depends on crystal specification Micronas C18 10n C19 10n C20 10n 10n XIN CVBS1 C9 1← VREFM 3 26 ...
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... By this publication, Micronas GmbH does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. ...