PM6344-RI PMC-Sierra Inc, PM6344-RI Datasheet
PM6344-RI
Specifications of PM6344-RI
Related parts for PM6344-RI
PM6344-RI Summary of contents
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... STANDARD PRODUCT PMC-951013 QUADRUPLE E1 FRAMER PMC-Sierra, Inc. ISSUE 6 PM6344 EQUAD ISSUE 6: DECEMBER 2005 100-2700 Production Way, Burnaby, BC Canada V5A 4X1 604 .415.6000 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... PERFORMANCE MONITOR COUNTERS (PMON) ......................................... 39 8.5 HDLC RECEIVER (RFDL) ................................................................................. 39 8.6 ELASTIC STORE (ELST) .................................................................................. 40 8.7 SIGNALING EXTRACTOR (SIGX) .................................................................... 40 8.8 BACKPLANE RECEIVE INTERFACE (BRIF).................................................... 41 8.9 TRANSMITTER (TRAN) .................................................................................... 41 8.10 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (PCSC)......................... 42 8.11 HDLC TRANSMITTER (XFDL) .......................................................................... 42 8.12 DIGITAL JITTER ATTENUATOR (DJAT) ........................................................... 43 8.13 TIMING OPTIONS (TOPS) ................................................................................ 47 8.14 DIGITAL E1 TRANSMIT INTERFACE (DTIF).................................................... 47 ISSUE 6 i PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... PAYLOAD LOOPBACK....................................................................... 200 13.3.2 LINE LOOPBACK ............................................................................... 201 13.3.3 DIAGNOSTIC DIGITAL LOOPBACK .................................................. 201 13.4 USING THE PER-CHANNEL SERIAL CONTROLLERS................................. 203 13.4.1 INITIALIZATION .................................................................................. 203 13.4.2 DIRECT ACCESS MODE ................................................................... 203 13.4.3 INDIRECT ACCESS MODE................................................................ 203 13.5 USING THE DIGITAL JITTER ATTENUATOR................................................. 204 13.5.1 DEFAULT APPLICATION.................................................................... 204 ISSUE 6 ii PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... USING THE PERFORMANCE MONITOR COUNTER VALUES .................... 208 13.7 RESET PROCEDURE ..................................................................................... 210 14 ABSOLUTE MAXIMUM RATINGS................................................................................ 217 15 CAPACITANCE ............................................................................................................. 218 16 D.C. CHARACTERISTICS........................................................................................... 219 17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS............................. 221 18 EQUAD I/O TIMING CHARACTERISTICS................................................................... 226 19 ORDERING AND THERMAL INFORMATION .............................................................. 240 20 MECHANICAL INFORMATION..................................................................................... 241 ISSUE 6 iii PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... REGISTER 012H, 092H, 112H, 192H: CDRC INTERRUPT STATUS ........................................ 92 REGISTER 013H, 093H, 113H, 193H: CDRC ALTERNATE LOSS OF SIGNAL STATUS ......... 94 REGISTERS 014H, 094H, 114H AND 194H: CHANNEL SELECT (0 TO 7)............................... 95 REGISTERS 015H, 095H, 115H AND 195H: CHANNEL SELECT (8 TO 15)............................. 96 ISSUE 6 iv PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... REGISTER 02AH, 0AAH, 12AH, 1AAH: FRMR CRC ERROR COUNTER - LSB .................... 121 REGISTER 02BH, 0ABH, 12BH, 1ABH: FRMR CRC ERROR COUNTER - MSB ................... 122 REGISTER 02CH, 0ACH, 12CH, 1ACH: TS16 AIS ALARM STATUS....................................... 123 REGISTER 030H, 0B0H, 130H, 1B0H: TPSC BLOCK CONFIGURATION .............................. 124 ISSUE 6 v PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... SIGX INDIRECT REGISTERS 33 (21H)- 47 (2FH) - SEGMENT 2: TYPICAL TIMESLOT SIGNALING DATA REGISTER (TSS 1-15) .................................................................. 152 SIGX INDIRECT REGISTERS 49 (31H)- 63 (3FH) - SEGMENT 2: TYPICAL TIMESLOT SIGNALING DATA REGISTER (TSS 17-31) ................................................................ 153 SIGX INDIRECT REGISTERS 64 (40H (5FH) - SEGMENT 3: TYPICAL PER-TIMESLOT PCM TRUNK CONDITIONING DATA REGISTER ....................................................... 154 ISSUE 6 vi PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... REGISTER 04CH, 0CCH, 14CH, 1CCH: CRC ERROR COUNT LSB...................................... 170 REGISTER 04DH, 0CDH, 14DH, 1CDH: CRC ERROR COUNT MSB..................................... 171 REGISTER 04EH, 0CEH, 14EH, 1CEH: LINE CODE VIOLATION COUNT LSB ..................... 172 REGISTER 04FH, 0CFH, 14FH, 1CFH: LINE CODE VIOLATION COUNT MSB..................... 173 ISSUE 6 vii PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... FIGURE 17 - RECEIVE CHANNEL INTERFACE................................................................... 182 FIGURE 18 - TRANSMIT BACKPLANE INTERFACE............................................................ 183 FIGURE 19 - TRANSMIT CHANNEL INTERFACE ................................................................ 183 FIGURE 20 - MULTIPLEXED RECEIVE BACKPLANE INTERFACE .................................... 184 FIGURE 21 - MULTIPLEXED TRANSMIT BACKPLANE INTERFACE.................................. 186 FIGURE 22 - MULTIPLEXED TRANSMIT BACKPLANE INTERFACE WITH BTXMFP=1.... 188 ISSUE 6 viii PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... TRANSMIT DATA LINK INPUT TIMING DIAGRAM.......................................... 231 FIGURE 43 - BACKPLANE RECEIVE TIMING DIAGRAM .................................................... 232 FIGURE 44 - BACKPLANE RECEIVE TIMING (RCLKOSEL = 1) DIAGRAM ....................... 233 FIGURE 45 - MULTIPLEXED BACKPLANE RECEIVE TIMING DIAGRAM .......................... 234 FIGURE 46 - RECEIVE DATA LINK OUTPUT TIMING DIAGRAM ........................................ 235 ISSUE 6 ix PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... TRANSMIT INTERFACE OUTPUT TIMING DIAGRAM ................................... 236 FIGURE 49 - TRANSMIT DATA LINK DMA INTERFACE OUTPUT TIMING DIAGRAM ....... 237 FIGURE 50 - RECEIVE DATA LINK DMA INTERFACE OUTPUT TIMING DIAGRAM.......... 238 FIGURE 51 - 128 PIN COPPER LEADFRAME PLASTIC QUAD FLAT PACK (R SUFFIX) .. 241 ISSUE 6 x PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... BACKPLANE RECEIVE TIMING, MENB INPUT HIGH (FIGURE 43).............. 232 TABLE 19 - BACKPLANE RECEIVE TIMING, MENB INPUT HIGH, RCLKOSEL = 1 (FIGURE 44) 233 TABLE 20 - MULTIPLEXED BACKPLANE RECEIVE TIMING, MENB INPUT LOW (FIGURE 45) 234 TABLE 21 - RECEIVE DATA LINK OUTPUT TIMING (FIGURE 46).................................... 235 ISSUE 6 xi PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... TRANSMIT INTERFACE OUTPUT TIMING (FIGURE 48)............................... 236 TABLE 24 - TRANSMIT DATA LINK DMA INTERFACE OUTPUT TIMING (FIGURE 49) ... 237 TABLE 25 - RECEIVE DATA LINK DMA INTERFACE OUTPUT TIMING (FIGURE 50) ..... 238 TABLE 26 - EQUAD ORDERING INFORMATION............................................................... 240 TABLE 27 - EQUAD THERMAL INFORMATION ................................................................. 240 ISSUE 6 xii PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Provides loss of signal detection, and indicates loss of frame alignment (OOF), loss of signaling multiframe alignment and loss of CRC multiframe alignment. • Supports line and path performance monitoring according to ITU-T recommendations. Accumulators are provided for counting: • CRC-4 errors to 1000 per second; ISSUE 6 1 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Optionally provides dual rail digital PCM output signals to allow BPV transparency. Also supports unframed mode. • Supports transfer of PCM and signaling data to 2.048 Mbit/s or 16.384Mbit/s backplane buses. • Can be configured to attenuate jitter on the receive side by placing the digital jitter attenuator in the receive path. ISSUE 6 2 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter. FIFO full or empty indication allows for bit-stuffing in higher rate multiplexing applications. • Supports HDB3 or AMI line code. • Provides dual rail or single rail digital PCM output signals. ISSUE 6 3 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Digital Access and Cross-Connect Systems (DACS) and Electronic DSX Cross-Connect Systems (EDSX) • E1 Frame Relay Interfaces • E1 ATM Interfaces • ISDN Primary Rate Interfaces (PRI) • SDH Byte Synchronous TU12 Mappers • Test Equipment ISSUE 6 4 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... ITU-T Blue Book, Recommendation O.162, - "Equipment to Perform in Service Monitoring on 2048 kbit/s Signals", Vol. IV, Fascicle IV.4, 1988. 11. ITU-T Recommendation Q.506, - "Operations and maintenance functions", Vol. VI, Fascicle VI.5, 1984. 12. ITU-T Recommendation Q.516, - "Operations and maintenance functions", Vol. VI, Fascicle VI.5, 1984. ISSUE 6 5 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... STANDARD PRODUCT PMC-951013 13. Transmission and Multiplexing (TM); Generic Functional Requirements for SDH Transmission Equipment, Part 1: Generic Processes and Performance", ETSI DE/TM-1015, November, 1993, Version 1.0. ISSUE 6 6 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... E1XC device are used to terminate these 21 signals. The DS-0 backplane data is transmitted and received using a 2.048 MHz system clock. ISSUE 6 PM6344 4 E1s EQUAD 4 E1s PM6344 EQUAD PM6344 4 E1s EQUAD 4 E1s PM6344 EQUAD 4 E1s PM6344 EQUAD 1 E1 PM6341 E1XC 7 PM6344 EQUAD QUADRUPLE E1 FRAMER Synchronous DS0 Services Backplane ...
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... Data Detection DJAT Digital Jitter Attenuator Optional placement RFDL HDLC Receiver * These signals are shared between all four framers. Optional connections are shown with dashed lines. 8 PM6344 EQUAD QUADRUPLE E1 FRAMER TRANSMITTER DTIF TCLKO[1:4] Digital TDP/TDD[1:4] Transmit TDN/TFLG[1:4] Interface TDLCLK/ TDLUDR[1:4] TDLSIG/ ...
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... STANDARD PRODUCT PMC-951013 Description The PM6344 Quadruple E1 Framer (EQUAD feature-rich device suitable for use in many E1 systems with a minimum of external circuitry. Each of the framers and transmitters is independently software configurable, allowing feature selection without changes to external wiring. On the receive side, the EQUAD recovers clock and data and can be configured to frame to a basic G ...
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... EQUAD device. Serial PCM interfaces allow 2.048 Mbit/s backplanes to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic. Optional bit interleaved multiplexing of the individual serial streams supports 16.384 Mbit/s backplanes. ISSUE 6 10 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... TDP[4]/TDD[4] TDN[4]/TFLG[4] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] PIN 38 PIN 39 ISSUE 6 Index Pin PM6344 EQUAD Top View 11 PM6344 EQUAD QUADRUPLE E1 FRAMER PIN 103 PIN 102 BRSIG[4]/BRDN[4] BRSIG[3]/BRDN[3] BRSIG[2]/BRDN[2] BRSIG[1]/BRDN[1] BRFPO[4] BRFPO[3] BRFPO[2] BRFPO[1] BRCLK/MRCLK BRFPI/MRFPI RCLKO[4] RCLKO[3] PLA[2] PHA[2] RCLKO[2] RCLKO[1] ...
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... RCLKI[4:1]. When enabled for RZ, the clocks are recovered from the corresponding RDP[4:1] and RDN[4:1] inputs. Receive Digital E1 Signal (RDD[4:1]). When the EQUAD is configured to receive single-rail data, these inputs may be enabled to be sampled on the rising or falling edge of the corresponding RCLKI[4:1]. 12 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... When the ELST is by-passed or the RCLKOSEL register bit is set, BRPCM[x] and BRSIG[x] are updated on the falling edge of the associated RCLKO[x option, the digital attenuator's smooth 2.048 MHz clock may be presented on RCLKO[x]. See the Operations Section for details on this application. 13 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... CRC multiframe alignments are coincident, RFP[x] will pulse high for 1 RCLKO[x] cycle every 16 frames. Each RFP[x] is updated on the falling edge of the associated RCLKO[x]. RFP[x] should not be used when register bit RCLKOSEL is set to a logic 1. 14 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Receive Data Link End of Message (RDLEOM[4:1]). The RDLEOM[4:1] signals are available on these outputs when the associated RFDL is enabled. Each RDLEOM[x] goes high when the last byte of a received sequence is read from the associated RFDL FIFO buffer, or when the FIFO buffer is overrun. 15 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Mbit/s serial stream presented on MRD aligned with MRFPI. MRFPI is sampled on the rising edge of MRCLK and MRD is updated on the falling edge of MRCLK. When MENB input is deasserted high, each PCM and signaling stream has its own dedicated pin and MRD is unused. 16 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... The BRDN[4:1] signals are available on these outputs when the backplane is configured for dual-rail output. Each BRDN[x] NRZ output represents the RZ receive digital negative pulse signal extracted from the input bipolar signal. BRDN[x] is updated on the falling edge of the associated RCLKO[x]. 17 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... BRFPO[x] will pulse high for 1 clock cycle. When configured for backplane receive overhead output, BRFPO[x] is high for timeslot 0 and timeslot 16 of each 256-bit frame, indicating the overhead bit positions of the BRPCM[x] data stream. BRFPO[x] is updated on the falling edge of the BRCLK or RCLKO[x]. 18 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... PCM and signaling streams to allow bit interleaved multiplexing. If frame alignment only is required, a pulse no more than 1 MRCLK cycle wide must be provided on each MRFPI every 2048 bit periods. 19 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... When the multiplex enable (MENB) input is asserted low, the four sets of PCM and signaling streams are expected in a single bit interleaved 16.384 Mbit/s serial stream. Frame alignment is indicated by MTFP. MTD is sampled on the rising edge of MTCLK. 20 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... In dual- rail input mode, the BTDN[x] input by-passes the transmitter and is fed directly into the DJAT. BTDN[x] is sampled on the rising edge of the associated BTCLK[x]. These inputs are unused when the multiplex enable (MENB) input is asserted low. 21 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... E1 channel from the TDLSIG pin, the BTFP input must have a valid frame pulse applied. The insertion of the transmit fractional E1 channel will not operate correctly if the BTFP is tied to logic high or low. If frame alignment is not required, BTFP[x] may be tied to logic high or low. 22 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Multiplexed Transmit Clock (MTCLK). MTCLK shares a pin with BTCLK[1]. BTCLK[4:2] are unused when the multiplex enable (MENB) input is asserted low. When the multiplex enable (MENB) input is asserted low, this clock is 16.384 MHz. MTFP and MTD are sampled on the rising edge of MTCLK. 23 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... E1 is disabled, the TDLCLK[x] output is held low. Transmit Data Link Underrun (TDLUDR[4:1]). The TDLUDR[4:1] signals are available on this output when the associated XFDL is enabled. TDLUDR[x] goes high when the processor has failed to service the TDLINT[x] interrupt before the transmit buffer is emptied. 24 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... The TFLG[x] output indicates when the transmit rate conversion FIFO in DJAT is nearing an empty or a full condition. Either indication may be selected. This output may be enabled to be updated on the rising or falling edge of the associated TCLKO[x]. 25 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Active low chip select (CSB). This signal must be low to enable EQUAD register accesses. This signal must be toggled high to clear the PMCTST register bit (register 00BH or 20BH) and to ensure the EQUAD will operate in normal mode. 26 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Address bus (A[9:0]). This bus selects specific registers 31 during EQUAD register accesses power pins (PHA[4:0]). These pins must be 52 connected to a common, well decoupled +5V DC supply 89 together with the DC power pins PHD[3:0] . 105 121 27 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... DC 90 ground pins PLD[3:0]. 106 122 ground pins (PLD[3:0]). These pins must be 51 connected to a common ground together with the AC 86 ground pins PLA[5:0]. 116 These power supply connections must 28 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... TDLINT[x] request for more data before a specific time-out period. This period is dependent upon the frequency of TDLCLK[x]: 1) for a TDLCLK[x] frequency of 4 kHz, the time-out is 1.0 ms; 2) for a TDLCLK[x] frequency of 20 kHz, the time-out is 0.2 ms; 3) for a TDLCLK[x] frequency of 64 kHz, the time-out is 62.5 µs. ISSUE 6 29 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... The input jitter tolerance for E1 interfaces complies with ITU-T Recommendation G.823. The tolerance is measured with with ALGSEL set to 1 and shown in Figure 2 and Figure 3. ISSUE sequence. The E1 jitter tolerance 30 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... STANDARD PRODUCT PMC-951013 Figure 2 - CDRC jitter tolerance with ALGSEL = 1 Measurement Limit 10 1.0 G823 Jitter Tolerance Specification 0.1 0.01 . ISSUE 6 Jitter Frequency (Hz) 31 PM6344 EQUAD QUADRUPLE E1 FRAMER Measured CDRC Jitter Tolerance (ALGSEL = 1) ...
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... PMON block. Once the FRMR has found CAS multiframe alignment, the PCM data is continuously monitored for CAS multiframe alignment pattern errors. Once the ISSUE 6 G823 Jitter Tolerance Specification Jitter Frequence (Hz) 32 PM6344 EQUAD QUADRUPLE E1 FRAMER Measured CDRC Jitter Tolerance (ALGSEL = 0) ...
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... The first algorithm finds frame alignment by using the following sequence: 1. Search for the presence of the correct 7-bit FAS; 2. Check that the FAS is absent in the following frame by verifying that bit 2 of the assumed timeslot 0 byte is a logic 1; ISSUE 6 33 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... These algorithms are illustrated in Figure 4. ISSUE 6 34 PM6344 EQUAD QUADRUPLE E1 FRAMER 15 -1 pseudo ...
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... Frame alignment in following established frame Bit 2=1 check occurrence of 7-bit FAS in next frame FAS Found Frame alignment established 35 PM6344 EQUAD QUADRUPLE E1 FRAMER not found Algorithm #2: Bit 2 =0 Wait for byte location in next frame Algorithm #2: Bit 2 =0 FAS Found & No Check Sequence selected ...
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... FEBE bits (bit 1 of frames 13 and 15 of the multiframe).The block declares loss of CRC multiframe alignment if four consecutive CRC multiframe alignment signals have been received in error frame alignment has been lost. ISSUE 6 36 PM6344 EQUAD QUADRUPLE E1 FRAMER -3 bit error rate and -3 bit error rate. The ...
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... This block also indicates the reception of timeslot 16 AIS when timeslot 16 has been all-ones for two consecutive frames while out of CAS multiframe. The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe alignment signals have been received in error, or ISSUE 6 37 PM6344 EQUAD QUADRUPLE E1 FRAMER -3 bit ...
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... An interval with valid INF indication decrements the interval counter; the RED Alarm declaration is removed when the counter reaches 0. This algorithm biases OOF occurrences, leading to declaration of red alarm when intermittent loss of frame alignment occurs. ISSUE 6 38 PM6344 EQUAD QUADRUPLE E1 FRAMER -3 mean bit error ...
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... FIFO buffer. Interrupts are also generated when the terminating flag sequence, abort sequence, or FIFO buffer overrun are detected. When the internal HDLC receiver is disabled, the serial data extracted by the FRMR block is output on the RDLSIG[x] pin and is updated on the falling clock edge of the RDLCLK[x] pin. ISSUE 6 39 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... The SIGX selectively debounces the bits, and serializes the results onto the 2048 kbit/s serial stream BRSIG[x] output. Buffered signaling data is aligned with its associated voice timeslot in the E1 frame. ISSUE 6 40 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Common Channel Signaling (CCS) is supported in time slot 16 either through the internal HDLC Transmitter (XFDL) or through a serial data input and clock output. Support is provided for the transmission of AIS and TS16 AIS, and the transmission of remote alarm and remote multiframe alarm signals. ISSUE 6 41 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... CRC insertion has not been enabled) is transmitted. The XFDL then returns to the transmission of flag characters. If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort characters. ISSUE 6 42 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... If the FIFO read pointer (timed to TCLKO[x]) comes within one bit of the write pointer (timed to the input data clock, BTCLK[x] or RCLKO[x]), DJAT will track the jitter of the input clock. This permits the phase jitter to pass through unattenuated, inhibiting the loss of data. ISSUE 6 43 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... For DJAT, the input jitter tolerance is 35 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 308 Hz UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK divided by 24 and that of the input data clock. ISSUE 6 44 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Given that the DJAT PLL reference clock accuracy can be ±103 Hz from 2.048 MHz, and that the XCLK input accuracy can be ±100 ppm from 49.152 MHz, the minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK/24 are shown in Figure 6. ISSUE 6 45 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... The output jitter for jitter frequencies from more than 0.1 dB greater than the input jitter, excluding the residual jitter. Jitter frequencies above 8.8 Hz are attenuated at a level per octave, as shown in Figure 7. ISSUE 6 200 49 46 PM6344 EQUAD QUADRUPLE E1 FRAMER 42.4 39 34.9 300 308 Hz 100 ± ...
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... TDP/TDD[x] and TDN/TFLG[x]. When configured for dual-rail output, the multifunctional pins become the TDP[x] and TDN[x] outputs. These outputs can be formatted as either return-to-zero (RZ) or non-return-to-zero (NRZ) signals and can be ISSUE 6 47 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... PCM stream. All four multiplexed interfaces will have the same frame, signaling multiframe, and CRC multiframe alignment. See the Functional Timing section for more details. 8.16 Microprocessor Interface (MPIF) The Microprocessor Interface allows the EQUAD to be configured, controlled and monitored via internal registers. ISSUE 6 48 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Phase Status Word (LSB) 10FH 18FH Phase Status Word (MSB) 110H 190H CDRC Configuration 111H 191H CDRC Interrupt Enable 112H 192H CDRC Interrupt Status 113H 193H Alternate Loss of Signal 114H 194H Channel Select ( PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... FRMR Maintenance/Alarm Status Interrupt Indication 126H 1A6H FRMR Framing Status 127H 1A7H FRMR Maintenance/Alarm Status 128H 1A8H FRMR International/National Bits 129H 1A9H FRMR Extra Bits 12AH 1AAH FRMR CRC Error Count - LSB 12BH 1ABH FRMR CRC Error Count - MSB 50 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... Backplane Parity Configuration and Status 13EH 1BEH Reserved 13FH 1BFH Reserved 140H 1C0H SIGX Configuration 141H 1C1H SIGX µP Access Status 142H 1C2H SIGX Timeslot Indirect Address/Control 143H 1C3H SIGX Timeslot Indirect Data Buffer 144H 1C4H TRAN Configuration 51 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... PMON FEBE Count (MSB) 14CH 1CCH PMON CRC Count (LSB) 14DH 1CDH PMON CRC Count (MSB) 14EH 1CEH PMON LCV Count (LSB) 14FH 1CFH PMON LCV Count (MSB) 150H- 1D0H- Reserved 17FH 1FFH Reserved for Test 52 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... EQUAD to determine the programming state of the chip. 4. Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted. 5. Writing into read-only normal mode register bit locations does not affect EQUAD operation unless otherwise noted. ISSUE 6 53 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... The TRSLIP bit allows the ELST block to be used to measure, through SLIP indications, the frequency difference between the recovered receive line clock and the transmit clock driving the TRAN block when the ELST is bypassed. ISSUE 6 Function Default WORDERR 0 CNTNFAS 0 ELSTBYP 0 TRSLIP 0 Unused X SRSMFP 0 SRCMFP 0 TRKEN 0 54 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... RFP[x] pulses high for 1 RCLKO[x] cycle during bit 1 of frame 1 of the 16 frame signaling multiframe, indicating the signaling multiframe alignment of the RDLSIG[x] fractional E1 data stream. (Even when signaling multiframing is disabled, the RFP[x] output continues to indicate the position of bit 1 of every 16 th frame.) 55 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... RDLSIG[x] fractional E1 data stream. This mode allows both multiframe alignments to be decoded externally from the single RFP[x] signal. Note that if the signaling and CRC multiframe alignments are coincident, RFP[x] will pulse high for 1 RCLKO[x] cycle every 16 frames. 56 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... BRPCM/BRDP[x] and BRSIG/BRDN[x] are in either dual rail or single rail format. When BRX2RAIL is set to logic 1, the multifunction pins become the BRDP[x] and BRDN[x] dual rail outputs, which contain the ISSUE 6 Function Default RCLKOSEL 0 Unused X RXDMAGAT 0 ROHM 0 BRX2RAIL 0 BRXSMFP 0 BRXCMFP 0 OOSMFAIS 0 57 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... RCLKOSEL is set to logic 1) during bit 1 of frame 1 of every 16 frame CRC multiframe, indicating the CRC multiframe alignment of the BRPCM[x] data stream. (Even when CRC multiframing is disabled, the BRFPO[x] output continues to indicate the position of bit 1 of the FAS frame every th 16 frame). 58 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... BRFPO[x] will pulse high for 1 BRCLK cycle (or RCLKO[x] cycle if ELST is by-passed or RCLKOSEL is set to logic 1) every 16 frames. X Backplane receive overhead output: BRFPO[x] is high for timeslot 0 and timeslot 16 of each 256-bit frame, indicating the overhead of the BRPCM[x] data stream. 59 PM6344 EQUAD QUADRUPLE E1 FRAMER th ...
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... RDLSIG[x] with an aligned burst clock output on RDLCLK[x]. When RFRACE1 is set to logic 0, the RDLINT/RDLSIG[x] and RDLEOM/RDLCLK[x] pins contain the signals selected by the RXDMASIG bit. ISSUE 6 Function Default RXDMASIG 0 RFRACE1 0 TXDMASIG 0 TFRACE1 0 RDLINTE 0 RDLEOME 0 TDLINTE 0 TDLUDRE 0 60 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... When RDLINTE is set to logic 1, an event causing an interrupt in the RFDL (which is visible on the RDLINT output pin when RXDMASIG is logic 1) also causes an interrupt to be generated on the INTB output. When RDLINTE is set to logic 0, an interrupt event in the RFDL does not cause an interrupt on INTB. ISSUE 6 61 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
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... TXDMASIG is logic 1) also causes and interrupt to be generated on the INTB output. When TDLUDRE is set to logic 0, an underrun event in the XFDL does not cause an interrupt on INTB. Upon reset of the EQUAD, these bits are cleared to zero. ISSUE 6 62 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 76
... RDN/RLCV[x] signal unaltered. RUNI: The RUNI bit enables the interface to receive unipolar digital data and line code violation indications on the multifunction pins RDP/RDD[x] and ISSUE 6 Function Default Unused X Unused X BPV 0 RDNINV 0 RDPINV 0 RUNI 0 RFALL 0 Unused X 63 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 77
... RCLKI[x] edge. When RFALL is set to logic 1, the interface is enabled to sample either the RDD[x] and RLCV[x] inputs, or the RDP[x] and RDN[x] inputs, on the falling RCLKI[x] edge. When RFALL is set to logic 0, the interface is enabled to sample the inputs on the rising RCLKI[x] edge. ISSUE 6 64 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 78
... When TAISEN is set to logic 0, the TDP/TDD[x] and TDN[x] multifunction outputs operate normally. The transition to transmitting AIS on the TDP[x] and TDN[x] outputs is done in such a way as to not introduce any bipolar violations. ISSUE 6 Function Default FIFOBYP 0 TAISEN 0 TDNINV 0 TDPINV 0 TUNI 0 FIFOFULL 0 TRISE 0 TRZ 0 65 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 79
... TDP[x] and TDN[x] output signals as NRZ waveforms with duration equal to the TCLKO[x] period, updated on the selected edge of TCLKO[x]. The TRZ bit can only be used when TUNI and TRISE are set to logic 0. ISSUE 6 66 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 80
... STANDARD PRODUCT PMC-951013 When the system is reset, the contents of the register are set to logic 0, enabling the Transmit Interface to output NRZ formatted positive and negative pulse data on the TDP[x] and TDN[x] outputs, updated on the falling TCLKO[x] edge. ISSUE 6 67 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 81
... BTPCM/BTDP[x] and BTSIG/BTDN[x] are in either dual-rail or single-rail format. When BTX2RAIL is set to logic 1, the multifunction pins become the BTDP[x] and BTDN[x] ISSUE 6 Function Default Unused X Unused X BTFPREF 0 Unused X BTXCLK 0 Unused X BTX2RAIL 0 BTXMFP 0 68 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 82
... PCM stream of every 16 frame CRC multiframe. All four interfaces will have the same frame alignment. Upon reset of the EQUAD, these bits are cleared to zero. ISSUE 6 69 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 83
... Slot 0 of non-frame alignment signal frames. If the TXSA8EN bit is logic 1, the TDLSIG[x] value is written into bit 8 of Time Slot 0 of non-frame alignment signal frames. The other enable bits operate in an analogous fashion. A ISSUE 6 Function Default PATHCRC 0 Unused X Unused X TXSA4EN 1 TXSA5EN 0 TXSA6EN 0 TXSA7EN 0 TXSA8EN 0 70 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 84
... Use bits which are not included in the data link are sourced from either BTPCM[x] or the TRAN block International/National Control register. Upon reset of the EQUAD, all bits are logic 0 except TXSA4EN. By default kbit/s data link is inserted into Sa4 from the TDLSIG[x] input. ISSUE 6 71 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 85
... When OCLKSEL1 is set to logic 1, the DJAT FIFO output clock is driven with the input data clock driving the DJAT ICLK input. In this mode the jitter attenuation is disabled and the input clock must be jitter-free. ISSUE 6 Function Default HSBPSEL 0 XCLKSEL 0 OCLKSEL1 0 OCLKSEL0 0 PLLREF1 0 PLLREF0 0 TCLKISEL 0 SMCLKO 0 72 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 86
... The following table illustrates the required bit settings for these various clock sources to affect the transmitted data: ISSUE 6 Source of PLL Reference 0 Transmit clock used by TRAN ( either the 2.048MHz BTCLK[x] or the 2.048MHz RCLKO[x], as selected by the BTXCLK register bit) 1 BTCLK[x] input 0 RCLKO[x] output 1 TCLKI[x] input 73 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 87
... PLLREF0 =X 16.384MHz TCLKISEL =0 SMCLKO =0 XCLKSEL =1 TCLKISEL =1 SMCLKO =1 DJAT SYNC =0 74 PM6344 EQUAD QUADRUPLE E1 FRAMER Data Jitter attenuated. TCLKO[ smooth 2.048 MHz. TCLKO[x] referenced to BTCLK[x]. TCLKO[x] referenced to RCLKO[x]. TCLKO[x] referenced to TCLKI[x]. Jitter attenuated. TCLKO[ smooth 2.048MHz. TCLKO[x] referenced to externally "gapped" ...
Page 88
... XCLKSEL =1 OCLKSEL1 =0 OCLKSEL0 =0 PLLREF1 =X PLLREF0 =X TCLKISEL =1 SMCLKO =1 75 PM6344 EQUAD QUADRUPLE E1 FRAMER Data No jitter attenuation. TCLKO[x] is equal to TCLKI[x] (useful for higher rate MUX applications). Same as above. TCLKI[ jitter-free 16.384MHz clock. TCLKO[x] is equal to 1 TCLKI[x]÷8. Same as above. XCLK is a jitter-free 16 ...
Page 89
... PLL Smooth PLLREF[1:0] 16.384 MHz 10 24X reference clock for jitter attenuation 11 ÷ TCLKISEL 0 1 XCLKSEL 0 1 HSBPSEL 76 PM6344 EQUAD QUADRUPLE E1 FRAMER FIFO output TCLKO[x] data clock 0 1 OCLKSEL1 OCLKSEL0 "Jitter-free" 1 2.048MHz SMCLKO 0 "Jitter-free" 1 16.384MHz "High-speed" clock for CDRC & FRMR (=16.384MHz) " ...
Page 90
... SACI bit (register 009H, Receive TS0 Data Link Enable register) is the source of the interrupt. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication. ISSUE 6 Function Default DJAT 0 PARITY 0 FRMR/SA 0 PMON 0 ELST 0 RFDL 0 XFDL 0 CDRC 0 77 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 91
... Slot 0 of non-frame alignment signal frames. The other enable bits operate in an analogous fashion. A clock pulse is generated on RDLCLK[x] for each enable that is logic 1. Any combination enable bits is allowed resulting in a data rate between 4 kbit/s and 20 kbit/s. ISSUE 6 Function Default Unused X SACE 0 SACI 0 RXSA4EN 1 RXSA5EN 0 RXSA6EN 0 RXSA7EN 0 RXSA8EN 0 78 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 92
... RDLINT/RDLSIG[x] and RDLEOM/RDLCLK[ set to logic has the highest priority over the control of these outputs. Upon reset of the EQUAD, all bits are logic 0 except RXSA4EN. By default kbit/s data link is extracted from Sa4 and presented on the RDLSIG output. ISSUE 6 79 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 93
... The DDLB bit selects the diagnostic digital loopback mode, where the transmit side outputs from DJAT are internally connected to the receive side inputs. When DDLB is set to logic 1, the diagnostic digital loopback mode is ISSUE 6 Function Default Unused X Unused X PAYLB 0 LINELB 0 Unused X DDLB 0 Unused X TXDIS 0 80 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 94
... When TXDIS is set to logic 0, the digital output of TRAN is not suppressed. Zeroing of the transmitter takes place before HDB3 encoding. In order to generate an all-zero's output, TXDIS and AMI encoding (in the E1 TRAN Configuration register) should be set. Upon reset of the EQUAD, these register bits are cleared to zero. ISSUE 6 81 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 95
... PMC manufacturing test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and is cleared by setting CSB to logic 1. ISSUE 6 Function Default TST X A_TM[8] X A_TM[7] X PMCTST X DBCTRL 0 IOTST 0 HIZDATA 0 HIZIO 0 82 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 96
... While the HIZIO bit is a logic 1, all output pins of the EQUAD except the data bus are held in a high-impedance state. The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is also held in a high- impedance state which inhibits microprocessor read cycles. ISSUE 6 83 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 97
... The version identification bits, ID[4:0], are set to a fixed value representing the version number of the EQUAD. The chip identification bits, TYPE[2:0], is set to logic 1 representing the EQUAD. Writing any value to this register causes all performance monitor counters to be updated simultaneously. ISSUE 6 Function Default TYPE[2] 0 TYPE[1] 0 TYPE[0] 1 ID[4] 0 ID[3] 0 ID[2] 0 ID[1] 0 ID[ PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 98
... Holding the framer in a reset state effectively puts it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus deasserting the software reset. ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X RESET 0 85 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 99
... PSB[7:6] bits of the current phase status word value to those of the previous word value; PSB[8] is toggled only under the following conditions (all other bit value transitions leave PSB[8] unchanged): ISSUE 6 Function Default PSB[7] X PSB[6] X PSB[5] X PSB[4] X PSB[3] X PSB[2] X PSB[1] X PSB[ PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 100
... It is important to read the MSB register before the LSB register because, once the Phase Status Word (LSB) register has been read, the phase status word counter is unfrozen and the contents may change immediately. ISSUE 6 Current PSB[7: PM6344 EQUAD QUADRUPLE E1 FRAMER Effect on PSB[8] toggle toggle ...
Page 101
... LSB register because, once the Phase Status Word (LSB) register has been read, the phase status word counter is unfrozen and the contents may change immediately. ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X PSB[ PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 102
... Asserting the DCR bit disables clock recovery. With DCR high, the recovered clock (RCLKO[x]) is derived from RCLKI[x] instead of being recovered from the RDP[x] and RDN[x] inputs. ISSUE 6 Function Default AMI 0 LOS1 0 LOS0 0 DCR 0 Reserved 0 ALGSEL 0 O162 0 Unused X LOS0 Threshold (PCM periods 175 89 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 103
... HDB3 signature that is the same polarity as the last bipolar violation results in a line code violation indication O162 is a logic 1, a line code violation is indicated if a bipolar violation is of the same polarity as the last bipolar violation, as per ITU-T Recommendation O.162. ISSUE 6 90 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 104
... The occurrence of any of these events will generate an interrupt if there is a logic 1 in the corresponding bit position. When the EQUAD is reset, Z4DE, HDB3E, LOSE, and LCVE bits are set to logic 0, disabling any interrupt generation. ISSUE 6 Function Default LCVE 0 LOSE 0 HDB3E 0 Z4DE 0 Unused X Unused X Unused X Unused X 91 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 105
... Z4DI: The Z4DI bit is set high if four consecutive spaces occur. ISSUE 6 Function Default LCVI X LOSI X HDB3I X Z4DI X Unused X Unused X Unused X LOS X 92 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 106
... STANDARD PRODUCT PMC-951013 LOS: The LOS bit is the loss of signal status logic 1 if the number of consecutive spaces exceeds the programmed threshold. The status is deasserted upon the reception of a single mark. ISSUE 6 93 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 107
... The ALTLOS bit is asserted when the number of consecutive zeros exceeds the threshold specified by the CDRC Configuration register. The ALTLOS bit is deasserted only after 255 bit periods during which no sequence of four zeros has been received. ISSUE 6 Function Default ALTLOSE 0 ALTLOSI X Unused X Unused X Unused X Unused X Unused X ALTLOS X 94 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 108
... STANDARD PRODUCT PMC-951013 Registers 014H, 094H, 114H and 194H: Channel Select ( Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W ISSUE 6 Function Default CH[7] 0 CH[6] 0 CH[5] 0 CH[4] 0 CH[3] 0 CH[2] 0 CH[1] 0 CH[ PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 109
... STANDARD PRODUCT PMC-951013 Registers 015H, 095H, 115H and 195H: Channel Select (8 to 15) Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W ISSUE 6 Function Default CH[15] 0 CH[14] 0 CH[13] 0 CH[12] 0 CH[11] 0 CH[10] 0 CH[9] 0 CH[ PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 110
... STANDARD PRODUCT PMC-951013 Registers 016H, 096H, 116H and 196H: Channel Select (16 to 23) Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W ISSUE 6 Function Default CH[23] 0 CH[22] 0 CH[21] 0 CH[20] 0 CH[19] 0 CH[18] 0 CH[17] 0 CH[16 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 111
... TS0 by the TRAN block. If CH[16] is set to logic 1, the TDLSIG[x] input will be inserted into TS16 regardless of the settings of the SIGEN and DLEN bits of the TRAN Configuration register. ISSUE 6 Function Default CH[31] 0 CH[30] 0 CH[29] 0 CH[28] 0 CH[27] 0 CH[26] 0 CH[25] 0 CH[24 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 112
... The UNDI bit is asserted when an attempt is made to read data from the FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X OVRI 0 UNDI 0 99 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 113
... Writing to this register will reset the PLL and, if the SYNC bit in the DJAT Configuration register is high, will also reset the FIFO. Upon reset of the EQUAD, the default value set to decimal 47 (2FH). Consult the Operations section for clarification of divisor selection criteria. ISSUE 6 Function Default N1[7] 0 N1[6] 0 N1[5] 1 N1[4] 0 N1[3] 1 N1[2] 1 N1[1] 1 N1[0] 1 100 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 114
... Writing to this register will reset the PLL and, if the SYNC bit is high, will also reset the FIFO. Upon reset of the EQUAD, the default value set to decimal 47 (2FH). Consult the Operations section for clarification of divisor selection criteria. ISSUE 6 Function Default N2[7] 0 N2[6] 0 N2[5] 1 N2[4] 0 N2[3] 1 N2[2] 1 N2[1] 1 N2[0] 1 101 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 115
... UNDE is set to logic 1, an overrun event or underrun event, respectively, is allowed to generate an interrupt on the INTB pin. When OVRE or UNDE is set to logic 0, the FIFO error events are disabled from generating an interrupt. ISSUE 6 Function Default Unused X Unused X Reserved 1 CENT 0 UNDE 0 OVRE 0 SYNC 1 LIMIT 1 102 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 116
... When LIMIT is set to logic 1, the PLL jitter attenuation is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally. Upon reset of the EQUAD, the LIMIT and SYNC bits are set to logic 1, and the OVRE, UNDE, and CENT bits are set to logic 0. ISSUE 6 103 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 117
... The OR bit selects the output frame format. The OR bit must be set to logic 1 to properly generate the E1 frame format output from the ELST. SETTING OR TO LOGIC RESERVED SETTING AND SHOULD NOT BE USED. ISSUE 6 Function Default ACCEL 0 Unused X Unused X Unused X Unused X Unused 104 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 118
... The SLIPI bit is set if a slip occurred since the last read of the Interrupt Status register. The SLIPI bit is cleared just after the Interrupt Status register read operation. ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X SLIPE 0 SLIPD X SLIPI X 105 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 119
... The writing of the idle code pattern is asynchronous with respect to the output data clock. One timeslot of idle code data will be corrupted if the register is written to when the framer is out of frame. ISSUE 6 Function Default 106 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 120
... AFAA: The AFAA bit enables an alternate framing algorithm. If AFAA is a logic zero, frame alignment is declared after a correct FAS, a logic 1 in bit 2 of time slot ISSUE 6 Function Default CRCEN 0 CASDIS 0 AFAA 0 CHKSEQ 0 CASA 0 REFR 0 REFCRCE 0 REFRDIS 0 107 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 121
... CRC errors, etc.). Note that while the FRMR remains locked in frame due to REFRDIS=1, a received AIS will not be detected since the FRMR must be out-of-frame to detect AIS. ISSUE 6 108 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 122
... T16C. ISSUE 6 Function Default FASC 0 BIT2C 0 SMFASC 0 T16C 0 RADEB 0 RMADEB 0 CMFACT X EXCRCE X 109 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 123
... The EXCRCE bit is an active high status bit indicating that excessive CRC evaluation errors (i.e. ≥915 error in one second) have occurred, thereby initiating a reframe if enabled by the REFCRCE bit of the Frame Alignment Options register. The EXCRCE bit is reset to logic 0 after the register is read. ISSUE 6 110 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 124
... CMFERE: A logic one in the CMFERE bit enables the generation of an interrupt when an error has been detected in the CRC multiframe alignment signal. ISSUE 6 Function Default Unused X OOFE 0 OOSMFE 0 OOCMFE 0 COFAE 0 FERE 0 SMFERE 0 CMFERE 0 111 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 125
... Si bits of frames 13 or 15. CRCEE: When the CRCEE bit is a logic one, an interrupt is generated when calculated CRC differs from the received CRC remainder. ISSUE 6 Function Default RRAE 0 RRMAE 0 AISDE 0 T16AISDE 0 REDE 0 AISE 0 FEBEE 0 CRCEE 0 112 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 126
... The contents of this register are cleared to logic 0 after the register is read; the interrupt is also cleared if it was generated by any of the Framing Status outputs. ISSUE 6 Function Default Unused X OOFI X OOSMFI X OOCMFI X COFAI X FERI X SMFERI X CMFERI X 113 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 127
... The contents of this register are cleared to logic 0 after the register is read; the interrupt is also cleared if it was generated by one of the Maintenance/Alarm Status events. ISSUE 6 Function Default RRAI X RRMAI X AISDI X T16AISDI X REDI X AISI X FEBEI X CRCEI X 114 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 128
... CRC Multi-frame Find algorithm has been active for more than 8 ms. This bit is intended to be used for compatibility with ITU-T G.706 section 4.2, note 2. ISSUE 6 Function Default Unused X OOF X OOSMF X OOCMF X Unused X Unused X 8MSDIS8MSDIS 00 MFASDISE 0 115 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 129
... OOF = 1. When MFASDIS is a logic 1, CRC Multiframe alignment, once found, will not be lost unless there is a loss of basic frame alignment or excessive CRC errors (> 915 per second) occur. This bit should be set to logic 1 for compliance to ITU-T G.706. ISSUE 6 116 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 130
... AISD bit is updated every 512 bit times. TS16AISD: The TS16AISD is a logic one after an all-ones byte has been detected in time slot 16 for 2 consecutive frames while out of signaling multiframe alignment. ISSUE 6 Function Default RRA X RRMA X AISD X T16AISD X RED X AIS X Unused X Unused X 117 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 131
... AIS: The AIS bit is a logic one when an out of frame all-ones condition has persisted for 100 ms. The AIS bit returns to a logic zero when the AIS condition has been absent for 100 ms. ISSUE 6 118 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 132
... The Si0, RAWRA and Sn0-Sn4 bits map to the TSO NFAS as follows Si0 1 RAWRA ISSUE 6 Function Default Si1 X Si0 X RAWRA X Sn0 X Sn1 X Sn2 X Sn3 X Sn4 X Bit Position Sn0 Sn1 119 PM6344 EQUAD QUADRUPLE E1 FRAMER Sn2 Sn3 Sn4 ...
Page 133
... If the X3, X1, X0 bits are to be interpreted as binary values, care should be taken to ensure a coherent set of bit values by reading the register at least twice. ISSUE 6 Function Default Unused X Unused X Unused X Unused RAWRMA 120 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 134
... Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R This register contains the least significant byte of the 10-bit CRC error counter value, updated every second. ISSUE 6 Function Default CRCE7 X CRCE6 X CRCE5 X CRCE4 X CRCE3 X CRCE2 X CRCE1 X CRCE0 X 121 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 135
... This CRC error count is distinct from that of PMON because it is guaranteed accurate count of the number of CRC error in one second; whereas, PMON relies on externally initiated transfers which may not be one second apart. ISSUE 6 Function Default OVR 0 NEWDATA 0 Unused X Unused X Unused X Unused X CRCE9 X CRCE8 X 122 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 136
... The TS16AIS bit is a logic one when an all ones condition has persisted in time slot 16 for 3 ms. The bit returns to a logic zero when the time slot 16 AIS condition has been absent for 3 ms. ISSUE 6 Function Default Unused X TS16AISE 0 TS16AISI X T16AIS X Unused X Unused X Unused X Unused X 123 PM6344 EQUAD QUADRUPLE E1 FRAMER -3 mean bit error ...
Page 137
... Data Control byte and IDLE Code byte are passed on to the TRAN block. When the PCCE bit is set to logic 0, the per- timeslot functions are disabled. ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X IND 0 PCCE 0 124 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 138
... During normal operation, the Status Register should be polled until the BUSY bit goes low before another µP access request is initiated. A µP access request is typically completed within 480 ns. ISSUE 6 Function Default BUSY 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X 125 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 139
... The R/WB bit selects the operation to be performed on the addressed register: when R/WB is set to a logic 1, a read from the internal TPSC register is requested; when R/WB is set to a logic 0, an write to the internal TPSC register is requested. ISSUE 6 Function Default R/ 126 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 140
... PCM data, provide the per-timeslot Transmit IDLE Code, and provide the per- timeslot Transmit signaling control and the alternate signaling bits. The functions are allocated within the registers as follows: ISSUE 6 Function Default 127 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 141
... Data Control byte for Time Slot 31 IDLE Code byte for Time Slot 0 IDLE Code byte for Time Slot 1 IDLE Code byte for Time Slot 2 • • • IDLE Code byte for Time Slot 30 IDLE Code byte for Time Slot 31 128 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 142
... INV - data inversion on all timeslot bits 0 X Data substitution on - IDLE code replaces PCM timeslot data 1 0 Data substitution on - A-Law digital milliwatt pattern * replaces TPCM timeslot data Data substitution on - µ-Law digital milliwatt pattern * replaces TPCM timeslot data. 129 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 143
... Bit 5 Bit 130 PM6344 EQUAD QUADRUPLE E1 FRAMER Bit 7 Bit Bit 7 Bit ...
Page 144
... BTPCM when the SUBS bit in the PCM Control Byte is set to a logic 1 and the DS[0] bit in the PCM Control Byte is set to a logic 0. The IDLE Code is transmitted from MSB (bit 7) to LSB (bit 0). ISSUE 6 Function IDLE7 IDLE6 IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0 131 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 145
... Setting the CRC bit to logic 1 enables the ITU-T-CRC generator and the appends the 16 bit FCS to the end of each message. When the CRC bit is set to logic 0, the FCS is not appended to the end of the ISSUE 6 Function Default Unused X Unused X Unused X EOM 0 INTE 0 ABT 0 CRC 132 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 146
... The enable bit (EN) controls the overall operation of the XFDL block. When the EN bit is set to a logic 1, the XDFL block is enabled and flag sequences are sent until data is written into the XFDL Transmit Data register. When the EN bit is set to logic 0, the XFDL block is disabled. ISSUE 6 133 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 147
... XFDL will continuously transmit the all-ones idle pattern. The UDR bit can only be cleared by writing a logic 0 to the UDR bit position in this register. ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X INT 1 UDR 0 134 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 148
... Status register high. When INT and/or TDLINT[x] is set, the Transmit Data register must be written with the new data within 4 data bit periods to prevent the occurrence of an underrun. ISSUE 6 Function Default TD7 X TD6 X TD5 X TD4 X TD3 X TD2 X TD1 X TD0 X 135 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 149
... The RFDL block handles the TR input in the same manner as clearing and setting the EN bit, therefore, the RFDL state machine will begin searching for flags and an interrupt will be generated when the first flag is detected. ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused 136 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 150
... Function Default Unused X Unused X Unused X Unused X Unused X INTC1 0 INTC0 0 INT 0 INTC0 Description 0 Disable interrupts (All sources) 1 Enable interrupt when FIFO receives data 0 Enable interrupt when FIFO has 2 bytes of data 1 Enable interrupt when FIFO has 3 bytes of data 137 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 151
... STANDARD PRODUCT PMC-951013 a FIFO overrun is cleared by a RFDL Status register read, by disabling the block setting TR high. The contents of this register should only be changed when the RFDL block is disabled to prevent any erroneous interrupt generation. ISSUE 6 138 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 152
... EOM: The End of Message bit (EOM) follows the RDLEOM[x] output set when: ISSUE 6 Function Default FE 1 OVR 0 FLG 0 EOM 0 CRC 0 NVB2 1 NVB1 1 NVB0 1 139 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 153
... If the Receive Data register is read while there is no valid data, then a FIFO underrun condition occurs. The underrun condition is reflected in the Status register by forcing all bits to logic zero on the first Status register read immediately following the Received Data register read which caused the underrun condition. ISSUE 6 140 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 154
... FIFO underrun, then the pointer is inhibited from incrementing. The underrun condition will be signaled in the next RFDL Status register read by returning all zeros. ISSUE 6 Function Default RD7 X RD6 X RD5 X RD4 X RD3 X RD2 X RD1 X RD0 X 141 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 155
... The TCLKI active (TCLKIA) bit monitors for low to high transitions on the TCLKI[x] input. TCLKIA is set high on a rising edge of TCLKI[x], and is set low when this register is read. ISSUE 6 Function Default INT4 0 INT3 0 INT2 0 INT1 0 BTCLKA 0 TCLKIA 0 BRCLKA 0 RCLKIA 0 142 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 156
... BRCLK input. BRCLKA is set high on a rising edge of BRCLK, and is set low when this register is read. RCLKIA: The RCLKI active (RCLKA) bit monitors for low to high transitions on the RCLKI[x] input. RCLKIA is set high on a rising edge of RCLKI[x], and is set low when this register is read. ISSUE 6 143 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 157
... The BTPCMI bit indicates if a parity error has been detected on the BTPCM[x] input. This bit is cleared when this register is read. Odd or even parity is selected by the BTPTYP bit. ISSUE 6 Function Default BTPTYP 0 BTPRTYE 0 BTPCMPI X BTSIGPI X Unused X Unused X BRPTYP 0 BRPRTYE 0 144 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 158
... BRPRTYE: The BRPRTYE bit enables receive parity insertion. When set a logic one, parity is inserted into the PRTY-bit position of the BRPCM[x] and BRSIG[x] streams. When set to logic zero, the data in the PRTY-bit position passes through unaltered. ISSUE 6 145 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 159
... ELST Idle Code register to placed in all time slots on BRPCM. BRSIG presents the frozen signaling. If MTKC is a logic 1, each BRPCM and BRSIG time slot may have an unique idle code. ISSUE 6 Function Default ACCEL 0 Unused X Unused X Unused X MTKC 0 Reserved 0 IND 0 PCCE 0 146 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 160
... When the PCCE bit is set to logic 0, the per-timeslot functions are disabled. Upon reset of the EQUAD, the ACCEL, MTKC, IND, and PCCE bits are all set to logic 0 disabling µP indirect access and per-timeslot functions. ISSUE 6 147 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 161
... During normal operation, the Status Register should be polled until the BUSY bit goes low before another µP access request is initiated. A µP access request is typically completed within 480 ns. ISSUE 6 Function Default BUSY 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X 148 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 162
... The R/WB bit selects the operation to be performed on the addressed register: when R/WB is set to a logic 1, a read from the internal SIGX register is requested, when R/WB is set to a logic 0, a write to the internal SIGX register is requested. ISSUE 6 Function Default R/ 149 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 163
... Signaling Data Register for Time Slot 15 31H Signaling Data Register for Time Slot 17 • • • • • • 3EH Signaling Data Register for Time Slot 30 ISSUE 6 Function Default D[7] X D[6] X D[5] X D[4] X D[3] X D[2] X D[1] X D[0] X 150 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 164
... Slot 0 61H Configuration and Signaling Trunk Conditioning data for Time Slot 1 • • • • • • 7EH Configuration and Signaling Trunk Conditioning for Time Slot 30 7FH Configuration and Signaling Trunk Conditioning for Time Slot 31 ISSUE 6 151 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 165
... Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R ISSUE 6 Function Default A TS ‘n+16’ ‘n+16’ ‘n+16’ ‘n+16’ ‘n’ ‘n’ ‘n’ ‘n’ X 152 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 166
... Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R ISSUE 6 Function Default A TS ‘n-16’ ‘n-16’ ‘n-16’ ‘n-16’ ‘n’ ‘n’ ‘n’ ‘n’ X 153 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 167
... When trunk conditioning is enabled, PCM trunk conditioning bits TCD[7:0] replace timeslot bits 1 through 8 respectively for the referenced timeslot. TS0 and TS16 can be replaced with trunk conditioning data. ISSUE 6 Function Default TCD[7] X TCD[6] X TCD[5] X TCD[4] X TCD[3] X TCD[2] X TCD[1] X TCD[0] X 154 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 168
... Registers (one of 40H to 5FH) is output onto the data stream, BRPCM. In addition, the per-timeslot signaling trunk conditioning bits A’,B’,C’ and D’ are output onto the signaling data stream, BRSIG. ISSUE 6 Function Default RINV[1] X RINV[0] X RTKCE X RDEBE X A’ X B’ X C’ X D’ X 155 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 169
... To enable the RINV[1:0], RTKCE and RDEBE bits, the PCCE bit in the SIGX Configuration Register must be set to logic 1. When these bits are enabled, bits RINV[1:0] and RDEBE are ORed with their primary input equivalents to generate the applied configuration signals. ISSUE 6 156 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 170
... Reserved. 1 CAS enabled. TS16 data is taken from either BTSIG[x] stream or from the TPSC Data Control byte as selected on a per-timeslot basis via the SIGSRC bit. The format of the BTSIG[x] input data stream is shown in the "Functional Timing" section. 157 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 171
... BTPCM[x] stream. When INDIS and FDIS are logic 0, the bit values used for the International and National bits are dependent upon ISSUE 6 158 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 172
... CRC multiframe alignment signal is used for the International bit in the NFAS frames, with the Si[1:0] bits in the International/National Control Register used for the spare bits. Bit positions Sn[4:0] in the register are used for the National bits in NFAS frames. 159 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 173
... STANDARD PRODUCT PMC-951013 When the EQUAD is reset, the contents of this register are set to logic 0, except SIGEN and DLEN which are set to logic 1. ISSUE 6 160 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 174
... The SPATINV bit is a diagnostic control bit. When set to logic 1, SPATINV forces the signaling multiframe alignment signal written into bits 1-4 of TS16 of frame 0 of the signaling multiframe to be inverted (i.e., the correct signaling ISSUE 6 Function Default MTRK 0 FPATINV 0 SPLRINV 0 SPATINV 0 REMAIS 0 MFAIS 0 TS16AIS 0 AIS 0 161 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 175
... AIS: The AIS bit controls the transmission of the Alarm Indication Signal (unframed all-ones). A logic 1 in the AIS bit position forces the output streams to logic 1. When the EQUAD is reset, the contents of this register are set to logic 0. ISSUE 6 162 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 176
... Si[0] and Si[1] bits in the CRC multiframe. The Si[1], Si[0], and Sn[4:0] bits should be programmed to a logic 1 when not being used to carry information. When the EQUAD is reset, the contents of the register are set to logic 1. ISSUE 6 Function Default Si[1] 1 Si[0] 1 Unused X Sn[4] 1 Sn[3] 1 Sn[2] 1 Sn[1] 1 Sn[0] 1 163 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 177
... XDIS. The X[1], X[3], and X[4] bits should be programmed to a logic 1 when not being used to carry information. When the EQUAD is reset, the contents of the register are set to logic 1. ISSUE 6 Function Default Unused X Unused X Unused X Unused X X[1] 1 Unused X X[3] 1 X[4] 1 164 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 178
... A logic 0 indicates that no overrun has occurred. The OVR bit is cleared by reading this register. ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X INTE 0 XFER 0 OVR 0 165 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 179
... PMON registers should not be polled until 1.71µsec have elapsed from the "latch performance data" register write. When the EQUAD is reset, the contents of the PMON count registers are unknown until the first latching of performance data is performed. ISSUE 6 166 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 180
... This register indicates the number of framing bit error events that occurred during the previous accumulation interval. The FER counts are suppressed when the FRMR has lost frame alignment (OOF in the FRMR Framing Status register is set). ISSUE 6 Function Default Unused X FER[6] X FER[5] X FER[4] X FER[3] X FER[2] X FER[1] X FER[0] X 167 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 181
... Register 04AH, 0CAH, 14AH, 1CAH: Far End Block Error Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R ISSUE 6 Function Default FEBE[7] X FEBE[6] X FEBE[5] X FEBE[4] X FEBE[3] X FEBE[2] X FEBE[1] X FEBE[0] X 168 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 182
... These registers indicate the number of far end block error events that occurred during the previous accumulation interval. The FEBE counts are suppressed when the FRMR has lost frame alignment (OOF in the FRMR Framing Status register is set). ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X FEBE[9] X FEBE[8] X 169 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 183
... Register 04CH, 0CCH, 14CH, 1CCH: CRC Error Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R ISSUE 6 Function Default CRCE[7] X CRCE[6] X CRCE[5] X CRCE[4] X CRCE[3] X CRCE[2] X CRCE[1] X CRCE[0] X 170 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 184
... These registers indicate the number of CRC error events that occurred during the previous accumulation interval. CRC error events are suppressed when the FRMR is out of CRC-4 multiframe alignment (OOCMF bit in the FRMR Framing Status register is set). ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X CRCE[9] X CRCE[8] X 171 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 185
... Register 04EH, 0CEH, 14EH, 1CEH: Line Code Violation Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R ISSUE 6 Function Default LCV[7] X LCV[6] X LCV[5] X LCV[4] X LCV[3] X LCV[2] X LCV[1] X LCV[0] X 172 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 186
... An LCV event is defined as the occurrence of a Bipolar Violation or Excessive Zeros. The counting of Excessive Zeros can be disabled by the BPV bit of the Receive Interface Configuration register. ISSUE 6 Function Default Unused X Unused X Unused X LCV[12] X LCV[11] X LCV[10] X LCV[9] X LCV[8] X 173 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 187
... The value 02H must be written to addresses 007H, 087H, 107H, and 187H. Reading the following address locations returns the values for the indicated inputs : ISSUE 6 174 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 188
... XCLK BTSIG[2] MENB BTFP[2] RDP[3] XCLK BTSIG[3] MENB BTFP[3] RDP[4] XCLK BTSIG[4] MENB BTFP[4] Bit 5 Bit 4 Bit 3 RFP[1] 175 PM6344 EQUAD QUADRUPLE E1 FRAMER Bit 2 Bit 1 Bit 0 RCLKI[1] TDLSIG[1] BTCLK[1] RDN[2] RCLKI[2] TCLKI[2] TDLSIG[2] BTCLK[2] RDN[3] RCLKI[3] TCLKI[3] TDLSIG[3] BTCLK[3] RDN[4] RCLKI[4] ...
Page 189
... INTB 1 39CH 3A0H 3A3H 3B8H 3C0H 3C4H ISSUE 6 Bit 5 Bit 4 Bit 3 BRFPO[1] RFP[2] BRFPO[2] RFP[3] BRFPO[3] RFP[4] BRFPO[4] 176 PM6344 EQUAD QUADRUPLE E1 FRAMER Bit 2 Bit 1 Bit 0 RDLCLK[1] RDLSIG[1] TDLCLK[1] RCLKO[2] BRPCM[2] BRSIG[2] TCLKO[2] TDN[2] TDP[2] INTB 1 RDLCLK[2] RDLSIG[2] TDLCLK[2] RCLKO[3] BRPCM[3] ...
Page 190
... STANDARD PRODUCT PMC-951013 Notes: 1. Writing a logic 1 to any of the block interrupt signals asserts the INTB output low. ISSUE 6 177 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 191
... ISSUE Bit 3 Bit 4 Bit 5 Timeslot 178 PM6344 EQUAD QUADRUPLE E1 FRAMER Bit 6 Bit 7 Bit 8 FAS, Timeslot Undefined ...
Page 192
... Bit 3 Bit 4 Bit 5 CCS data collected over 32 timeslots and inserted into TS16 NFAS, Timeslot 179 PM6344 EQUAD QUADRUPLE E1 FRAMER Bit 6 Bit 7 Bit ...
Page 193
... If ROHM=0, BRXSMFP=1 and BRXCMFP=0, the BRFPO[x] signal pulses high only during the first bit of the frame containing the signaling multiframe alignment signal. ISSUE Undefined Timeslot 0 Timeslot 1 180 PM6344 EQUAD QUADRUPLE E1 FRAMER Undefined Timeslot 16 Timeslot 17 ...
Page 194
... Undefined Undefined Timeslot 0 Timeslot Undefined Timeslot 0 Timeslot 1 181 PM6344 EQUAD QUADRUPLE E1 FRAMER Undefined Timeslot Undefined ...
Page 195
... Undefined Timeslot 0 Timeslot Don't Care Timeslot 0 Timeslot 1 182 PM6344 EQUAD QUADRUPLE E1 FRAMER Undefined Undefined Timeslot 31 Timeslot ...
Page 196
... Don't Care Timeslot 0 Timeslot 1 Don't Care Timeslot 0 Timeslot 1 183 PM6344 EQUAD QUADRUPLE E1 FRAMER Don't Care Timeslot 16 Timeslot Don't Care ...
Page 197
... STANDARD PRODUCT PMC-951013 Figure 20 - Multiplexed Receive Backplane Interface ISSUE 6 184 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 198
... PCM data stream in each frame is replaced by the parity value calculated over the previous frame (not counting the parity bit of the previous frame). The parity bit of each SIG stream follows the parity bit of the PCM data stream. ISSUE 6 185 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 199
... STANDARD PRODUCT PMC-951013 Figure 21 - Multiplexed Transmit Backplane Interface ISSUE 6 186 PM6344 EQUAD QUADRUPLE E1 FRAMER ...
Page 200
... In the case where MENB=0 and BTXMFP=1, the input MTFP marks the start of the signaling multiframe and the start of the CRC multiframe as described in the description of the Transmit Backplane Options register. The waveforms for this case are shown in Fig. 21. ISSUE 6 187 PM6344 EQUAD QUADRUPLE E1 FRAMER ...