PM5313-BI PMC-Sierra Inc, PM5313-BI Datasheet

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PM5313-BI

Manufacturer Part Number
PM5313-BI
Description
Sonet/SDH payload extractor/aligner for 622 Mbit/s
Manufacturer
PMC-Sierra Inc
Datasheet

Specifications of PM5313-BI

Case
BGA
PMC-Sierra, Inc.
PM5313 SPECTRA-622
PRODUCTION
DATASHEET
PMC-1981162
ISSUE 6
SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S
PM5313
SPECTRA-622
SONET/SDH PAYLOAD
EXTRACTOR/ALIGNER
FOR 622 MBIT/S
DATA SHEET
PROPRIETARY AND CONFIDENTIAL
PRODUCTION
ISSUE 6: SEPTEMBER 2000
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

PM5313-BI Summary of contents

Page 1

... PMC-1981162 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S PROPRIETARY AND CONFIDENTIAL ISSUE 6: SEPTEMBER 2000 PMC-Sierra, Inc. PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S PM5313 SPECTRA-622 DATA SHEET PRODUCTION 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM5313 SPECTRA-622 ...

Page 2

... Add WANS programming section Update the RAD and TFPI timing diagrams. Update rev of CRU, GPGM and TTOC. Update the methodology Tools table. Added STM1-CONCAT register bits in RPPS and TPPS configuration. Extend the timing for output pins RSUC, RSOW, ROH and TDO. i PM5313 SPECTRA-622 ...

Page 3

... Control Port Fixed polarity for bit 7, register 0102 Added TPIP is held in reset in DS3 mode only Revised TPAIS and DPAIS frame slots to correctly correspond to slice order Clarified precedence of TOH Overhead port over TSOW, TSUC, and TLOW Removed some DLL registers ii PM5313 SPECTRA-622 ...

Page 4

... Added Register 0016 Added SCPII bit in register 000B Uncovered EXT bit in register 1151 Added pin number Added boundary scan chain information Removed DS-3 framers Block diagram updated TTOC and RTOC registers added Swapped RASE and SSTB register blocks Document created iii PM5313 SPECTRA-622 ...

Page 5

... SERIAL LINE SIDE INTERFACE SIGNALS....................... 23 10.2 PARALLEL LINE SIDE INTERFACE SIGNALS.................. 26 10.3 RECEIVE AND TRANSMIT CLOCKS ................................ 31 10.4 SECTION/LINE STATUS AND ALARMS SIGNALS ........... 35 10.5 RECEIVE TRANSPORT OVERHEAD EXTRACTION SIGNALS............................................................................ 42 10.6 TRANSMIT TRANSPORT OVERHEAD INSERTION SIGNALS............................................................................ 49 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S iv PM5313 SPECTRA-622 ...

Page 6

... RECEIVE SECTION TRACE BUFFER (SSTB).................110 11.4 RECEIVE LINE OVERHEAD PROCESSOR (RLOP)........111 11.5 RECEIVE TRANSPORT OVERHEAD CONTROLLER (RTOC)..............................................................................113 11.6 RING CONTROL PORT ....................................................113 11.7 RECEIVE PATH PROCESSING SLICE (RPPS) ...............114 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S v PM5313 SPECTRA-622 ...

Page 7

... TRANSMIT SECTION OVERHEAD PROCESSOR (TSOP) ............................................................................. 145 11.12 TRANSMIT SECTION TRACE BUFFER (SSTB) ............. 145 11.13 TRANSMIT LINE INTERFACE ......................................... 146 11.13.1...................................................CLOCK SYNTHESIS 11.13.2........................PARALLEL TO SERIAL CONVERTER 11.14 WAN SYNCHRONIZATION CONTROLLER (WANS) ...... 147 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S vi PM5313 SPECTRA-622 146 146 ...

Page 8

... PATH PROCESSING SLICE CONFIGURATION OPTIONS ......................................................................... 495 14.4.1 BASIC CONFIGURATION ..................................... 495 14.4.2 ADDITIONAL CONFIGURATION FOR TRANSMIT CONCATENATED STREAM SUPPORT ............................................................. 498 14.4.3 CONCATENATED AND NON- CONCATENATED STREAMS DETECTION.......... 498 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S vii PM5313 SPECTRA-622 151 153 ...

Page 9

... PHASE SAMPLE AVERAGING ............................. 507 14.9.4 IMPLEMENTATION EXAMPLE ............................. 508 14.10 LOOPBACK OPERATION................................................ 508 14.11 JTAG SUPPORT .............................................................. 509 14.11.1.................................................... TAP CONTROLLER 14.11.2.......................................................................STATES 14.11.3......................................................... INSTRUCTIONS 14.12 BOARD DESIGN RECOMMENDATIONS ........................ 515 14.13 POWER SUPPLIES ......................................................... 516 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S viii PM5313 SPECTRA-622 511 513 514 ...

Page 10

... TRANSMIT OVERHEAD (TOH) FUNCTIONAL TIMING .................................................................. 537 15.4 PATH OVERHEAD EXTRACTION AND INSERTION ...... 540 15.5 MATE SPECTRA-622 INTERFACES ............................... 544 15.6 TELECOM BUS SYSTEM SIDE....................................... 549 15.6.1 DROP BUS ............................................................ 549 15.6.2 ADD BUS............................................................... 556 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S ix PM5313 SPECTRA-622 ...

Page 11

... DROP BUS TIMING ......................................................... 592 19.6 PATH AIS INPUT TIMING................................................. 597 19.7 ADD BUS TIMING ............................................................ 599 19.8 TRANSMIT TIMING.......................................................... 602 19.9 JTAG TIMING ................................................................... 608 20 ORDERING AND THERMAL INFORMATION............................. 610 21 MECHANICAL INFORMATION ................................................... 612 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S x PM5313 SPECTRA-622 ...

Page 12

... INTERRUPT STATUS ................................................................. 191 REGISTER 000EH: SPECTRA-622 AUXILIARY SIGNAL INTERRUPT ENABLE ................................................................ 193 REGISTER 000FH: SPECTRA-622 AUXILIARY SIGNAL STATUS/INTERRUPT STATUS .................................................. 194 REGISTER 0010H: SPECTRA-622 PATH PROCESSING SLICE INTERRUPT STATUS #1 ............................................................ 195 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xi PM5313 SPECTRA-622 ...

Page 13

... REGISTER 0045H: RLOP REI ERROR COUNT #1.............................. 220 REGISTER 0050H: SSTB SECTION TRACE CONTROL ..................... 222 REGISTER 0051H: SSTB SECTION TRACE STATUS ......................... 225 REGISTER 0052H: SSTB SECTION TRACE INDIRECT ADDRESS.... 227 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xii PM5313 SPECTRA-622 ...

Page 14

... REGISTER 0089H: WANS REFERENCE PERIOD LSB....................... 252 REGISTER 008BH: WANS PHASE COUNTER PERIOD LSB.............. 253 REGISTER 008DH: WANS PHASE AVERAGE PERIOD ...................... 254 REGISTER 0090H: RTOC OVERHEAD CONTROL ............................. 255 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xiii PM5313 SPECTRA-622 ...

Page 15

... REGISTER 00C3H: TTOC TRANSMIT S1 ............................................ 278 REGISTER 0100H: SPECTRA-622 RPPS CONFIGURATION ............. 279 REGISTER 0102H: SPECTRA-622 RPPS PATH AND DS3 CONFIGURATION ...................................................................... 281 REGISTER 0110H: SPECTRA-622 RPPS PATH/DS3 AIS CONTROL #1.............................................................................. 283 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xiv PM5313 SPECTRA-622 ...

Page 16

... REGISTER 0134H: SPECTRA-622 RPPS AUXILIARY PATH STATUS ...................................................................................... 310 REGISTER 0150H: RPOP STATUS AND CONTROL (EXTD=0)............311 REGISTER 0150H: RPOP STATUS AND CONTROL (EXTD=1)........... 313 REGISTER 0151H: RPOP ALARM INTERRUPT STATUS (EXTD=0) .................................................................................... 314 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xv PM5313 SPECTRA-622 ...

Page 17

... REGISTER 0177H: PMON TRANSMIT NEGATIVE POINTER JUSTIFICATION COUNT ............................................................ 337 REGISTER 0180H: RTAL CONTROL.................................................... 338 REGISTER 0181H: RTAL INTERRUPT STATUS AND CONTROL ....... 340 REGISTER 0182H: RTAL ALARM AND DIAGNOSTIC CONTROL ....... 343 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xvi PM5313 SPECTRA-622 ...

Page 18

... REGISTER 01DBH: DPGM MONITOR STATUS................................... 370 REGISTER 01DCH: DPGM MONITOR ERROR COUNT #1................. 372 REGISTER 0D01H: SPECTRA-622 DROP BUS STM-1 #1 AU3 #1 SELECT ...................................................................................... 373 REGISTER 0D02H: SPECTRA-622 DROP BUS STM-1 #2 AU3 #1 SELECT ...................................................................................... 374 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xvii PM5313 SPECTRA-622 ...

Page 19

... REGISTER 1034H: SPECTRA-622 ADD BUS PARITY INTERRUPT STATUS ................................................................. 391 REGISTER 1036H: SPECTRA-622 SYSTEM SIDE CLOCK ACTIVITY MONITOR .................................................................. 392 REGISTER 1037H: SPECTRA-622 ADD BUS SIGNAL ACTIVITY MONITOR ................................................................................... 393 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xviii PM5313 SPECTRA-622 ...

Page 20

... REGISTER 106CH: SPECTRA-622 ADD BUS STM-1 #4 AU3 #3 SELECT ...................................................................................... 405 REGISTER 1100H: SPECTRA-622 TPPS CONFIGURATION .............. 406 REGISTER 1102H: SPECTRA-622 TPPS PATH AND DS3 CONFIGURATION ...................................................................... 409 REGISTER 1106H: SPECTRA-622 TPPS PATH TRANSMIT CONTROL ...................................................................................411 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xix PM5313 SPECTRA-622 ...

Page 21

... REGISTER 1181H: TTAL INTERRUPT STATUS AND CONTROL ........ 437 REGISTER 1182H: TTAL ALARM AND DIAGNOSTIC CONTROL........ 439 REGISTER 1190H: TPIP STATUS AND CONTROL (EXTD=0) ............. 441 REGISTER 1190H: TPIP STATUS AND CONTROL (EXTD=1) ............. 443 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xx PM5313 SPECTRA-622 ...

Page 22

... REGISTER 11DCH: APGM MONITOR ERROR COUNT #1 ................. 473 REGISTER ADDRESS 2000H: MASTER TEST.................................... 475 REGISTER ADDRESS 2001H: RX ANALOG TEST REGISTER ........... 477 REGISTER ADDRESS 2002H: TX ANALOG TEST REGISTER ........... 478 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxi PM5313 SPECTRA-622 ...

Page 23

... PRODUCTION DATASHEET PMC-1981162 REGISTER ADDRESS 2003H: MASTER TEST SLICE SELECT.......... 479 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxii PM5313 SPECTRA-622 ...

Page 24

... TABLE 16- MASTER TEST SLICE SELECT, SLICE_SEL[3:0] CODE-POINTS.............................................................. 479 TABLE 17-INSTRUCTION REGISTER (LENGTH - 3 BITS).................. 480 TABLE 18-IDENTIFICATION REGISTER.............................................. 480 TABLE 19-BOUNDARY SCAN REGISTER LENGTH - 277 BITS.......... 480 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxiii PM5313 SPECTRA-622 ...

Page 25

... TABLE 36- RECEIVE RING CONTROL PORT OUTPUT TIMING......... 592 TABLE 38- TELECOM DROP BUS INPUT TIMING............................... 592 TABLE 39- TELECOM DROP BUS OUTPUT TIMING AT 77.76 MHZ DCK ...................................................................... 594 TABLE 40- TELECOM DROP BUS OUTPUT TIMING AT 19.44 MHZ DCK ...................................................................... 594 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxiv PM5313 SPECTRA-622 ...

Page 26

... TABLE 52- JTAG PORT INTERFACE.................................................... 608 TABLE 53- ORDERING INFORMATION ............................................... 610 TABLE 54- THERMAL INFORMATION – THETA JC ............................. 610 TABLE 55- MAXIMUM JUNCTION TEMPERATURE ............................ 610 TABLE 56- THERMAL INFORMATION – THETA JA VS. AIRFLOW ...... 610 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxv PM5313 SPECTRA-622 ...

Page 27

... MBIT/S.................................................................... 108 FIGURE 12 - POINTER INTERPRETATION STATE DIAGRAM ........117 FIGURE 13 - POINTER GENERATION STATE DIAGRAM .............. 127 FIGURE 14 -PHASE COMPARATOR BLOCK DIAGRAM ................ 147 FIGURE 15 -PHASE AVERAGER BLOCK DIAGRAM ...................... 149 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxvi PM5313 SPECTRA-622 ...

Page 28

... SECTION/LINE AND LINE DCC TIMING (RX_GAPSEL=0)........................................................... 526 FIGURE 38 -RX LINE DCC TIMING (RX_GAPSEL=0)..................... 526 FIGURE 39 -RX SECTION DCC TIMING (RX_GAPSEL=0)............. 527 FIGURE 40 -RX SECTION/LINE AND LINE DCC TIMING (RX_GAPSEL=1)........................................................... 527 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxvii PM5313 SPECTRA-622 ...

Page 29

... TTOHFP (TX_GAPSEL=0) ............................................ 536 FIGURE 53 -TRANSMIT ORDER WIRE AND USER CHANNEL TIMING (TX_GAPSEL=1).............................................. 537 FIGURE 54 -TRANSMIT OVERHEAD FUNCTIONAL TIMING (TX_GAPSEL=0) ........................................................... 537 FIGURE 55 -TRANSMIT OVERHEAD FUNCTIONAL TIMING (TX_GAPSEL=1) ........................................................... 538 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxviii PM5313 SPECTRA-622 ...

Page 30

... STS-3C (STM-1/AU4) 19.44 MHZ BYTE ADD BUS (AFP) TIMING................................................................ 559 FIGURE 72 - STS-12C (STM-4-4C) 19.44 MHZ BYTE ADD BUS TIMING .......................................................................... 560 FIGURE 73 -STS-12C (STM-4-4C) 19.44 MHZ BYTE ADD BUS (AFP) TIMING................................................................ 561 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxix PM5313 SPECTRA-622 ...

Page 31

... TIMING DIAGRAM............................................. 582 FIGURE 87 -TRANSMIT PARALLEL LINE INTERFACE TIMING DIAGRAM...................................................................... 584 FIGURE 88 -RECEIVE PARALLEL LINE INTERFACE TIMING DIAGRAM...................................................................... 585 FIGURE 89 - RECEIVE SERIAL LINE SIDE TIMING ....................... 586 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxx PM5313 SPECTRA-622 ...

Page 32

... FIGURE 107 - JTAG PORT INTERFACE TIMING .............................. 608 FIGURE 108 - THETA JA VS. AIRFLOW PLOT .................................. 610 FIGURE 109 - MECHANICAL DRAWING 520 PIN SUPER BALL GRID ARRAY (SBGA).................................................... 612 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S xxxi PM5313 SPECTRA-622 ...

Page 33

... STS-12c (STM-4-4c) payload to system timing reference, accommodating plesiochronous timing offsets between the references through pointer processing. Maps twelve DS3 bit streams into an STS-12 (STM-4/AU3) frame. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 1 PM5313 SPECTRA-622 jitter ...

Page 34

... Extracts and serializes the order wire channels (E1, E2), the data communication channels (D1-D3, D4-D12) and the section user channel (F1) from the received stream, and inserts the corresponding signals into the transmit stream. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 2 PM5313 SPECTRA-622 ...

Page 35

... Optionally inserts path alarm indication signal (PAIS) and path remote defect indication (RDI) in the transmit stream. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 3 PM5313 SPECTRA-622 ...

Page 36

... Supports Telecombus interfaces by indicating/accepting the location of the STS identification byte (C1), optionally the path trace byte(s) (J1), optionally the first tributary overhead byte(s) (V1), and all synchronous payload envelope bytes in the byte serial stream. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 4 PM5313 SPECTRA-622 ...

Page 37

... Provides TSI function to interchange or groom twelve STS-1 (STM-0/AU3) paths or four STS-3/3c (STM-1/AU3/AU4) paths at the Telecom ADD and DROP buses. For STS-3 (STM-1/AU3) paths, grooming can be performed at the STS-1 (STM-0/AU3) level. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 5 PM5313 SPECTRA-622 ...

Page 38

... PRODUCTION DATASHEET PMC-1981162 2 APPLICATIONS SONET/SDH Add Drop Multiplexers SONET/SDH Terminal Multiplexers SONET/SDH Line Multiplexers SONET/SDH Cross Connects SONET/SDH Test Equipment Switches and Hubs Routers PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 6 PM5313 SPECTRA-622 ...

Page 39

... Hierarchy (SDH) Equipment Functional Blocks”, 28 October, 1992. ITU Recommendation O.151, “Error Performance measuring Equipment Operating at the Primary Rate and Above”, October, 1992. ITU Recommendation I.432, “ISDN User Network Interfaces”, March 93. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 7 PM5313 SPECTRA-622 ...

Page 40

... Transmit Path Overhead Processor TSOP Transmit Section Overhead Processor TTAL Transmit Telecom Aligner WANS Wide Area Network Synchronization Controller RPPS Receive Path Processing Slice TPPS Transmit Path Processing Slice PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 8 PM5313 SPECTRA-622 ...

Page 41

... TUPP-PLUS DD[15:8], DDP[2] ID[7:0], IDP DC1J1V1[2] IC1J1 DPL[2] IPL DCK SCLK PM5362 TUPP-PLUS DD[7:0], DDP[1] ID[7:0], IDP DC1J1V1[1] IC1J1 DPL[1] IPL DCK SCLK 9 PM5313 SPECTRA-622 OD[7:0], ODP OTV5 OTPL TPOH Four 19.44 MHz 8-bit OD[7:0], ODP IEEE P1396 OTV5 OTPL Telecombus TPOH Interfaces OD[7:0], ODP OTV5 OTPL TPOH OD[7:0], ODP ...

Page 42

... Mbit/s Optical Optical Transceiver Interface PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S PM5313 SPECTRA-622 AD[31:0], ADP[4:1] AC1J1V1[4:1] APL[4:1] RXD+/- SD TXD+/- DD[31:0], DDP[4:1] DC1J1V1[4:1] DPL[4:1] 10 PM5313 SPECTRA-622 ACK 77.76 MHz 8-bit High Speed Telecombus Interface DCK DFP Drop Add ...

Page 43

... Serial to Parallel and Parallel to Serial Conversion PIN[7:0] TFPO TOUT[7:0] ROUT[7:0] ROFP TFPO TOUT[7:0] ROUT[7:0] ROFP TFPO TOUT[7:0] ROUT[7:0] ROFP 11 PM5313 SPECTRA-622 PM5342 SPECTRA-622 ACK AD[31:0], ADP[4:1] TFPI AC1J1V1[4:1] TD[7:0] APL[4:1] PIN[7:0] DD[31:0], DDP[4:1] FPIN DC1J1V1[4:1] DPL[4:1] DCK, DFP IEEE P1396 Telecombus PM5342 SPECTRA-622 Interfaces ...

Page 44

... Channelised DS-3 Interface for High Speed IP Switches/Routers Channelised OC-12 Card 622 Mbit/s Optical Interface PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S S/UNI- QJET Opt SPECTRA- 622 S/UNI- Opt QJET S/UNI- QJET 12 PM5313 SPECTRA-622 FREEDM-8 FREEDM-8 FREEDM-8 FREEDM-8 FREEDM-8 FREEDM-8 Bus Interface ...

Page 45

... DS3RDAT[12:9] DS3TICLK[8:7] TCLK[4:1] TPOS[4:1] DS3TDAT[8:7] RCLK[4:1] DS3ROCLK[8:7] RPOS[4:1] DS3RDAT[8:7] DD[15:8], DDP[2] ID[7:0], IDP DC1J1V1[2] IC1J1 DPL[2] IPL DCK SCLK 13 PM5313 SPECTRA-622 PM7346 S/UNI-QJET ATM UTOPIA LEVEL 2 BUS (to ATM switch core) PM7366 PM7346 FREEDM-8 S/UNI-QJET TCLK[1:0] TD[1:0] RCLK[1:0] RD[1:0] 19.44 MHz 8-bit PM5362 TUPP-PLUS IEEE P1396 OD[7:0], ODP ...

Page 46

... DROP Side Receive Path Processing Slice (RPPS) #n, n= {1..12 ransport W AN Overhead Synchronization Controller Controller DPA IS (RTOC) RPOHC ANS) and PM5313 SPECTRA-622 ADD Bus Pointer Add Bus Generator/ Interpreter System Monitor (T PIP) Interface (A PGM ) Tx DS-3 System Interface ...

Page 47

... OP) Receive Path Processing Slice (RPPS) #n, n= {1..12} Rx Transport W AN Overhead Synchronization Controller Controller DPA IS (RTOC) RPOHCTRL (W ANS) and TPAIS 15 PM5313 SPECTRA-622 ADD_TSI ADD Bus PRBS Tx Pointer Add Bus G enerator/ Interpr eter System M onitor (TPIP) Interface (APGM ) T x DS-3 System Sid e System Lin opb ack ...

Page 48

... PRODUCTION DATASHEET PMC-1981162 8 DESCRIPTION The PM5313 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER (SPECTRA-622) terminates the transport and path overhead of STS-12 (STM-4/AU3 or STM- 4/AU4) and STS-12c (STM-4-4c) streams at 622.08 Mbit/s. The SPECTRA-622 implements significant functions for a SONET/SDH compliant line interface, as well as DS3 mapping. The SPECTRA-622 receives SONET/SDH frames via a bit serial interface, recovers clock and data, and terminates the SONET/SDH section (regenerator section), line (multiplexer section), and path ...

Page 49

... The SPECTRA-622 is implemented in low power, +3.3 Volt, CMOS technology. It has TTL and pseudo ECL (PECL) compatible inputs and outputs and is packaged in a 520 pin SBGA package. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 17 PM5313 SPECTRA-622 ...

Page 50

... The SPECTRA-622 is available in a 520 pin SBGA package having a body size and a ball pitch of 1.27 mm. Section views of the SPECTRA-622 Pin diagram follow Figure 6 Figure 6 -Full View of SPECTRA-622 diagram A31-T31 AL18-U31 Bottom View PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S A1-T17 UL-AL17 18 PM5313 SPECTRA-622 ...

Page 51

... D[1] A[11] A[6] A[1] GND D[4] D[0] A[10] A[5] A[0] RDB/E K WRB/R D[7] D[3] INTB A[9] A[4] CSB WB D[6] D[2] A[13] A[8] A[3] ALE RSTB VBIAS D[5] VDD A[12] A[7] A[2] MBEB 19 PM5313 SPECTRA-622 TRS GND GND GND VDD TB TDI TCK GND VDD GND TDO VDD VDD GND GND SCPO TMS VDD VDD GND [0] SCPO SCPI SCPI SCPI VDD [1] [1] ...

Page 52

... CLK[3] [6] [2] DS3RO TD TC1J1V PIN TD[3] CLK[2] [7] 1/TFO [7] DS3RO TDP TD[4] TD[0] TPL CLK[1] TD GND TDCK TD[1] TCLK GND [ PM5313 SPECTRA-622 N/C AVD AVS[4] ANA SD SAVS[4] [4] LOG QAVS[1 QAVD AVS[16 [1] AVD PBIAS AVD RRCLK RRCLK- [15] [3] [16] + PBIAS AVS SAVS[5] RXD+ RXD- [1] [15] ...

Page 53

... VDD N/C N/C N/C [0] DMODE DS3TDA DS3RDA N/C N/C [1] T[10] T[11] DS3TDA DS3TDA DS3TICL DS3RDA N/C T[12] T[9] K[10] T[10] DS3TDA DS3TICL DS3TICL DS3RDA N/C T[11] K[12] K[9] T[9] DS3RICL DS3TICL DS3ROC GND N/C K K[11] LK[12 PM5313 SPECTRA-622 DS3RDA DS3RDA VDD N/C N/C T[12] T[5] DS3TDA DS3TDA DS3TICL DS3RDA N/C T[8] T[5] K[7] T[6] DS3ROC DS3TDA DS3RDA N/C N/C LK[11] T[7] T[7] DS3ROC DS3TDA DS3TICL DS3RDA N/C LK[10] T[6] K[6] T[8] DS3ROC DS3TICL DS3TICL GND N/C LK[9] K[8] K[ ...

Page 54

... TTOHEN TLOW TLD PGMRCL TTOHCL N/C TOH TLDCLK K K VDD TFP TAD TTOH TSOW AD[4] N/C DD[2] DD[7] AD[9] Bottom View VDD N/C DD[10] DD[15] N/C VDD 22 PM5313 SPECTRA-622 RTOHCL ROWCL LRDI/RRCP GND RALM K K CLK ROHCL LOS/RRCPF RCLK RSOW RSLD K LAIS/RRCP RFPO RTOH RSUC RSLDCLK DAT RTOHF N/C RLOW ...

Page 55

... When the WAN Synchronization controller is used, REFCLK+/- is supplied using a VCXO. In that application, the transmit direction can be externally looped timed to the line receiver in order to meet wander transfer and holdover requirements. Please refer to the Operation section for a discussion of PECL interfacing issues. 23 PM5313 SPECTRA-622 ...

Page 56

... SPECTRA-622 receive functions. In this case, RXD+/- is sampled on the rising edge of RRCLK+/-. RRCLK+/- is ignored when clock recovery is enabled. Clock recovery bypass is selectable using the RBYP bit in the SPECTRA-622 Line Configuration #1 register. Please refer to the Operation section for a discussion of PECL interfacing issues. 24 PM5313 SPECTRA-622 ...

Page 57

... The signal levels on these outputs correspond to the bit values contained in the SPECTRA-622 Serial Control Port Status and Control register. SCPO[1:0] can be tristate using the SCPO_TS bit in the SPECTRA-622 Serial Control Port Status and Control register. On reset, these outputs will be tristate by default. 25 PM5313 SPECTRA-622 ...

Page 58

... AJ6 bit received). PIN[0] is the least significant bit AH6 (corresponding to bit 8 of each serial word, the last AJ7 bit received). The polarity of the PIN[7:0] pins can be changed by the RXDINV bit in register 0003H. PIN[7:0] is sampled on the rising edge of PICLK. 26 PM5313 SPECTRA-622 ...

Page 59

... SPECTRA-622 is out of frame. OOF is set low while the SPECTRA-622 is in-frame. An out of frame declaration occurs when four consecutive errored framing patterns (A1 and A2 bytes) have been received. OOF can be used to enable an upstream framing pattern detector to search for the framing pattern. OOF is updated on the rising edge of RCLK. 27 PM5313 SPECTRA-622 ...

Page 60

... TD[7] is the most significant bit AH9 (corresponding to bit 1 of each serial word, the first AJ9 bit transmitted). TD[0] is the least significant bit AK9 (corresponding to bit 8 of each serial word, the last AL9 bit transmitted). AH10 AJ10 TD[7:0] is updated on the rising edge of TCLK. 28 PM5313 SPECTRA-622 ...

Page 61

... In parallel mode, TFPO is set high for a single TCLK period during the first SPE (synchronous payload envelope) byte after the J0/Z0 bytes on TD[7:0]. In serial mode, it will rising 15 bits (+/- 3 bits) before the first byte of the SPE on TXD. TFPO is updated on the rising edge of TCLK. 29 PM5313 SPECTRA-622 ...

Page 62

... The INCTPL and INCTC1J1V1 register bits in the SPECTRA-622 Transmit Telecom Bus Configuration register control the inclusion of the TPL and TC1J1V1 signals in parity calculation and the sense (odd/even) of the parity. TDP is updated on the rising edge of TCLK. 30 PM5313 SPECTRA-622 ...

Page 63

... PICLK input. The RCLK output can be disabled and held low by programming the RCLKEN bit in the SPECTRA-622 Clock Control register. RFPO, SALM, LOF, LOS, OOF, LRDI and LAIS are updated on the rising edge of RCLK. RLAIS is sampled on the rising edge of RCLK. 31 PM5313 SPECTRA-622 ...

Page 64

... When clock recovery is enabled, PGMRCLK is a divide by thirty-two version of the recovered clock. When clock recovery is bypassed, PGMRCLK is a divide by thirty-two version of the recovered RRCLK+/- inputs. The PGMRCLK output can be disabled and held low by programming the PGMRCLKEN bit in the SPECTRA-622 Clock Control register. 32 PM5313 SPECTRA-622 ...

Page 65

... The TCLK output can be disabled and held low by programming the TCLKEN bit in the SPECTRA-622 Clock Control register. TFP, TC1J1V1/TFPO, TPL, TDP and TD[7:0] are updated on the rising edge of TCLK. TFPI, TLRDI and TLAIS are sampled on the rising edge of TCLK. 33 PM5313 SPECTRA-622 ...

Page 66

... PGMTCLK is a divide by thirty-two of the synthesized transmit line clock. The PGMTCLKSEL register bit may be found in the SPECTRA-622 Clock Control register The PGMTCLK output can be disabled and held low by programming the PGMTCLKEN bit in the SPECTRA-622 Clock Control register. 34 PM5313 SPECTRA-622 ...

Page 67

... Each alarm indication can be independently enabled using bits in the SPECTRA-622 Section Alarm Output Control #1 and #2 registers. SALM is set low when none of the enabled alarms are active. SALM is updated on the rising edge of RCLK. 35 PM5313 SPECTRA-622 ...

Page 68

... RRCPDAT stream. RRCPFP can be connected directly to the TRCPFP input of a mate SPECTRA-622 in ring-based add-drop multiplexer applications. RRCPFP is updated on the falling edge of RRCPCLK. The enabling and disabling of the ring control port is controlled by the RCPEN bit in the SPECTRA-622 Ring Control register. 36 PM5313 SPECTRA-622 ...

Page 69

... TRCPCLK input of a mate SPECTRA-622 in ring- based add-drop multiplexer applications. RRCPFP and RRCPDAT are updated on the falling edge of RRCPCLK. The enabling and disabling of the ring control port is controlled by the RCPEN bit in the SPECTRA-622 Ring Control register. 37 PM5313 SPECTRA-622 ...

Page 70

... REI bit positions. RRCPDAT can be connected directly to the TRCPDAT input of a mate SPECTRA-622 in ring-based add-drop multiplexer applications. RRCPDAT is updated on the falling edge of RRCPCLK. The enabling and disabling of the ring control port is controlled by the RCPEN bit in the SPECTRA-622 Ring Control register. 38 PM5313 SPECTRA-622 ...

Page 71

... RRCPCLK output of a mate SPECTRA-622 in ring- based add-drop multiplexer applications. TRCPFP and TRCPDAT are sampled on the rising edge of TRCPCLK. The enabling and disabling of the ring control port is controlled by the RCPEN bit in the SPECTRA-622 Ring Control register. 39 PM5313 SPECTRA-622 ...

Page 72

... TRCPDAT stream. TRCPFP can be connected directly to the RRCPFP output of a mate SPECTRA-622 in ring-based add-drop multiplexer applications. TRCPFP is sampled on the rising edge of TRCPCLK. The enabling and disabling of the ring control port is controlled by the RCPEN bit in the SPECTRA-622 Ring Control register. 40 PM5313 SPECTRA-622 ...

Page 73

... REI bit positions.TRCPDAT can be connected directly to the RRCPDAT output of a mate SPECTRA-622 in ring-based add-drop multiplexer applications. TRCPDAT is sampled on the rising edge of TRCPCLK. The enabling and disabling of the ring control port is controlled by the RCPEN bit in the SPECTRA-622 Ring Control register. 41 PM5313 SPECTRA-622 ...

Page 74

... RSLDSEL register bit used to select the section or line DCC. The same register also contains the RX_GAPSEL register bit used to select the smooth or gapped RSLDCLK output clock and the RSLD_TS register bit that can be used to tri-state RSLDCLK and RSLD outputs. 42 PM5313 SPECTRA-622 ...

Page 75

... RTOHFP may be sampled high at the same time as the MSB on RLD. The RTOC Overhead Control register contains the RX_GAPSEL register bit used to select the smooth or gapped RLDCLK output clock and the RLD_TS register bit that can be used to tri-state RLDCLK and RLD outputs. 43 PM5313 SPECTRA-622 ...

Page 76

... RFPO may also be used. In smooth clock mode, RTOHFP may be sampled high at the same time as the MSB on RSOW, RSUC and RLOW. The RTOC Overhead Control register contains the RX_GAPSEL register bit used to select the smooth or gapped ROWCLK output clock. 44 PM5313 SPECTRA-622 ...

Page 77

... RLOW is updated on the falling edge of ROWCLK and should be externally sampled on the rising edge of ROWCLK. The RTOC Overhead Control register contains the RX_GAPSEL register bit used to select the smooth or gapped ROWCLK output clock. 45 PM5313 SPECTRA-622 ...

Page 78

... APS bytes. The same register also contains the RX_GAPSEL register bit used to select the smooth or gapped ROHCLK output clock and the ROH_TS register bit that can be used to tri- state ROHCLK and ROH outputs. 46 PM5313 SPECTRA-622 ...

Page 79

... The receive transport overhead (RTOH) bit serial output signal contains the received transport overhead bytes (A1, A2, J0, Z0, B1, E1, F1, D1-D3, H1-H3, B2, K1, K2, D4-D12, Z1/S1, Z2/M1, and E2) from the incoming stream. RTOH is updated on the falling edge of RTOHCLK and should be sampled externally on the rising edge of RTOHCLK. 47 PM5313 SPECTRA-622 ...

Page 80

... RSLDCLK, RLDCLK, ROWCLK and ROHCLK to locate the MSB of the RSLD, RLD, RSOW, RSUC, RLOW and ROH serial output streams. In this mode, the generation of these clocks are aligned with the generation of RTOHFP. RTOHFP is updated on the falling edge of RTOHCLK. 48 PM5313 SPECTRA-622 ...

Page 81

... The TTOC Overhead Control register contains the TSLD_SEL register bit used to select the section or line DCC. The same register also contains the TX_GAPSEL register bit used to select the smooth or gapped TSLDCLK output clock and the TSLD_TS register bit that can be used to tri-state the TSLDCLK output. 49 PM5313 SPECTRA-622 ...

Page 82

... MSB should be present on TSLD. The TTOC Overhead Control register contains the TX_GAPSEL register bit used to select the smooth or gapped TLDCLK output clock and the TLD_TS register bit that can be used to tri-state the TLDCLK output. 50 PM5313 SPECTRA-622 ...

Page 83

... TFP may also be used. In smooth clock mode, TTOHFP may be used to identify the rising edge when the MSB should be present on TSOW, TSUC and TLOW. The TTOC Overhead Control register contains the TX_GAPSEL register bit used to select the smooth or gapped TOWCLK output clock. 51 PM5313 SPECTRA-622 ...

Page 84

... TLOW is sampled on the rising edge of TOWCLK. The TOH and the TTOH and TTOHEN inputs take precedence over TLOW. The TTOC Overhead Control register contains the TX_GAPSEL register bit used to select the smooth or gapped TOWCLK output clock. 52 PM5313 SPECTRA-622 ...

Page 85

... TOHSEL[1:0] register bits used to select the section orderwire, section user channel, line orderwire or line APS bytes. The same register also contains the TX_GAPSEL register bit used to select the smooth or gapped TOHCLK output clock and the TOH_TS register bit that can be used to tri-state the TOHCLK output. 53 PM5313 SPECTRA-622 ...

Page 86

... The transmit transport overhead (TTOH) bit serial input signal contains the transport overhead bytes (A1, A2, J0, Z0, B1, E1, F1, D1-D3, H1-H3, B2, K1, K2, D4-D12, Z1/S1, Z2/M1, and E2 transmitted and errors masks to be applied on the B1, B2, H1 and H2 transmitted bytes. TTOH is sampled on the rising edge of TTOHCLK. 54 PM5313 SPECTRA-622 ...

Page 87

... TSLDCLK, TLDCLK, TOWCLK and TOHCLK to locate the MSB of the TSLD, TLD, TSOW, TSUC, TRLOW and TOH serial input streams. In this mode, the generation of these clocks are aligned with the generation of TTOHFP. TTOHFP is updated on the falling edge of TTOHCLK. 55 PM5313 SPECTRA-622 ...

Page 88

... When the transmit trace enable (TREN) bit in the TTOC Transport Overhead Byte Control register is a logic 1, the J0 byte contents are sourced from the section trace buffer, regardless of the state of TTOHEN. TTOHEN is sampled on the rising edge of TTOHCLK. 56 PM5313 SPECTRA-622 ...

Page 89

... STS-3/3c (STM- 1/AU3/AU4) streams or the single STS-12c (STM- 4-4c) stream. RPOHCLK is a nominally 12.96 MHz, 50% duty cycle clock. B3E, RALM, RPOH and RPOHFP are updated on the falling edge of the RPOHCLK signal. RAD is updated on the falling edge of RPOHCLK. 57 PM5313 SPECTRA-622 ...

Page 90

... F2, H4, Z3, Z4, and Z5) extracted from the path overhead of the twelve STS-1 (STM-0/AU3) streams or the four STS-3/3c (STM-1/AU3/AU4) streams or the single STS-12c (STM-4-4c) stream. The corresponding RPOHEN signal is set high to identify the valid overhead bytes that are presented. RPOH is updated on the falling edge of RPOHCLK. 58 PM5313 SPECTRA-622 ...

Page 91

... The selection of alarms to be reported is controlled by the SPECTRA-622 RPPS RALM Output Control #1 and #2 registers. RALM is updated on the falling edge of RPOHCLK. The LOS/LOF/LAIS signal indicates the loss of signal (LOS), loss of frame (LOF) or line AIS (LAIS) in the STS-12 (STM-4) SONET/SDH 59 PM5313 SPECTRA-622 ...

Page 92

... ERDI alarm code (bits 5,6,7) of the path status (G1) byte is set to the same alarm codepoint for five or ten consecutive frames. The RDI10 bit in the RPOP Pointer MSB register controls whether five or ten consecutive frames will cause a PRDI indication. 60 PM5313 SPECTRA-622 ...

Page 93

... SONET/SDH stream. In mode 1, PSLM is set high when the accepted PSL differs from the expected PSL written by the microprocessor. In mode 2, PSLM is set high when 5 consecutive mismatches have been declared The receive path trace identifier unstable status (TIU-P) reports the stable/unstable status 61 PM5313 SPECTRA-622 ...

Page 94

... The receive alarm port data signal (RAD) contains the path BIP error count and the path remote alarm indication status of the twelve receive STS-1 (STM-0/AU3) streams or the four STS-3/3c (STM-1/AU3/AU4) streams or the single STS-12c (STM-4-4c) stream. RAD is updated on the falling edge of RPOHCLK. 62 PM5313 SPECTRA-622 ...

Page 95

... The SPECTRA-622 will ignore the byte on TPOH when TPOHEN is set low. The TPOHRDY is set low to indicate SPECTRA-622 is not ready, and the byte must be re-presented at the next opportunity. TPOH is sampled on the rising edge of the TPOHCLK output. 63 PM5313 SPECTRA-622 ...

Page 96

... When the byte at the byte position on TPOH is accepted used as an error mask to modify the corresponding transmit path overhead byte, respectively. The accepted error mask is XOR’ed with the corresponding byte before it is transmitted. TPOHEN is sampled on the rising edge of the TPOHCLK. 64 PM5313 SPECTRA-622 ...

Page 97

... REI bit location of the first STS-1 (STM-0/AU3) stream or the first path REI bit location of the first STS-3c (STM-1/AU4) stream or the first path REI bit location of the single STS-12c (STM-4-4c) stream. TAFP is sampled on the rising edge of TACK. 65 PM5313 SPECTRA-622 ...

Page 98

... DS3 AIS assertion request of the first DROP bus STS-1 (STM-0/AU3) stream. It also marks the path AIS assertion request of the first DROP bus STS-3c (STM-1/AU4) stream or the single DROP bus STS-12c (STM-4-4c) stream. DPAISFP is sampled on the rising edge of DPAISCK. 66 PM5313 SPECTRA-622 ...

Page 99

... DS3 AIS assertion request of the first transmit STS-1 (STM-0/AU3) stream. It also marks the path AIS assertion request of the first transmit STS-3c (STM-1/AU4) stream or the single transmit STS-12c (STM-4-4c) stream. TPAISFP is sampled on the rising edge of TPAISCK. 67 PM5313 SPECTRA-622 ...

Page 100

... TPPS Path and DS3 Configuration register, then a DS3 AIS is inserted instead of a path AIS. Path AIS insertion can also be inserted via register access or in response to ADD bus path alarms. Similarly, DS3 AIS insertion can be performed via register access. TPAIS is sampled on the rising edge of TPAISCK. 68 PM5313 SPECTRA-622 ...

Page 101

... By default the input pins are used to set the DROP bus mode. DMODE[1:0] = 01b: Telecom Mode DMODE[1:0] = 10b: DS3 Mode DMODE[1:0] = 11b: Dual Mode DMODE[1:0] = 00b: Reserved 69 PM5313 SPECTRA-622 ...

Page 102

... STS (AU) pointer and may change relative to DFP. The SPECTRA-622 will flywheel in the absence of a DFP pulse. If the DFP aligment changes, all the slices are resynchronized and the DPGMs need to be manually regen if used. DFP is sampled on the rising edge of DCK. 70 PM5313 SPECTRA-622 ...

Page 103

... DD[7:0] is updated on the rising edge of DCK. These outputs are forced low in DROP DS3 interface mode. The DROP interface mode is set via the DMODE[1:0] input pins or the DMODE[1:0] register bits in the SPECTRA-622 DROP Bus Configuration register. 71 PM5313 SPECTRA-622 ...

Page 104

... DD[15:8] is updated on the rising edge of DCK. These outputs are forced low in DROP DS3 interface mode. The DROP interface mode is set via the DMODE[1:0] input pins or the DMODE[1:0] register bits in the SPECTRA-622 DROP Bus Configuration register. 72 PM5313 SPECTRA-622 ...

Page 105

... DD[23:16] is updated on the rising edge of DCK. These outputs are forced low in DROP DS3 interface mode. The DROP interface mode is set via the DMODE[1:0] input pins or the DMODE[1:0] register bits in the SPECTRA-622 DROP Bus Configuration register. 73 PM5313 SPECTRA-622 ...

Page 106

... DD[31:24] is updated on the rising edge of DCK. These outputs are forced low in DROP DS3 interface mode. The DROP interface mode is set via the DMODE[1:0] input pins or the DMODE[1:0] register bits in the SPECTRA-622 DROP Bus Configuration register. 74 PM5313 SPECTRA-622 ...

Page 107

... DPL[2] is updated on the rising edge of DCK. This output is forced low in DROP DS3 interface mode and STS-12/STM-4 parallel mode. The DROP interface mode is set via the DMODE[1:0] input pins or the DMODE[1:0] register bits in the SPECTRA- 622 DROP Bus Configuration register. 75 PM5313 SPECTRA-622 ...

Page 108

... DPL[4] is updated on the rising edge of DCK. This output is forced low in DROP DS3 interface mode and STS-12/STM-4 parallel mode. The DROP interface mode is set via the DMODE[1:0] input pins or the DMODE[1:0] register bits in the SPECTRA- 622 DROP Bus Configuration register. 76 PM5313 SPECTRA-622 ...

Page 109

... DC1J1V1[2] is updated on the rising edge of DCK. This output is forced low in DROP DS3 interface mode and STS-12/STM-4 parallel mode. The DROP interface mode is set via the DMODE[1:0] input pins or the DMODE[1:0] register bits in the SPECTRA- 622 DROP Bus Configuration register. 77 PM5313 SPECTRA-622 ...

Page 110

... DC1J1V1[4] is updated on the rising edge of DCK. This output is forced low in DROP DS3 interface mode and STS-12/STM-4 parallel mode. The DROP interface mode is set via the DMODE[1:0] input pins or the DMODE[1:0] register bits in the SPECTRA- 622 DROP Bus Configuration register. 78 PM5313 SPECTRA-622 ...

Page 111

... DDP[2] is updated on the rising edge of DCK. This output is forced low in DROP DS3 interface mode and STS-12/STM-4 parallel mode. The DROP interface mode is set via the DMODE[1:0] input pins or the DMODE[1:0] register bits in the SPECTRA-622 DROP Bus Configuration register. 79 PM5313 SPECTRA-622 ...

Page 112

... DDP[4] is updated on the rising edge of DCK. This output is forced low in DROP DS3 interface mode and STS-12/STM-4 parallel mode. The DROP interface mode is set via the DMODE[1:0] input pins or the DMODE[1:0] register bits in the SPECTRA-622 DROP Bus Configuration register. 80 PM5313 SPECTRA-622 ...

Page 113

... H1 and H2 pointer bytes. AD[7] is the most significant bit (corresponding to bit 1 of each serial word, the first bit transmitted). AD[0] is the least significant bit (corresponding to bit 8 of each serial word, the last bit transmitted). AD[7:0] is sampled on the rising edge of ACK. 81 PM5313 SPECTRA-622 ...

Page 114

... H1 and H2 pointer bytes. AD[15] is the most significant bit (corresponding to bit 1 of each serial word, the first bit transmitted). AD[8] is the least significant bit (corresponding to bit 8 of each serial word, the last bit transmitted). AD[15:8] is sampled on the rising edge of ACK. 82 PM5313 SPECTRA-622 nd STS-3/3c ...

Page 115

... H1 and H2 pointer bytes. AD[23] is the most significant bit (corresponding to bit 1 of each serial word, the first bit transmitted). AD[16] is the least significant bit (corresponding to bit 8 of each serial word, the last bit transmitted). AD[23:16] is sampled on the rising edge of ACK. 83 PM5313 SPECTRA-622 rd STS-3/3c ...

Page 116

... H3 to indicate a positive pointer justification event. The APL[1] input must be strapped low when the AFPEN bit in SPECTRA-622 Add Bus Configuration is set high. APL[1] is sampled on the rising edge of ACK. 84 PM5313 SPECTRA-622 th STS-3/3c ...

Page 117

... H3 to indicate a positive pointer justification event. The APL[4] input must be strapped low when the AFPEN bit in SPECTRA-622 Add Bus Configuration is set high. APL[4] is sampled on the rising edge of ACK. 85 PM5313 SPECTRA-622 ...

Page 118

... TPPS slice clocks by AC1J1V1/AFP[1] ADD BUS. This bit should only be used when all 12 TPPS slices are placed in Autonomous mode and the AC1J1V1/AFP[1] (and/or APL) ADD BUS interface can not maintain a constant frame alignment. AC1J1V1[1] is sampled on the rising edge of ACK. 86 PM5313 SPECTRA-622 ...

Page 119

... TPPS slice clocks by AC1J1V1/AFP[1] ADD BUS. This bit should only be used when all 12 TPPS slices are placed in Autonomous mode and the AC1J1V1/AFP[1] (and/or APL) ADD BUS interface can not maintain a constant frame alignment. AFP[1] is sampled on the rising edge of ACK. 87 PM5313 SPECTRA-622 ...

Page 120

... The AD[7:0], AD[15:8], AD[23:16] and AD[31:24] ADD buses must be frame aligned with the C1 pulses of the associated AC1J1V1. All C1 pulses must be aligned. If the AC1J1V1[2] aligment changes, all the slices are resynchronized and the APGMs need to be manually regen if used. AC1J1V1[2] is sampled on the rising edge of ACK. 88 PM5313 SPECTRA-622 ...

Page 121

... ADD buses must be frame aligned with the AFP pulses of the associated AC1J1V1/AFP signal. All AFP pulses must be aligned If the AFP[2] aligment changes, all the slices are resynchronized and the APGMs need to be manually regen if used. AFP[2] is sampled on the rising edge of ACK. 89 PM5313 SPECTRA-622 ...

Page 122

... ADD buses must be frame aligned with the C1 pulses of the associated AC1J1V1 signals. All C1 pulses must be aligned. If the AC1J1V1[3] aligment changes, all the slices are resynchronized and the APGMs need to be manually regen if used. AC1J1V1[3] is sampled on the rising edge of ACK. 90 PM5313 SPECTRA-622 ...

Page 123

... ADD buses must be frame aligned withthe AFP pulses of the associated AC1J1V1/AFP signals. All AFP pulses must be aligned. If the AFP[3] aligment changes, all the slices are resynchronized and the APGMs need to be manually regen if used. AFP[3] is sampled on the rising edge of ACK. 91 PM5313 SPECTRA-622 ...

Page 124

... ADD buses must be frame aligned with the C1 pulses of the associated AC1J1V1 signals. All C1 pulses must be aligned. If the AC1J1V1[4] aligment changes, all the slices are resynchronized and the APGMs need to be manually regen if used. AC1J1V1[4] is sampled on the rising edge of ACK. 92 PM5313 SPECTRA-622 ...

Page 125

... ADD Bus Configuration register control the inclusion of the APL[1] and AC1J1V1[1]/AFP[1] signals in parity calculations and the sense (odd/even) of the parity. ADP[1] is sampled on the rising edge of ACK. ADP[1] should not be tied high or low, this would prevent the detection of activity by the bit ACA1 (reg 1037H) 93 PM5313 SPECTRA-622 ...

Page 126

... ADD Bus Configuration register control the inclusion of the APL[4] and AC1J1V1[4]/AFP[4] signals in parity calculations and the sense (odd/even) of the parity. ADP[4] is sampled on the rising edge of ACK. ADP[4] should not be tied high or low, this would prevent the detection of activity by the bit ACA4 (reg 1037H) 94 PM5313 SPECTRA-622 ...

Page 127

... DS3_SEL52 bit in the corresponding AK22 SPECTRA-622 RPPS Path and DS3 Configuration AJ22 register is set low. DS3ROCLK[n] is generated by AL23 gapping an internal 51.84 MHz clock when the DS3_SEL52 bit is set high, in this mode, the REFCLK signal is required. DS3RDAT[n] is updated on the falling edge of DS3ROCLK[n]. 95 PM5313 SPECTRA-622 ...

Page 128

... DS3TICLK[n] as selected using the AK19 DS3TICLKB bit in the SPECTRA-622 TPPS Path AH19 and DS3 Configuration register. AL20 AK24 AJ24 AL25 AK25 96 PM5313 SPECTRA-622 STM-1 #1, AU3 #1 STM-1 #2, AU3 #1 STM-1 #3, AU3 #1 STM-1 #4, AU3 #1 STM-1 #1, AU3 #2 STM-1 #2, AU3 #2 STM-1 #3, AU3 #2 STM-1 #4, AU3 #2 STM-1 #1, AU3 #3 STM-1 #2, AU3 #3 ...

Page 129

... WRB/RWB signal functions as RWB. When MBEB is high, the SPECTRA-622 is configured for Intel bus mode where the RDB/E signal functions as RDB. The MBEB input has an integral pull up resistor. 97 PM5313 SPECTRA-622 STM-1 #1, AU3 #1 STM-1 #2, AU3 #1 STM-1 #3, AU3 #1 STM-1 #4, AU3 #1 STM-1 #1, AU3 #2 STM-1 #2, AU3 #2 ...

Page 130

... CSB is low and RWB and E are high. The contents of D[7:0] are clocked into the addressed register on the falling E edge while CSB and RWB are low. C12 The bi-directional data bus, D[7:0], is used during D12 SPECTRA-622 read and write accesses. E12 B11 C11 D11 A10 B10 98 PM5313 SPECTRA-622 ...

Page 131

... The active low interrupt (INTB) is set low when a SPECTRA-622 enabled interrupt source is active. The SPECTRA-622 may be enabled to report many alarms or events via interrupts. INTB is tri-stated when the interrupt is acknowledged via the appropriate register access. INTB is an open drain output. 99 PM5313 SPECTRA-622 ...

Page 132

... PREFEN is set high, the PECLREF voltage controls the bias voltage of the PECL outputs. When PREFEN is set low, the PECLREF input is ignored and the bias voltage is set by the internal bandgap generator. This PIN should be tied to analog ground (AVS) during normal operation. 100 PM5313 SPECTRA-622 ...

Page 133

... The active low test reset (TRSTB) signal provides an asynchronous SPECTRA-622 test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmidt triggered input with an integral pull up resistor. In the event that TRSTB is not used, it must be connected to RSTB. 101 PM5313 SPECTRA-622 ...

Page 134

... A1, A31, B2, B30, C3, C4, C16, C28, C29, D3, D4, D16, D28, D29, E5, E11, E16, E21, E27, L5, L27, T3, T4, T5, T27, T28, T29, AA5, AA27, AG5, AG11, AG16, AG21, AG27, AH3, AH4, AH16, AH28, AH29, AJ3, AJ4, AJ16, AJ28, AJ29, AK2, AK30, AL1, AL31 102 PM5313 SPECTRA-622 ...

Page 135

... The analog power (AVD) pins for the analog core. The AVD pins should be connected through passive filtering networks to a well-decoupled +3.3V analog power supply. Please see the Operation section for detailed information. AA2, AB1, AB4, AB5, U5, AC4, AC5, AD3, J2, J4, H2, K3, K5, M3, M4, W5, W3, N2, P3 103 PM5313 SPECTRA-622 ...

Page 136

... The SAVS pins should be connected to the analog ground of the analog power supply. These pins are for shielding purposes only and do not sink any current. Please see the Operation section for detailed information. K2, N3, R3, R1, U1, Y5, AA4, AB3 104 PM5313 SPECTRA-622 ...

Page 137

... Operation section of this document.Do not exceed 100 mA of current on any pin during the power-up or power-down sequence. Refer to the Power Sequencing description in the Operations section. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 105 PM5313 SPECTRA-622 ...

Page 138

... Ensure that all digital power is applied simultaneously, and applied before or simultaneously with the analog power. Refer to the Power Sequencing description in the Operations section. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 106 PM5313 SPECTRA-622 ...

Page 139

... REFCLK+/- reference accuracy under loss of signal conditions. In applications that are required to meet the Bellcore GR-253-CORE SONET Network Element free-run accuracy PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 107 PM5313 SPECTRA-622 ...

Page 140

... PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT 108 PM5313 SPECTRA-622 ...

Page 141

... Serial to Parallel Converter block) that searches for occurrences of the framing pattern (A1, A2) in the bit serial data stream. Once the serial to parallel converter has found byte alignment, the RSOP block monitors PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 109 PM5313 SPECTRA-622 ...

Page 142

... In mode 1 operation, the receive portion of the SONET/SDH Section Trace Buffer (SSTB) captures the received section trace identifier message (J0 byte) into microprocessor readable registers. It contains three pages of trace message PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 110 PM5313 SPECTRA-622 -3 BER, the first algorithm ...

Page 143

... STS-12 (STM-4) stream. The SONET/SDH frame alignment is indicated by the Receive Section Overhead Processor. The RLOP extracts the line data communication channel, line order PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 111 PM5313 SPECTRA-622 ...

Page 144

... Registers are provided that allow accumulated line REI events to be read out at intervals one second duration. Bits 2 through 8 of the Z2/M1 byte are used for the line REI function. For STS-12 (STM-4) PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 112 PM5313 SPECTRA-622 ...

Page 145

... SPECTRA-622. The alarm status and maintenance signal control information that is passed on the ring control ports consists of Filtered APS (K1 and K2) byte values Change of filtered APS byte value status PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 113 PM5313 SPECTRA-622 ...

Page 146

... DS3 signal from an STS-1 (STM-0/AU3) payload. PRBS payload generation and monitoring is also supported on a per STS (AU) basis. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S starting with the last frame of the last three identical bytes 114 PM5313 SPECTRA-622 ...

Page 147

... RDI in the transmit stream. The PRBS generator of an RPPS can be enabled to generate the DROP bus transport frame in addition to the payload. For an STS-3c (STM-1/AU4) stream, PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 115 PM5313 SPECTRA-622 ...

Page 148

... J1 byte STS-1 (STM-0/AU3) or equivalent stream. The algorithm can be modeled by a finite state machine. Within the pointer interpretation algorithm three states are defined as shown below: NORM_state (NORM) AIS_state (AIS) LOP_state (LOP) PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 116 PM5313 SPECTRA-622 ...

Page 149

... NDF + ss + offset value in range 782 AIS_ind 'hFF 'hFF PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT eq_new_point NDF_enable NORM eq_new_point AIS_ind 3 x AIS_ind 8 x inv_point 117 PM5313 SPECTRA-622 3 x eq_new_point NDF_enable AIS ...

Page 150

... Note 7 the requirement for previous NDF_enable, inc_ind or dec_ind be more than 3 frames ago may be optionally disabled. Note 8 new_point is also an inv_point. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 118 PM5313 SPECTRA-622 ...

Page 151

... NORM_state to NORM_state do not represent state changes but imply offset changes. Note new_point takes precedence over 8 x inv_point and resets the inv_point counter. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 119 PM5313 SPECTRA-622 ...

Page 152

... NDF disabled definitions. The third occurrence of equal new_point indications (3 x eq_new_point) is reported as a discontinuous change of pointer alignment event (DISCOPA) instead of a new pointer event and the active offset PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 120 PM5313 SPECTRA-622 ...

Page 153

... Enhanced RDI alarm is detected when the enhanced RDI code in bits 5,6,7 of the path status byte indicates the same error codepoint for five/ten consecutive frames. The Enhanced RDI alarm is removed when the enhanced RDI code in PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 121 PM5313 SPECTRA-622 ...

Page 154

... An interrupt may be optionally generated on entry to and exit from the unstable state. Optionally, path AIS may be inserted PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 122 PM5313 SPECTRA-622 ...

Page 155

... PSL values will cause the counter to increment twice, once PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S Accepted PSL 123 PM5313 SPECTRA-622 PSLM State Match Mismatch Mismatch Mismatch Match Match Mismatch Match Match Mismatch ...

Page 156

... RTAL in the master RPPS. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S Action Note: Unequipped Mismatch XX = anything except 00H or 01H Mismatch YY = anything except 00H or 01H Unequipped (XX not equal YY). Match Match Unequipped Match Match Mismatch 124 PM5313 SPECTRA-622 ...

Page 157

... AIS is optionally inserted in the DROP bus for three frames to alert downstream elements of data corruption. During PAIS, outgoing pointer justifications are not performed. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 125 PM5313 SPECTRA-622 ...

Page 158

... Receive Path Overhead Processor block. The transitions from INC, DEC, and NDF states to the NORM state occur autonomously with the generation of special pointer patterns. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 126 PM5313 SPECTRA-622 ...

Page 159

... ES filling is above the upper threshold + previous inc_ind, dec_ind or NDF_enable more than three frames ago. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S PI_AIS dec_ind ES_lowerT NORM PI_LOP FO_discont PI_AIS PI_NORM PI_AIS 127 PM5313 SPECTRA-622 DEC ES_upperT NDF_enable NDF ...

Page 160

... RPOP block. 11.7.3.3 Bypass The RPPS can be put in bypass mode by setting the RESBYP of the DROP Bus Configuration register (bit 4, register 0D30H). In this mode, all twelve slices are PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 128 PM5313 SPECTRA-622 ...

Page 161

... CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR 129 PM5313 SPECTRA-622 CCRROORS CCRROORS CCRROORS CCRROORS ...

Page 162

... (0) F (0) C ( (0) D 130 PM5313 SPECTRA-622 (0) D ...

Page 163

... DS3ROCLK under the normal, DS3 AIS, faster and slower status. The faster pattern is used to drain the elastic store to avoid overflows. The slower pattern is used to allow the elastic store to fill to avoid underflows. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 131 PM5313 SPECTRA-622 a ...

Page 164

... ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S Run Faster 621 621 622 621 621 622 621 621 622 23 -1 payload test sequence in an 132 PM5313 SPECTRA-622 Run Slower 621 621 621 621 622 622 621 621 622 621 622 621 621 ...

Page 165

... PRBS generator of the PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT test sequence and accumulates pattern errors nd and every twelfth bytes thereafter will be 133 PM5313 SPECTRA-622 st (after the transport overhead ...

Page 166

... In processing an STS-3c (STM-1/AU4), the first STS-1 (STM-0/AU3) equivalent stream will be processed by a TPPS (e.g. TPPS#1) configured as the master. The master TPPS controls two slave TPPS’s (e.g. TPPS#5, TPPS#9) which PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 134 PM5313 SPECTRA-622 ...

Page 167

... Similarly for an STS-12c (STM-4-4c) stream, the PRBS generator in the master TPPS will co-ordinate the distributed PRBS generation by the PRBS generators in the twelve TPPS’s required to process this concatenated stream. Each PRBS PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 135 PM5313 SPECTRA-622 ...

Page 168

... DS3 serial bit rate (DS3TICLK) and the available STS-1 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT payload test sequence in an 136 PM5313 SPECTRA-622 ...

Page 169

... Each row contains one stuff opportunity. The following table illustrates the stuffing implementation where S means stuff bit and I means an information bit (DS3 data). PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 137 PM5313 SPECTRA-622 ...

Page 170

... The TPIP is held in reset in DS3 mode, DS3ADDSEL = ‘1’ and when SLLBEN = '0' (reg 1n00). When held in reset, TPIP registers cannot be accessed. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S Run Faster 138 PM5313 SPECTRA-622 Run Slower ...

Page 171

... The Pointer Generator block schedules a pointer increment event if the FIFO depth is below the lower threshold and a pointer decrement event if the depth is above the upper threshold. FIFO PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 139 PM5313 SPECTRA-622 ...

Page 172

... Transmit Path Overhead Processor block for insertion in the transmit stream. When the microprocessor is updating the transmit page buffer, SPTB may be programmed to transmit null characters to prevent transmission of partial messages. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 140 PM5313 SPECTRA-622 ...

Page 173

... SPECTRA-622. 11.8.6.3 Transmit Alarm Port Received path BIP errors (REI) and remote defect indications (RDI) from Receive Path Overhead Processors (RPOP remote SPECTRA-622 are PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 141 PM5313 SPECTRA-622 ...

Page 174

... MHz transport overhead clock, TTOHCLK, and the transport overhead frame position, TTOHFP. The transport overhead enable signal, TTOHEN, controls the insertion of transport overhead from TTOH. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 142 PM5313 SPECTRA-622 ...

Page 175

... PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 4- D11 National Bytes Unused Bytes 143 PM5313 SPECTRA-622 4- 4- D12 E2 Z2 ...

Page 176

... The bits in the SPECTRA-622 Line RDI Control Register controls the immediate insertion of Line RDI upon detection of various errors in the received SONET/SDH stream. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 144 PM5313 SPECTRA-622 ...

Page 177

... The section trace buffer contains one page of transmit trace identifier message memory. Identifier message data bytes are written by the microprocessor into the message buffer and delivered serially to the Transport PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 145 PM5313 SPECTRA-622 ...

Page 178

... Parallel to Serial Converter The Parallel to Serial Converter (PISO) converts the transmit byte serial stream to a bit serial stream. The transmit bit serial stream appears on the TXD+/- PECL PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 146 PM5313 SPECTRA-622 ...

Page 179

... VCXO clock, VCOCLK) is implemented by sampling fixed interval, the Reference Period the output of the Phase Counter. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S VCO CLK RPHALFLG REACQ UISIT ION RPHALFLG 147 PM5313 SPECTRA-622 PHASE CO UNTER R PHASE S AMPLE REGISTER E N PHSAMP[15:0] ...

Page 180

... AUTOREAC bit of the WANS configuration register. Phase Averager To provide some noise immunity and improve the resolution of the phase detector algorithm of the WANS, the phase samples are averaged over a programmable number of samples. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 148 PM5313 SPECTRA-622 ...

Page 181

... WANS Interrupt and Status register (0081H). The RPHALGN signal is reset at the end of the following valid Phase Averaging period. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S SAMP LEN EO C TIMFLG 149 PM5313 SPECTRA-622 PHSAMP[15:0] SA MPLE ACCUMULA PHASE W ORD RE GIST PHAW ORD[30:0] ...

Page 182

... STS-3 (STM-1) #1 STS-1 (STM-0/AU3) #2 STS-3 (STM-1) #2 STS-1 (STM-0/AU3) #2 STS-3 (STM-1) #3 STS-1 (STM-0/AU3) #2 STS-3 (STM-1) #4 STS-1 (STM-0/AU3) #2 STS-3 (STM-1) #1 STS-1 (STM-0/AU3) #3 STS-3 (STM-1) #2 STS-1 (STM-0/AU3) #3 STS-3 (STM-1) #3 STS-1 (STM-0/AU3) #3 STS-3 (STM-1) #4 STS-1 (STM-0/AU3) #3 150 PM5313 SPECTRA-622 ...

Page 183

... MHz ADD bus (AD[7:0]). For the STM-1 byte Telecom bus modes, the ADD bus STM-1 #1, STM-1 #2, STM-1 #3 and STM-1 #4 streams are sourced from the AD[7:0], AD[15:8], AD[23:16] and AD[31:24] buses, respectively. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 151 PM5313 SPECTRA-622 ...

Page 184

... AC1J1V1 marks ground C1 position only APL marks AC1J1V1 marks C1, J1 and V1 payload bytes positions APL marks AC1J1V1 marks payload bytes C1 position only 152 PM5313 SPECTRA-622 Comments TPIP block is bypassed. TPIP block interprets pointers for J1/V1 TPIP block interprets pointers for J1/V1. Ignores J1/V1 indications on ...

Page 185

... AFP[4:1] Input Pin X AFP marks first SPE byte position only DPL[4:1] DC1J1V1[4:1] DPL marks payload DC1J1V1 marks C1, bytes J1 and V1 positions DPL marks payload DC1J1V1 marks C1 bytes and J1 positions only 153 PM5313 SPECTRA-622 Comments TPIP block interprets pointers for J1/V1. Ignores APL input. ...

Page 186

... SPECTRA-622 Ring Control SPECTRA-622 Line RDI Control SPECTRA-622 Section Alarm Output Control #1 SPECTRA-622 Section Alarm Output Control #2 Reserved SPECTRA-622 Section/Line Block Interrupt Status SPECTRA-622 Auxiliary Section/Line Interrupt Enable SPECTRA-622 Auxiliary Section/Line Interrupt Status SPECTRA-622 Auxiliary Signal Interrupt Enable 154 PM5313 SPECTRA-622 ...

Page 187

... RLOP Line BIP (B2) Error Count #3 RLOP Line REI Error Count #1 RLOP Line REI Error Count #2 RLOP Line REI Error Count #3 Reserved SSTB Section Trace Control SSTB Section Trace Status SSTB Section Trace Indirect Address SSTB Section Trace Indirect Data SSTB Reserved 155 PM5313 SPECTRA-622 ...

Page 188

... RASE SD Saturation Threshold RASE SD Saturation Threshold RASE SD Declaring Threshold RASE SD Declaring Threshold RASE SD Clearing Threshold RASE SD Clearing Threshold RASE Receive K1 RASE Receive K2 RASE Receive Z1/S1 Reserved WANS Configuration WANS Interrupt and Status WANS Phase Word LSB WANS Phase Word 156 PM5313 SPECTRA-622 ...

Page 189

... RTOC AIS Control RTOC Reserved Reserved Reserved Reserved Reserved Reserved DROP Bus DLL Configuration Reserved DROP Bus DLL Reset Register DROP Bus DLL Control Status Reserved Reserved Reserved CSPI Configuration CSPI Status Reserved Reserved TSOP Control TSOP Diagnostic 157 PM5313 SPECTRA-622 ...

Page 190

... SPECTRA-622 RPPS Auxiliary Path Interrupt Status #1 SPECTRA-622 RPPS Auxiliary Path Interrupt Status #2 SPECTRA-622 RPPS Auxiliary Path Status RPOP Status and Control (EXTD=0) RPOP Status and Control (EXTD=1) RPOP Alarm Interrupt Status (EXTD=0) RPOP Alarm Interrupt Status (EXTD=1) RPOP Pointer Interrupt Status 158 PM5313 SPECTRA-622 ...

Page 191

... PMON Transmit Positive Pointer Justification Count PMON Transmit Negative Pointer Justification Count RPPS Reserved RTAL Control RTAL Interrupt Status and Control RTAL Alarm and Diagnostic Control RTAL Reserved RPPS Reserved SPTB Control SPTB Path Trace Identifier Status SPTB Indirect Address 159 PM5313 SPECTRA-622 ...

Page 192

... DPGM Monitor Error Count #2 DPGM Reserved RPPS Reserved DROP Bus STM-1 #1 AU3 #1 Select DROP Bus STM-1 #2 AU3 #1 Select DROP Bus STM-1 #3 AU3 #1 Select DROP Bus STM-1 #4 AU3 #1 Select DROP Bus STM-1 #1 AU3 #2 Select DROP Bus STM-1 #2 AU3 #2 Select 160 PM5313 SPECTRA-622 ...

Page 193

... ADD Bus STM-1 #1 AU3 #2 Select ADD Bus STM-1 #2 AU3 #2 Select ADD Bus STM-1 #3 AU3 #2 Select ADD Bus STM-1 #4 AU3 #2 Select ADD Bus STM-1 #1 AU3 #3 Select ADD Bus STM-1 #2 AU3 #3 Select ADD Bus STM-1 #3 AU3 #3 Select ADD Bus STM-1 #4 AU3 #3 Select 161 PM5313 SPECTRA-622 ...

Page 194

... TPOP Pointer Control TPOP Reserved TPOP Current Pointer LSB TPOP Current Pointer MSB TPOP Payload Pointer LSB TPOP Payload Pointer MSB TPOP Path Trace TPOP Path Signal Label TPOP Path Status TPOP Path User Channel TPOP Path Growth #1 162 PM5313 SPECTRA-622 ...

Page 195

... TPIP Path BIP-8 Count LSB TPIP Path BIP-8 Count MSB TPIP Reserved TPIP Reserved TPIP Tributary Multiframe Status and Control TPIP BIP Control TPIP Reserved TPIP Reserved TPPS Reserved D3MA Control D3MA Interrupt Status D3MA Interrupt Enable D3MA Reserved 163 PM5313 SPECTRA-622 ...

Page 196

... APGM Generator Status APGM Reserved APGM Monitor Control #1 APGM Monitor Control #2 APGM Monitor Concatenate Control APGM Monitor Monitor Status APGM Monitor Error Count #1 APGM Monitor Error Count #2 APGM Reserved Reserved Master Test Master Test Slice Select Reserved for Test 164 PM5313 SPECTRA-622 ...

Page 197

... Slice #5 1,2 Slice #9 1,3 Slice #2 2,1 Slice #6 2,2 Slice #10 2,3 Slice #3 3,1 Slice #7 3,2 Slice #11 3,3 4,1 Slice #4 4,2 Slice #8 4,3 Slice #12 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S Order of T ransm ission Tw elveth Byte 4,3 3,3 2,3 1,3 4,2 Byte Interleaving to generate STS-12 (ST M-4) stream 165 PM5313 SPECTRA-622 First Byte 3,2 2,2 1,2 4,1 3,1 2,1 1,1 STS-12 (STM-4) ...

Page 198

... To ensure that the SPECTRA-622 operates as intended, reserved register bits must only be written with the logic level as specified. Writing to reserved registers should be avoided. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 166 PM5313 SPECTRA-622 ...

Page 199

... This is independent of all other processing blocks. This bit is not self clearing. Therefore, a logic zero must be written to bring the slices out PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S Function Default RESET 0 RESET_PATH 0 TIP X ID[4] 0 ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 167 PM5313 SPECTRA-622 ...

Page 200

... TX bypass mode must be enabled by setting the BYPASS bit in register 1030H. Either of those writes will activate the TX line interface, once done, those bits can be reprogrammed at any value. PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S 168 PM5313 SPECTRA-622 ...

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