TS68230 STMicroelectronics, TS68230 Datasheet
TS68230
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TS68230 Summary of contents
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... LY ADDRESSABLE REGISTERS ARE ADDRESSED FOR MOVEP (Move Peripheral) AND DMAC COMPATIBILITY DESCRIPTION The TS68230 parallel interface/timer (PI/T) provides versatile double buffered parallel interfaces and a system oriented timer for TS68000 systems. The pa- rallel interfaces operate in unidirectional or bidirectio- nal modes, either bits wide. In the ...
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... TS68230 SECTION 1 INTRODUCTION The TS68230 parallel interface/timer (PI/T) provides versatile double buffered parallel interfaces and a system oriented timer for TS68000 systems. The parallel interfaces operate in unidirectional or bidi- rectional modes, either bits wide. In the uni- directional modes, an associated data direction register determines whether each port pin is an input or output ...
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... Figure 1.1 : Block Diagram. TS68230 3/61 ...
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... TS68230 Table 1.1 : Port Mode Control Summary. Mode 0 (unidirectional 8-bit mode) Port A Submode 00 - Pin-definable Double-buffered Input or Single-buffered Output H1 - Latches Input Data H2 - Status/interrupt Generating Input, General-purpose Output, or Operation with H1 in the Interlocked or Pulsed Handshake Protocols Submode 01 - Pin-definable Double-buffered Output or Non-latched Input H1 - Indicates Data Received by Peripheral ...
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... Figure 1.2 : Port Mode Layout. TS68230 5/61 ...
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... TS68230 Figure 1.2 : Port Mode Layout (continued). 1.2. SIGNAL DESCRIPTION Throughout this data sheet, signals are presented u- sing the terms active and inactive or asserted and negated independent of whether the signal is active in the high-voltage state or low-voltage state. (The active state of each logic pin is given below). Active low signals are denoted by a superscript bar ...
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... High Read, Low Write Level Low Level Low Level Rising Edge High Level Low Low TS68230 OutputStates High, Low, High Impedance High, Low High, Low, High Impedance* High, Low, High Impedance High, Low, High Impedance Low, High Impedance* High, Low Low, High Impedance* 7/61 ...
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... TS68230 1.2.3. READ/WRITE (R/W). R high impe- dance read/write input signal from the TS68000 bus master, indicating whether the current bus cycle is a read (high) or write (low) cycle. 1.2.4. CHIP SELECT (CS high-impedance input that selects the PI/T registers for the current bus cycle. Address strobe and the data strobe (up- ...
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... Bit Bit Bit Bit H4S H3S H2S H1S Level TS68230 Register Value after RESET (hex value Port General Control Register 0 0 Port Service Request Register Bit 0 0 Port A Data 0 Direction Register Bit 0 0 Port B Data ...
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... TS68230 Table 1.3 : Register Model (continued). Register Select Bits TOUT/TIACK Control Bit Bit Bit Bit Bit Bit Bit Bit Bit ...
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... The TS68230 CLK pin has the same specifica- tions as the TS68000 CLK pin, and must not be ga- ted off at any time. ...
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... TS68230 of chip select, then three-stated to avoid interfe- rence with the next bus cycle. The system designer must take care that DTACK is negated and three-stated quickly enough after each bus cycle to avoid interference with the next one. With an TS68000 this necessitates a relatively fast external path from the data strobe negation to CS bus master negation ...
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... A (port B) data register. Thus, anytime the H2(H4) output is as- serted, new input data may be entered by as- serting H1(H3). At other times transitions of H1(H3) are ignored. The H2S(H4S) status bit is always zero. When H12 enable (H34 enable) is zero, H2(H4) is held negated. TS68230 13/61 ...
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... TS68230 5. H2(H4) may be an output pin in the pulsed in- put handshake protocol asserted exactly as in the interlocked input protocol, but never remains asserted longer than four clock cy- cles. Typically, a four clock cycle pulse is ge- nerated. But in the case that a subsequent H1(H3) asserted edge occurs before termina- tion of the pulse, H2(H4) is negated asynchro- nously ...
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... DMAREQ pin is not currently associated. The most-significant six bits are provided by the port interrupt vector register (PIVR), with the lower two bits supplied by prioriti- zation logic according to conditions present when PIACK is asserted important to note that the on- TS68230 15/61 ...
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... H1(H3) and falling edge for CS). Refer to 1.4 BUS INTERFACE OPERATION for the exception concer- 16/61 DMAREQ is generated on the bus side of the TS68230 by the synchronized* chip select. If the conditions of figures 2.3 or 2.4 are met, an assertion of CS will cause DMAREQ to be asserted three PI/T clocks (plus the delay time from the clock edge) after CS is synchronized ...
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... They have no effect on the operation of the hand-shake pins, double-buffered transfers, status bits, or any o- ther aspect of the PI/T, and they are mode/submode independent. Refer to 4.7. Port Alternate Regis- ters for further information. TS68230 17/61 ...
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... TS68230 SECTION 3 PORT MODES This section contains information that distinguishes the various port modes and submodes. General characteristics common to all modes are defined in Section 2 Port General Information and Conven- tions. A description of the port A control register (PACR) and port B control register (PBCR) is given before each mode description ...
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... Output pins may be used independently of the input transfers. However, read bus cycles to the data register do re- move data from the port. Therefore, care should be taken to avoid processor instructions that perform unwanted read cycles. TS68230 Note 1 Note 2 Note 1 19/61 ...
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... TS68230 Programmable Options Mode 0 - Port A Submode 00 and Port B Submode 00 PACR 7 6 Port A Submode 0 0 Submode 00 PACR Control Input pin - edge-sensitive status input, H2S is set on an asserted edge Output pin - negated, H2S is always clear Output pin - asserted, H2S is always clear. ...
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... The H3S(H4S) status bit is always clear. When H12 enable (H34 enable) is clear H2(H4) is held negated. For pins used as inputs, data written to the associa- ted data register is double-buffered and passed to the initial or final output latch, but, the output buffer is disabled. TS68230 21/61 ...
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... TS68230 Programmable Options Mode 0 - Port A Submode 01 and Port B Submode 01 PACR 7 6 Port A Submode 0 1 Submode 01 PACR Control Input pin - edge-sensitive status inputs, H2S is set on an asserted edge Output pin - negated, H2S is always clear Output pin - asserted, H2S is always clear. ...
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... H2(H4) may be a general-purpose output pin that is always negated. In this case the H2S(H4S) status bit is always clear. 3. H2(H4) may be a general-purpose output pin that is always asserted. In this case the H2S(H4S) status bit is always clear. TS68230 23/61 ...
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... TS68230 Programmable Option Mode 0 - Port A Submode 1X and Port B Submode 1X PACR 7 6 Port A Submode 1 X Submode 1X PACR Control Input pin - edge-sensitive status input, H2S is set on an asserted edge Output pin - negated, H2S is always cleared Output pin - asserted, H2S is always cleared. ...
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... The interlocked and pulsed handshake protocols, status bits, and DMAREQ are keyed to the access of port B data register in mode 1. Transfers proceed properly with interlocked or pulsed handshakes when the port B data register is accessed last. TS68230 DDR = 1 FOL Note 2 IOL/FOL Note 1 ...
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... TS68230 3.4.1. PORT A CONTROL REGISTER (PACR Port A Interrupt SVCRQ Submode H2 Control Enable The port A control register, in conjunction with the programmed mode and the port B submode, controls the operation of port A and the handshake pins H1 and H2. The port A control register contains five fields : bits 7 and 6 specify the port A submode ...
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... H12 enable bit of the port general control re- gister is clear may be a general-purpose output pin that is always negated. The H2S status bit is al- ways clear may be a general-purpose output pin that is always asserted. The H2S status bit is al- ways clear. TS68230 27/61 ...
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... TS68230 Programmable Options Mode 1 - Port A Submode XX and Port B Submode X0 (continued) PBCR Control Input pin - edge-sensitive status input, H4S is set on an asserted edge Output pin - negated, H4S is always cleared Output pin - asserted, H4S is always cleared Output pin - interlocked input handshake protocol. ...
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... The H2S status bit is al- ways clear. For pins used as inputs, data written to either data register is double buffered and passed to the initial or final output latch, as usual, but the output buffer is disabled (refer to 3.3.2. Submode 01 - Pin-Defi- nable Double-Buffered Output or Non-Latched Input). TS68230 29/61 ...
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... TS68230 Programmable Options Mode 1 - Port A Submode XX and Port B Submode X1 (continued) PBCR Control Input pin - edge-sensitive status input, H4S is set on an asserted edge Output pin - negated, H4S is always cleared Output pin - asserted, H4S is always cleared Output pin - interlocked input handshake protocol. ...
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... When H12 enable in the port general control register is clear held negated may be an output pin in the pulsed output handshake protocol asserted exactly as in the interlocked output protocol above, but ne- ver remains asserted longer than four clock cy- TS68230 DDR = 1 FOL 31/61 ...
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... TS68230 cles. Typically, a four clock cycle pulse is ge- nerated. But in the case that a subsequent H1 asserted edge occurs before termination of the pulse negated asynchronously. Thus, anytime after the leading edge of the H2 pulse, new data may be transferred to the double- buffered output latches. The H2S status bit is Table 3 ...
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... But in the case that a subsequent H3 asserted edge occurs before termination of the pulse negated asynchronously. Thus, anytime after the leading edge of the H4 pulse, new data may be entered in the double-buffered input latches. The H4 status bit is always clear. When H34 en- able is clear held negated. TS68230 33/61 ...
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... TS68230 3.6.2. DOUBLE-BUFFERED OUTPUT TRANS- FERS. Data, written by the bus master to the PI/T, is stored in the port’s output latch. The peripheral ac- cepts the data by asserting H1, which causes the next data to be moved to the port’s output latch as soon available. The H1S status bit, in the port status register, may be programmed for two inter- pretations ...
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... The H4 interrupt is disabled. 1 The H4 interrupt is enabled. PBCR 1 H3 SVCRQ Enable 0 The H3 interrupt and DMA request are disabled. 1 The H3 interrupt and DMA request are enabled. PBCR 0 H3 Status Control X The H3S status bit is set anytime input data is present in the double-buffered input path. TS68230 35/61 ...
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... TS68230 SECTION 4 PROGRAMMER’S MODEL This section describes the internal accessible regis- ter organization as represented in table 1.3 located Table 4.1 : PI/T Register Addressing Assignments. Register Port General Control Register Port Service Request Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register ...
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... The PSRR is always readable and writable. All bits are reset to zero when the RESET pin is as- serted. PSRR The PC4/DMAREQ pin carries the PC4 TS68230 H12 Enable 0 Handshake Pin Sense Operation Port Interrupt ...
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... TS68230 function ; DMA is not used. PSRR SVCRQ Select 1 0 The PC4/DMAREQ pin carries the DMAREQ function and is associatedwith double-buffered transfers controlled by H1 removed from PI/T’s interrupt structure, and thus, does not cause interrupt requests to be generated. To obtain DMAREQ pulses, port A control register bit 1 (H1 SVCRQ enable) must be a one ...
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... C/ alternate-func- tion pins. The exact hardware accessed is determi- ned by the type of bus cycle (read or write) and individual conditions affecting each pin. These conditions are : 1) whether the pin is used for the port C or alternate function, and 2) whether the port C da- TS68230 39/61 ...
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... TS68230 Table 4.3 : PCDR Hardware Accesses. Operation PCDDR = 0 Read Port C Data Pin Register Write Port C Data Output Register, Register Buffer Disabled ta direction register indicates the input or output di- rection. The port C data register is single buffered for output pins and non-latched for input pins. These conditions are summarized in table 4 ...
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... The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise, the timer is in the halt state The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented TS68230 41/61 ...
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... TS68230 following the rising transition of the TIN pin after being synchronized with the internal clock. The 24-bit counter is decremented, rolls over loaded from the counter preload registers when the prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the run or halt state ...
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... Programming of the timer control register is outlined with several examples given. 5.1. TIMER OPERATION The TS68230 timer can provide several facilities needed by TS68000 operating systems. It can ge- nerate periodic interrupts, a square wave single interrupt after a programmed time period. Also, it can be used for elapsed time measurement device watchdog ...
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... TS68230 8. For configurations in which the prescaler is not u- sed, the contents of the counter preload registers are transferred to the counter on the first asserted edge of the TIN input after entering the run state. On subsequent asserted edges the counter de- crements, rolls over loaded from the counter preload registers ...
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... CPRs. When the processor takes the interrupt it can halt the timer, read the counter and calculate the time from the inter- rupt request to entering the service routine. Accurate knowledge of the interrupt latency may be useful in some applications (see figure 5.3). TS68230 45/61 ...
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... TS68230 Figure 5.3 : Single Interrupt after Timeout Example. 5.2.4. ELAPSED TIME MEASUREMENT EXAM- PLES. Elapsed time measurement takes several forms ; two forms are described in the following paragraphs. 5.2.4.1. System Clock Example Z.D Clock TOUT/TIACK * Control Control Control This configuration allows time interval measure- ment by software ...
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... TOUT output is asserted. (The counter rolls over and keeps counting). In either case, when the TIN input is negated the ZDS status bit is zero, the TOUT 1 0 output is negated, the counting stops, and the pres- caler is forced to all ones (see figure 5.5). Timer Enable 1 Changed TS68230 47/61 ...
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... TS68230 SECTION 6 ELECTRICAL SPECIFICATIONS This section contains electrical specifications and associated timing information for the TS68230. 6.1 ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage CC V Input Voltage IN T Operating Temperature Range A TS68230C TS68230V T Storage Temperature This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields ; however advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high- 6 ...
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... H1, H3, R/W, RESET, CLK, RS1-RS5, CS D0-D7 DTACK, PC0-PC7, H2, H4, PA0-PA7, PB0-PB7 DTACK, D0-D7 H2, H4, PB0-PB7, PA0-PA7 PC0-PC7 PC3/TOUT, PC5/PIRQ D0-D7, DTACK PA0-PA7, PB0-PB7, H2, H4, PC0-PC2, PC4, PC6, PC7 = 1MHz) A Parameter TS68230 = unless otherwise noted Min. Max. Unit – ...
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... TS68230 6.6. AC ELECTRICAL SPECIFICATIONS (V = 5.0Vdc 5 0Vdc Read and Write Cycle Timings (figures 6.2 and 6.3) Number 1 R/W, RS1-RS5 Valid to CS Low (setup time Low to R/W and RS1-RS5 Invalid (hold time Low to CLK Low (setup time Low to Data Out Valid 5 RS1-RS5 Valid to Data Out Valid ...
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... Figure 6.2 : Read Cycle Timing Diagram. Figure 6.3 : Write Cycle Timing Diagram. TS68230 51/61 ...
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... TS68230 6.6. AC ELECTRICAL SPECIFICATIONS (V = 5.0Vdc 5 0Vdc Peripheral Input Timings (figures 6.4) Number 14 Port Input Data Valid to H1(H3) Asserted (setup time) 15 H1(H3) Asserted to Port Input Data Invalid (hold time) 16 Handshake Input H1(H4) Pulse Width Asserted 17 Handshake Input H1(H4) Pulse Width Negated 18 H1(H3) Asserted to H2(H4) Negated (delay time) ...
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... Figure 6.4 : Peripheral Input Timing Diagram. 7. CLK refers to the actual frequency of the CLK pin, not the maximum allowable CLK frequency. Note : Timing measurements are referenced to and from a low voltage of 0.8volt and a high voltage of 2.0volts, unless otherwise noted. Notes : 1. This specification assures recognition of the asserted edge of H1(H3). TS68230 53/61 ...
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... TS68230 6.6. AC ELECTRICAL SPECIFICATIONS (V = 5.0Vdc 5 0Vdc Peripheral Output Timings (figures 6.5) Number 16 Handshake Input H1(H4) Pulse Width Asserted 17 Handshake Input H1(H4) Pulse Width Negated 18 H1(H3) Asserted to H2(H4) Negated (delay time) 19 CLK Low to H2(H4) Asserted (delay time H2(H4) Asserted to H1(H3) Asserted ( CLK Low to H2(H4) Pulse Negated (delay time ...
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... Figure 6.5 : Peripheral Ouput Timing Diagram. Notes : 1. Timing diagram shows H1, H2, H3, and H4 asserted low. 2. Timing measurements are referenced to and from a low voltage of 0.8volt and a high voltage of 2.0volts, unless otherwise noted. TS68230 55/61 ...
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... TS68230 6.6. AC ELECTRICAL SPECIFICATIONS (V = 5.0Vdc 5 0Vdc Iack Timings (figure 6.6) Number PIACK or TIACK High to Data Out Invalid (hold time PIACK or TIACK High to D0-D7 High Impedance PIACK or TIACK High to DTACK High PIACK or TIACK High to DTACK High Impedance 29 CLK Low to Data Output Valid, Interrupt Acknowledge Cycle ...
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... Synchronized means that the input signal has been seen by the PI/T on the appropriate edge of the clock (rising edge for H1(H3) and falling edge for CS). (Refer to the 1.4. Bus Interface Operation for the exception concerning CS). 7.1. PIN ASSIGNMENTS 48-Pin Dual-in-Line 52-Pin Quad Pack (PLCC) TS68230 57/61 ...
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... TS68230 7.2. PACKAGE MECHANICAL DATA mm mm 58/61 ...
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... Bit Bit Bit Bit Bit Bit Bit Bit ZDS TS68230 Register Value after RESET (hex value Timer Control Register 0 F Timer Interrupt Vector Register 0 0 (null) Counter Preload Register (high) Counter Preload Register (mid) Counter Preload ...
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... TS68230 Table 1.3 : Register Model (sheet 1 of 2). Register Select Bits Port Mode H34 Control Enable SVCRQ Select Bit Bit Bit Bit Bit Bit Bit ...
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... The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. Temperature Range system is granted provided that the system conforms to the I Specification as defined by Philips. TS68230 Package Type Plastic DIL P Suffix PLCC FN Suffix 2 C Patent Standard 61/61 ...