DT28F320S5-90 Intel Corporation, DT28F320S5-90 Datasheet
DT28F320S5-90
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DT28F320S5-90 Summary of contents
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FlashFile™ MEMORY FAMILY 28F160S5, 28F320S5 Includes Extended Temperature Specifications n Two 32-Byte Write Buffers 2 s per Byte Effective Programming Time n Operating Voltage Read Access Time (16 Mbit ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel’s website at http:\\www.intel.com COPYRIGHT © INTEL CORPORATION, 1997 *Third-party brands and names are the property of their respective owners. CG-041493 ...
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INTRODUCTION .............................................5 1.1 New Features...............................................5 1.2 Product Overview.........................................5 1.3 Pinout and Pin Description ...........................6 2.0 PRINCIPLES OF OPERATION .......................9 2.1 Data Protection ..........................................10 3.0 BUS OPERATION .........................................11 3.1 Read ..........................................................11 3.2 Output Disable ...........................................11 3.3 Standby......................................................11 3.4 Deep Power-Down ...
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REVISION HISTORY Number -001 Original version 4 Description ADVANCE INFORMATION ...
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INTRODUCTION This datasheet contains Word-Wide FlashFile™ memory (28F160S5, 28F320S5) specifications. Section 1 provides a flash memory overview. Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications for extended temperature product offerings. ...
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Individual block locking uses a combination of block lock-bits to lock and unlock blocks. Block lock-bits gate block erase, full chip erase, program and write to buffer operations. Lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits ...
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Table 1. Pin Descriptions Sym Type A –A INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally 0 21 latched during a write cycle x16 mode not used; input buffer is off. 0 ...
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Figure 3. 28F320S5 and 28F160S5 SSOP 56-Lead Pinout 2.0 PRINCIPLES OF OPERATION The Word-Wide FlashFile memories include an on-chip Write State Machine (WSM) to manage block erase, program, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed ...
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Read Array, Status Register, query, and identifier codes can be accessed through the CUI independent of the V voltage. PP programming voltage on V enables successful PP block erasure, program, and configuration. All functions associated altering memory contents—block ...
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BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Block information, query information, identifier codes and Status Registers can ...
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Read Identifier Codes Operation The read-identifier codes operation outputs the manufacturer code, device code, and block lock configuration codes for each block configuration (see Figure 5). Using the manufacturer and device codes, the system software automatically match ...
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Table 2. Bus Operations Mode Notes RP Read 1 Output Disable Standby Reset/Power Down Mode Read Identifier ...
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Table 3. Word-Wide FlashFile™ Memory Command Set Definitions Command Scaleable Bus or Basic Cycles Command Req'd Set (14) Read Array SCS/BCS 1 Read Identifier Codes SCS/BCS Read Query SCS Read Status Register SCS/BCS 2 Clear Status Register SCS/BCS ...
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NOTES: 1. Bus operations are defined in.Table Any valid address within the device Address within the block being erased or locked Identifier Code Address: see Table 12 Query database Address. ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for ...
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Table 4. Summary of Query Structure Output as a Function of Device and Mode Device Type/Mode Word Addressing Location x16 device/ 10h x16 mode 11h 12h x16 device/ N/A (1) x8 mode NOTE: 1. The system must drive the lowest ...
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QUERY STRUCTURE OVERVIEW The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized in Table 8. The following sections describe the ...
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BLOCK STATUS REGISTER The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Table 7. Block Status Register Offset Length (bytes) (1) (BA+2)h ...
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CFI QUERY IDENTIFICATION STRING The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which vendor- specified command set(s) is (are) supported. Table 8. ...
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SYSTEM INTERFACE INFORMATION The following device information can be useful in optimizing system interface software. Table 9. System Interface Information Offset Length (bytes) 1Bh 01h V Logic Supply Minimum Program/Erase Voltage CC bits 7–4 BCD volts bits 3–0 BCD ...
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DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. Table 10. Device Geometry Definition Offset Length (bytes) 27h 01h Device Size = 2 N 28h 02h Flash Device Interface Description value 0002h 2Ah ...
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INTEL-SPECIFIC EXTENDED QUERY TABLE Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. Table 11. Primary-Vendor Specific Extended Query Offset (1) Length (bytes) (P)h 03h Primary Extended Query ...
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Table 11. Primary-Vendor Specific Extended Query (Continued) Offset Length (bytes) (P+C)h 01h V Logic Supply Optimum Program/Erase voltage CC (highest performance) bits 7–4 bits 3–0 (P+D)h 01h V [Programming] Supply Optimum Program/Erase PP voltage bits 7–4 bits 3–0 ...
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Following a program, block erase, set block lock-bit, or clear block lock-bits command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O pins DQ and DQ are invalid. When the 0-6 8-15 ...
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This two-step command sequence of setup followed by execution ensures that block contents are not accidentally erased. An invalid Full Chip Erase command sequence will result in both Status Register bits SR.4 and SR.5 being set to 1. ...
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Status Register bits PP PPLK SR.4 and SR.3 will be set to “1.” Successful byte/word programming requires corresponding block lock-bit be cleared byte/word program is attempted when corresponding block lock-bit is set and ...
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The only other valid commands while programming is suspended are Read Status Register and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. Status Register bits SR.2 and SR.7 will ...
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Table 13. Write Protection Alternatives Block Operation Lock- WP# Bit Program and Block Erase Full Chip Erase 0 Set or Clear ...
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Table 15. Status Register Definition WSMS ESS ECLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block erase suspended 0 = Block erase in ...
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Start Set Time-Out Issue Write Command No E8H, Block Address Read Extended Status Register Write Buffer 0 XSR.7 = Time-Out? 1 Write Word or Byte Count, Block Address Write Buffer Data, Start Address Yes ...
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Figure 7. Single Byte/Word Program Flowchart 32 0608_08 ADVANCE INFORMATION ...
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Figure 8. Program Suspend/Resume Flowchart ADVANCE INFORMATION 28F160S5, 28F320S5 0608_09 33 ...
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Start Device Supports Queuing Yes Set Time-Out Issue Block Queue Erase Command 28H, Block Address No Read Extended Status Register Is Queue Erase Block 0=No Available? Time-Out? XSR.7= 1=Yes Another Block Yes Erase? Yes Issue Erase Command 28H ...
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Start Write B0H Read Status Register 0 SR SR.6 = Block Erase Completed 1 Read Write Read or Write? Write Read Array No Data Loop Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data ...
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Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage ...
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Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range Error 0 1 SR.1= ...
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DESIGN CONSIDERATIONS 5.1 Three-Line Output Control Intel provides three control inputs to accommodate multiple memory connections ( OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation; b. Data bus ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings Temperature under Bias ................ –40°C to +85°C Storage Temperature................... –65°C to +125°C Voltage On Any Pin (except V and .................................... –0. Supply Voltage ............ ...
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CAPACITANCE Table 18. Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT NOTE: 1. Sampled, not 100% tested. 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 3.0 INPUT 1.5 0.0 AC test inputs are driven at 3.0V for ...
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DC CHARACTERISTICS Table 19. DC Characteristics, T Sym Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down Current CCD Read Current CCR CC I ...
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Table 19. DC Characteristics (Continued) Sym Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage (TTL) OH1 V Output High Voltage (CMOS) OH2 V V Lockout Voltage ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Table 20. AC Read Characteristics Versions (4) (All units in ns unless otherwise noted) # Sym Parameter R1 t Read/Write Cycle Time AVAV R2 t Address to Output Delay AVQV ...
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Note the latter and CE # low or the first Figure 16. AC Waveform for Read Operations high ADVANCE INFORMATION ...
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AC CHARACTERISTICS - WRITE OPERATIONS Table 21. Write Operations Versions (6) # Sym RP# High Recovery to WE# (CE ) PHWL PHEL Setup to WE# Going Low ELWL ...
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NOTES power-up and standby Write block erase or program setup. C. Write block erase confirm or valid address and data.. D. Automated erase or program delay. E. Read Status Register data. F. Write Read ...
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RESET OPERATIONS Figure 18. AC Waveform for Reset Operation Table 22. Reset AC Specifications # Sym Parameter P1 t RP# Pulse Low Time PLPH (If RP# is tied this specification is not applicable ...
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ERASE, PROGRAM, AND LOCK-BIT CONFIGURATION PERFORMANCE Table 23. Erase/Write/Lock Performance Version # Sym W16 Byte/word program time (using write buffer) W16 t Per byte program time (without write buffer) WHQV1 t EHQV1 W16 t Per word program ...
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APPENDIX A DEVICE NOMENCLATURE AND ORDERING INFORMATION Product line designator for all Intel Flash products Package DT = Extended Temp. 56-Lead SSOP TE = Extended Temp. 56-Lead TSOP Device ...
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ADDITIONAL INFORMATION Order Number 290608 Word-Wide FlashFile™Memory Family 28F160S3, 28F320S3 Datasheet 292203 AP-645 28F160S3/S5 Compatibility with 28F016SA/SV AP-646 Common Flash Interface and Command Sets 292204 290528 28F016SV 16-Mb (1Mbit x 16, 2Mbit x 8) FlashFile™ Memory Datasheet 290489 ...