HY5DS573222F-33 Hynix Semiconductor, HY5DS573222F-33 Datasheet
HY5DS573222F-33
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HY5DS573222F-33 Summary of contents
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... HY5DS573222F(P) 256M(8Mx32) GDDR SDRAM HY5DS573222F(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Feb. 2005 1 ...
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... CL, tCK_max, tRAS, tDAL change & Comment of DLL_off condition 1) Changed IDD & VDD_max 0.5 2) Changed tRCDWR, tWR, CL, tCK_max at 350Mhz speed bin 1.0 Version 1.0 Release Rev. 1.0 / Feb. 2005 History 1HY5DS573222F(P) Draft Date Remark Mar. 2004 Apr. 2004 Apr. 2004 Jun. 2004 Oct. 2004 Feb. 2005 ...
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... Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials. We'll add "P" character after "F" for lead free product. For example, the part number of 300Mhz Lead free product is HY5DS573222FP-33. Rev. 1.0 / Feb. 2005 • ...
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... PIN CONFIGURATION (Top View) ROW and COLUMN ADDRESS TABLE Organization Row Address Column Address Bank Address Auto Precharge Flag Rev. 1.0 / Feb. 2005 Items 8Mx32 4banks A0 ~ A11 A0 ~ A7, A9 BA0, BA1 Refresh 1HY5DS573222F( ...
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... DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31 Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. 1HY5DS573222F(P) 5 ...
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... Rev. 1.0 / Feb. 2005 Write Data Register 2-bit Prefetch Unit 64 Bank 2Mx32/Bank0 Control 2Mx32 /Bank1 2Mx32 /Bank2 2Mx32 /Bank3 Row Decoder Column Decoder Column Address Counter CLK_DLL CLK, DLL /CLK Block Mode Register 1HY5DS573222F( DQ[0:31] DQS(0~3) Data Strobe Transmitter Data Strobe DS Receiver 6 ...
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... 1HY5DS573222F(P) A8 Note ADDR code 1 code ...
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... Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data. 2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the data on DQ24-Q31. Rev. 1.0 / Feb. 2005 /CS, /RAS, CKEn DM(0~3) /CAS, / 1HY5DS573222F(P) A8/ BA ADDR Note 1,2 1,2 ...
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... OPCODE MRS DSEL NOP BST L H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP 1HY5DS573222F(P) Action 3 NOP or power down 3 NOP or power down 4 ILLEGAL 4 ILLEGAL 4 ILLEGAL Row Activation NOP 5 Auto Refresh or Self Refresh Mode Register Set NOP NOP 4 ILLEGAL 6 Begin read : optional AP ...
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... L H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP H H BA, RA ACT H L BA, AP PRE/PALL AREF/SREF L L OPCODE MRS 1HY5DS573222F(P) Action 4 ILLEGAL Term burst, precharge 11 ILLEGAL 11 ILLEGAL Continue burst to end Continue burst to end ILLEGAL 10 ILLEGAL 10 ILLEGAL 4,10 ILLEGAL 4,10 ILLEGAL 11 ILLEGAL 11 ILLEGAL Continue burst to end ...
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... L OPCODE MRS DSEL NOP BST L H BA, CA, AP READ/READAP 1HY5DS573222F(P) Action NOP - Enter ROW ACT after tRCD NOP - Enter ROW ACT after tRCD 4 ILLEGAL 4,10 ILLEGAL 4,10 ILLEGAL 4,9,10 ILLEGAL 4,10 ILLEGAL 11 ILLEGAL 11 ILLEGAL NOP - Enter ROW ACT after tWR NOP - Enter ROW ACT after tWR ...
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... BST L H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP H H BA, RA ACT H L BA, AP PRE/PALL AREF/SREF L L OPCODE MRS 1HY5DS573222F(P) Action 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL NOP - Enter IDLE after tMRD NOP - Enter IDLE after tMRD 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL ...
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... 1HY5DS573222F(P) /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle ...
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... SREF IDLE SREX PDEX AREF ACT POWER DOWN PDEN BST PDEX BANK ACTIVE WRITE READ READAP WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITEAP WRITE PRE(PALL) PRE- CHARGE POWER-UP POWER APPLIED 1HY5DS573222F(P) SELF REFRESH AUTO REFRESH READ READ Command Input Automatic Sequence 14 ...
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... Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles of clock are required for locking DLL) 6. Issue Precharge commands for all banks of the device. Rev. 1.0 / Feb. 2005 Sequencing Voltage relationship to avoid latch-up After or with VDD 1HY5DS573222F(P) < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 15 ...
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... CODE CODE tRP tMRD tMRD tRP EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command 1HY5DS573222F(P) AREF MRS ACT RD CODE CODE CODE CODE CODE CODE CODE CODE CODE ...
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... A5 A4 CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved 1HY5DS573222F( Burst Length A1 A0 Sequential Interleave 0 0 Reserved Reserved Reserved Reserved 0 1 Reserved Reserved 1 0 ...
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... Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table Rev. 1.0 / Feb. 2005 1HY5DS573222F(P) Sequential ...
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... This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-to- point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2, Class II, and Matched impedance driver, about 30% of Full drive strength. Rev. 1.0 / Feb. 2005 1HY5DS573222F(P) 19 ...
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... All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 1.0 / Feb. 2005 RFU Output Driver Impedance Control 1HY5DS573222F( DLL A0 DLL enable 0 Enable 1 Diable Full Half RFU* Weak 20 ...
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... DC level of the same. DDQ the DC value Voltage referenced Min. Max 0. =0V disabled OUT 1HY5DS573222F(P) Rating Unit -55 ~ 125 o C -0.5 ~ 3.6 V -0.5 ~ 3.6 V -0 260 ˜ ˜sec = 0V) SS Max Unit Note 2 ...
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... I =0mA All banks active (min), RC RFC All banks active CKE d 0.2V Four bank interleaving with BL=4, Refer to the following page for detailed test condition 1HY5DS573222F(P) = 0V) SS Speed Unit 190 170 160 140 mA 210 200 180 170 mA ...
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... IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V -0.2 IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V) Value V DDQ V DDQ V REF V REF 1HY5DS573222F(P) = 0V) Max Unit Note 0.35 V REF DDQ 0.5*V +0 DDQ Unit REF ...
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... DQSQ - 0.35 - 0.35 tHPmin tHPmin -tQHS -tQHS tCH/L tCH min min t QHS - 0. 0. 0. 0.4 0.6 0.4 0.6 DQSH t DQSL 0.4 0.6 0.4 0.6 t DQSS 0.85 1.15 0.85 1.15 1HY5DS573222F( Unit Min Max Min Max 100K 8 100K ...
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... Max t DS 0. 0. 0.9 1.1 0.9 1.1 RPRE t RPST 0.4 0.6 0.4 0.6 WPRES WPREH 0. 0.4 0.6 0.4 0.6 WPST t MRD XSC 200 - 200 - 2tCK 2tCK t PDEX - - + tIS + tIS t REFI - 7.8 - 7.8 1HY5DS573222F( Unit Note Min Max Min Max ns 0 0 0.9 1.1 0.9 1.1 CK 0.4 0.6 0.4 0 0. 0.4 0.6 0.4 0 200 - 200 - 1tCK 1tCK tIS + tIS us - 7 ...
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... AC CHARACTERISTICS - II Frequency CL tRC 350MHz (2.8ns 300MHz (3.3ns 275MHz (3.6ns 250MHz (4.0ns Rev. 1.0 / Feb. 2005 tRFC tRAS tRCDRD tRCDWR 1HY5DS573222F(P) tRP tDAL Unit tCK tCK tCK tCK 26 ...
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... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output Rev. 1.0 / Feb. 2005 Pin CK, /CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50: T Zo=50: V REF C =30pF L 1HY5DS573222F(P) Symbol Min Max Unit ...
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... PACKAGE INFORMATION 12mm x 12mm, 144ball Fine-pitch Ball Grid Array Rev. 1.0 / Feb. 2005 1HY5DS573222F(P) 28 ...