PM6341-QI PMC-Sierra Inc, PM6341-QI Datasheet
PM6341-QI
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PM6341-QI Summary of contents
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... DATA SHEET PMC-910419 E1 FRAMER/TRANSCEIVER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC DATA SHEET ISSUE 8: JUNE 1998 PM6341 E1XC E1 FRAMER/TRANSCEIVER ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Details of Change Data Sheet Reformatted — No Change in Technical Content. Generated R8 data sheet from PMC-901204, R10 Update to rev 9 of Eng Doc Update to rev 6 of Eng Doc Creation of Document PM6341 E1XC E1 FRAMER/TRANSCEIVER ...
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... CRC FRAME FIND............................................................ 48 1.4.3 CRC CHECK AND AIS DETECTION ................................ 49 1.1.4 SIGNALLING FRAME FIND.............................................. 49 1.1.5 ALARM INTEGRATION..................................................... 50 1.5 PERFORMANCE MONITOR COUNTERS (PMON) .................... 51 1.6 HDLC RECEIVER (RFDL) ........................................................... 51 1.7 ELASTIC STORE (ELST) ............................................................ 52 1.8 SIGNALLING EXTRACTOR (SIGX)............................................. 52 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER i ...
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... OPERATIONS....................................................................................... 198 14.1 CONFIGURING THE E1XC FROM RESET............................... 198 14.2 USING THE INTERNAL FDL TRANSMITTER ........................... 199 14.3 USING THE INTERNAL FDL RECEIVER.................................. 201 14.3.1 KEY USED ON SUBSEQUENT DIAGRAMS: ................. 205 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 ........................................................................................ 177 PM6341 E1XC E1 FRAMER/TRANSCEIVER ii ...
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... ALTERNATE TCLKO REFERENCE APPLICATION ........ 226 1.10.5 CHANGING THE JITTER TRANSFER FUNCTION ........ 226 1.11 USING THE PERFORMANCE MONITOR COUNTER VALUES 226 2 ABSOLUTE MAXIMUM RATINGS........................................................ 230 3 CAPACITANCE ..................................................................................... 231 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER iii ...
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... DATA SHEET PMC-910419 4 D.C. CHARACTERISTICS ................................................................... 232 5 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ...... 234 6 E1XC I/O TIMING CHARACTERISTICS .............................................. 239 7 ANALOG CHARACTERISTICS ............................................................ 252 8 ORDERING AND THERMAL INFORMATION ...................................... 254 9 MECHANICAL INFORMATION ............................................................ 255 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER iv ...
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... REGISTER 12H: CDRC INTERRUPT STATUS ............................................... 106 REGISTER 13H: ALTERNATE LOSS OF SIGNAL STATUS............................ 108 REGISTER 14H: XPLS BLOCK LINE LENGTH CONFIGURATION ............... 109 REGISTER 15H: XPLS BLOCK CONTROL/STATUS...................................... 111 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER v ...
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... REGISTER 29H: FRMR EXTRA BITS ............................................................ 135 REGISTER 2AH: FRMR CRC ERROR COUNTER – LSB .............................. 136 REGISTER 2BH: FRMR CRC ERROR COUNTER – MSB ............................. 137 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER CONTROL vi ...
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... SIGX INDIRECT REGISTERS 49 (31H)- 63 (3FH) - SEGMENT 2: TYPICAL TIMESLOT SIGNALLING DATA REGISTER (TSS 17-31) .................... 165 SIGX INDIRECT REGISTERS 64 (40H (5FH) - SEGMENT 3: TYPICAL PER-TIMESLOT PCM TRUNK CONDITIONING DATA REGISTER ..... 166 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER vii ...
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... REGISTER 4F: LINE CODE VIOLATION COUNT MSB .................................. 184 REGISTER 5CH: RSLC BLOCK CONFIGURATION....................................... 185 REGISTER 5DH: RSLC BLOCK INTERRUPT ENABLE/STATUS................... 186 REGISTER 0BH: E1XC MASTER TEST ......................................................... 190 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER viii ...
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... FIGURE 18- RECEIVE COMPOSITE MULTIFRAME OUTPUT (BRXSMFP=1 AND BRXCMFP=1): ............................................................................. 196 FIGURE 19- RECEIVE OVERHEAD OUTPUT (ROHM=1):............................ 196 FIGURE 20- RECEIVE LINE DATA INTERFACE ............................................ 196 FIGURE 21- TRANSMIT BACKPLANE INTERFACE ...................................... 197 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER ix ...
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... FIGURE 41- DIGITAL RECEIVE INTERFACE INPUT TIMING DIAGRAM...... 243 FIGURE 42- TRANSMIT DATA LINK INPUT TIMING DIAGRAM .................... 244 FIGURE 43- BACKPLANE RECEIVE INPUT TIMING DIAGRAM................... 245 FIGURE 44- RECEIVE DATA LINK OUTPUT TIMING DIAGRAM................... 246 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER x ...
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... FIGURE 50- ANALOG RECEIVE DATA INPUT TIMING DIAGRAM................ 252 FIGURE 51- 68 PIN PLASTIC LEADED CHIP CARRIER (Q SUFFIX)........... 255 FIGURE 52- 80 PIN COPPER LEADFRAME PLASTIC QUAD FLAT PACK (R SUFFIX):............................................................................................... 256 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER xi ...
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... TABLE 19 - MICROPROCESSOR WRITE ACCESS (FIGURE 37) ............... 237 TABLE 20 - BACKPLANE TRANSMIT INPUT TIMING (FIGURE 38) ............ 239 TABLE 21 - XCLK=49.152MHZ INPUT (FIGURE 39).................................... 240 TABLE 22 - TCLKI INPUT (FIGURE 40)........................................................ 241 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER xii ...
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... TABLE 32 - RECEIVE ANALOG INPUT THRESHOLD ................................. 252 TABLE 33 - ANALOG RECEIVE DATA INPUT TIMING (FIGURE 50) ........... 252 TABLE 34 - TRANSMIT PULSE SYMMETRY ............................................... 253 TABLE 35 - E1XC ORDERING INFORMATION ............................................ 254 TABLE 36 - E1XC THERMAL INFORMATION............................................... 254 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER xiii ...
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... DATA SHEET PMC-910419 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER xiv ...
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... CRC-4 errors to 1000 per second; Far end block errors to 1000 per second; Frame sync errors to 127 per second; and Line code violations to 8191 per second. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 1 ...
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... Optionally accepts dual rail digital PCM inputs to allow BPV transparency. Also supports unframed mode. Provides channel associated signalling insertion, programmable idle code substitution, digital milliwatt code substitution, and data inversion on a per timeslot basis. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 2 ...
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... Provides analog circuitry for transmitting a G.703 compatible 2048 kbit/s signal programmable line build out is provided. Provides dual rail or single rail digital PCM output signals. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 coaxial line or a 120 symmetrical line. PM6341 E1XC E1 FRAMER/TRANSCEIVER Digitally 3 ...
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... Electronic Cross-Connect Systems (EDSX) E1 & E3 Test Equipment (TEST) ISDN Primary Rate Interfaces (PRI) E1 Channel Service Units (CSU) and Data Service Units (DSU) SONET/SDH Add/Drop Multiplexers (ADM) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 4 ...
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... ITU-T Recommendation Q.516, - "Operations and maintenance functions", Vol. VI, Fascicle VI.5, 1984. 13. Transmission and Multiplexing (TM); Generic Functional Requirements for SDH Transmission Equipment, Part 1: Generic Processes and Performance", ETSI DE/TM-1015, November, 1993, Version 1.0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 5 ...
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... DATA SHEET PMC-910419 14. American National Standard for Telecommunications, ANSI T1.102-1992 - "Digital Hierarchy - Electrical Interfaces". PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 6 ...
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... Interface for PDH (S/UNI-PDH™) to implement an ATM wide area User Network Interface (UNI) or Network Node Interface (NNI). In this example, the E1 LIU and framing functions are provided by the PM6341 E1XC. The combination of the E1XC with the S/UNI-PDH allows both PLCP formatted E1 signals and ITU-T G.804 compliant E1 signals to be processed. ...
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... DATA SHEET PMC-910419 Figure 2 - DS0 Cross-connect M T 8980 6341 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6341 PM6341 E1XC E1 FRAMER/TRANSCEIVER 8 ...
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... DATA SHEET PMC-910419 Figure application utilizing 4 PM6341 E1XC chips and a Mitel MT8980 Digital Time/Space Switch to implement a simple DS0 cross-connect. An alternate architecture could use two MT8980, one as a voice switch and the other as a signalling switch, and 8 E1XCs to cross-connect 8 E1's. ( Note: a true implementation would require redundancy in the switch core.) The " ...
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... Perform ance Elas tic M onitor Store C ounters FRM R Fram er: Fram Alignm ent, Alarm D ata D etection PM6341 E1XC E1 FRAMER/TRANSCEIVER Analog Pulse G enerator igital TD P /TD D Tra nsm it ...
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... DATA SHEET PMC-910419 6 DESCRIPTION The PM6341 E1 Framer/Transceiver (E1XC feature-rich device suitable for use in many E1 systems (such as CSU, DSU, CH BANK, MUX, DPBX, DACS, and ESDX) with a minimum of external circuitry. The E1XC is software configurable, allowing feature selection without changes to external wiring. On the receive side, the E1XC recovers clock and data and can be configured to frame to a basic G ...
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... PCM interface that allows 2048 kbit/s backplanes to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 12 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM6341 (TOP VIEW) PM6341 E1XC E1 FRAMER/TRANSCEIVER 60 VSSO[ TAP 57 RAVD 56 ...
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... VSSI[0] 10 VDDI[0] 11 VDDO[1] 12 D[4] 13 D[5] 14 D[6] 15 D[7] 16 RDB 17 WRB PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 (TOP VIEW) PM6341 E1XC E1 FRAMER/TRANSCEIVER VSSO[ TAP 55 RAVD 54 RAVS 53 RAS 52 RRC 51 REF 50 VSSI[1] 49 VDDI[1] 48 RCLKI ...
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... The RDN input can be enabled for either RZ or NRZ waveforms. When enabled for NRZ, this input may be enabled to be sampled on the rising or falling edge of RCLKI. When enabled for RZ, clock is recovered from the RDP and RDN inputs. PM6341 E1XC E1 FRAMER/TRANSCEIVER 15 ...
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... Receive Reference (REF). This analog bidirectional pin provides DC bias to an external isolation transformer connected to the negative lead of the transformer secondary and to a decoupling capacitor to RAVS. PM6341 E1XC E1 FRAMER/TRANSCEIVER 16 ...
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... RAVS must be connected to a common ground together with the VSSO[3:0] and VSSI[1:0] pins. Care must be taken to avoid coupling noise induced on the VSSO and VSSI pins into the RAVS pin. PM6341 E1XC E1 FRAMER/TRANSCEIVER 17 ...
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... RDIEN = 1), since the data should be available at the RDD input. Recovered PCM (RPCM). This output is available when the E1XC is configured for raw data output. This NRZ output signal is the recovered data stream without optional HDB3 decoding applied updated on the falling edge of RCLKO. PM6341 E1XC E1 FRAMER/TRANSCEIVER 18 ...
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... RCLKO cycle during bit 1 of frame 1 of every 16 frame CRC multiframe, indicating the CRC multiframe alignment of the RDPCM data stream. (Even when CRC multiframing is disabled, the RFP output continues to indicate the position of bit 1 of the FAS frame every 16 PM6341 E1XC E1 FRAMER/TRANSCEIVER th frame.) 19 ...
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... RFP will pulse high for 1 RCLKO cycle every 16 frames. RFP does not indicate the frame or multiframe alignment of RDPCM when the digital receive interface is configured for unipolar operation (RUNI = 1 and RDIEN = 1 in register 03H.) RFP is updated on the falling edge of RCLKO. PM6341 E1XC E1 FRAMER/TRANSCEIVER 20 ...
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... RDLSIG. Receive Data Link End of Message (RDLEOM). The RDLEOM signal is available on this output when RFDL is enabled. RDLEOM goes high when the last byte of a received sequence is read from the RFDL FIFO buffer, or when the FIFO buffer is overrun. PM6341 E1XC E1 FRAMER/TRANSCEIVER 21 ...
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... Pulse (BRDP). The BRDP signal is available on this output when the backplane is configured for dual-rail output. The BRDP NRZ output represents the RZ receive digital positive pulse signal extracted from the input bipolar signal. BRDP is updated on the falling edge of RCLKO. PM6341 E1XC E1 FRAMER/TRANSCEIVER 22 ...
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... Pulse (BRDN). The BRDN signal is available on this output when the backplane is configured for dual-rail output. The BRDN NRZ output represents the RZ receive digital negative pulse signal extracted from the input bipolar signal. BRDN is updated on the falling edge of RCLKO. PM6341 E1XC E1 FRAMER/TRANSCEIVER 23 ...
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... CRC multiframe, indicating the CRC multiframe alignment of the BRPCM data stream. (Even when CRC multiframing is disabled, the BRFPO output continues to indicate the position of bit 1 of the FAS frame every 16 PM6341 E1XC E1 FRAMER/TRANSCEIVER th frame.) th frame.) 24 ...
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... BRFPO will pulse high for 1 clock cycle. When configured for backplane receive overhead output, BRFPO is high for timeslot 0 and timeslot 16 of each 256-bit frame, indicating the overhead bit positions of the BRPCM data stream. BRFPO is updated on the falling edge of BRCLK or RCLKO. PM6341 E1XC E1 FRAMER/TRANSCEIVER 25 ...
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... BTCLK. Backplane Transmit Positive Line Pulse (BTDP). When the backplane is configured for dual-rail input, the BTDP input by-passes the transmitter and is fed directly into the DJAT. BTDP is sampled on the rising edge of BTCLK. PM6341 E1XC E1 FRAMER/TRANSCEIVER 26 ...
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... BTSIG is sampled on the rising edge of BTCLK. Backplane Transmit Negative Line Pulse (BTDN). When the backplane is configured for dual-rail input, the BTDN input by-passes the transmitter and is fed directly into the DJAT. BTDN is sampled on the rising edge of BTCLK. PM6341 E1XC E1 FRAMER/TRANSCEIVER 27 ...
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... BTCLK cycle every 16 frames Backplane Transmit Clock (BTCLK). This clock should be 2.048MHz with optional gapping for adaptation from non-uniform backplane data streams. The E1XC may be configured to ignore the BTCLK input and use the RCLKO signal in its place. PM6341 E1XC E1 FRAMER/TRANSCEIVER 28 ...
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... The TDLINT signal is output on this pin when XFDL is enabled. TDLINT goes high when the last data byte written to the XFDL has been set up for transmission and processor intervention is required to either write control information to end the message provide more data. PM6341 E1XC E1 FRAMER/TRANSCEIVER 29 ...
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... TCLKO. TCLKO is a 2.048 MHz clock that is adequately jitter and wander free in absolute terms to permit an acceptable G.703 2048 kbit/s signal to be generated. Depending on the configuration of the E1XC, TCLKO may be derived from TCLKI, RCLKO, or BTCLK, with or without jitter attenuation. PM6341 E1XC E1 FRAMER/TRANSCEIVER 30 ...
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... The TFLG output indicates when the transmit rate conversion FIFO in DJAT is nearing an empty or a full condition. Either indication may be selected. This output may be enabled to be updated on the rising or falling edge of TCLKO. PM6341 E1XC E1 FRAMER/TRANSCEIVER 31 ...
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... An analog Transmit Monitor Negative point is internally bonded to this output and is used to monitor the negative pulses on the transmit line Transmit Reference Decoupling Capacitor (TC). This analog bidirectional provides decoupling for an internal reference generator connected to a decoupling capacitor to TAVD. PM6341 E1XC E1 FRAMER/TRANSCEIVER 32 ...
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... TAVS must be connected to a common ground together with the VSSO[3:0] and VSSI[1:0] pins. Care must be taken to avoid coupling noise induced on the VSSO and VSSI pins into the TAVS pin. PM6341 E1XC E1 FRAMER/TRANSCEIVER 33 ...
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... XCLK may be driven with a 16.384 MHz clock. When transmit clock generation or jitter attenuation are required, XCLK must be driven with a 49.152 MHz clock. Vector Clock (VCLK). The VCLK signal is used during E1XC production test to verify internal functionality. PM6341 E1XC E1 FRAMER/TRANSCEIVER 34 ...
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... RSTB input. In any case, CSB must be high at least once after a powerup in order to clear internal test modes Bidirectional data bus (D[7:0]). This bus is used during E1XC read and 6 14 write accesses PM6341 E1XC E1 FRAMER/TRANSCEIVER 35 ...
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... When ALE is high, the address latches are transparent Active low reset (RSTB). This signal asynchronously resets the E1XC Address bus (A[7:0]). This bus selects specific registers during E1XC register 23 28 accesses PM6341 E1XC E1 FRAMER/TRANSCEIVER 36 ...
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... These power supply connections must all be utilized and must all connect to a common + ground rail, as appropriate. There is no low impedance connection within the PM6341 between the core, pad ring, and transmit analog supply rails. Failure to properly make these connections may result in improper operation or damage to the device ...
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... V or ground rail, as appropriate, with the core, pad ring, and transmit analog supply rails. There is no low impedance connection within the PM6341 between the receive analog supply rail and other supply rails. When the receive analog function is not desired, RAVD should be connected to RAVS ...
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... G.703 75 attenuator pad (see Figure 5). The following network values are recommended for the two intended applications: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 coax. The RSLC block is configured via an off-chip PM6341 E1XC E1 FRAMER/TRANSCEIVER 39 ...
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... Analog Pulse Slicer" in the "Operation" section of this databook. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE ± 1%) ( ± 1%) 357 121 205 95.3 PM6341 E1XC E1 FRAMER/TRANSCEIVER Squelch Level on the Primary 276 mV ± 20% 220 mV ± 20% 40 ...
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... BH Electronics 500-1775 (1:1:1); Pulse Engineering PE 64931 (1:1:1); or Pulse Engineering PE 65341 (1:1:1) (for extended temp range) BH Electronics 500-1777; Pulse Engineering PE64952; or Pulse Engineering PE65774 (for extended temp range) PM6341 E1XC E1 FRAMER/TRANSCEIVER V DD RAVD RAS (Zin = 10k ± 10%) REF RRC RAVS ...
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... If AMI line code is selected, all bipolar violations are counted as line code violations. The input jitter tolerance of CDRC complies with ITU-T Recommendation G.823. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 42 ...
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... Max t o lerance c eiling MHz BRCLK - lim ram e slip er. IN SPEC REGION REC. G823 JITTER TOLERANCE SPECIFICATION 2.0 2 PM6341 E1XC E1 FRAMER/TRANSCEIVER DPLL TOLERANCE WITH 14 ZEROS RESTRICTION (ALGSEL=0) DPLL TOLERANCE WITH 25% ONES DENSITY (ALGSEL=0) 25% ONES DENSITY (ALGSEL=1) 1.8 ...
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... Search for the presence of the correct 7-bit FAS; 2. Check that the FAS is absent in the following frame by verifying that bit 2 of the assumed timeslot 0 byte is a logic 1; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 44 ...
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... These algorithms are illustrated in Figure 7. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 15 -1 pseudo 45 ...
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... Check bit 2 =1 Frame alignment in following established frame Bit 2=1 check occurrence of 7-bit FAS in next frame FAS Found Frame alignment established PM6341 E1XC E1 FRAMER/TRANSCEIVER not found Algorithm #2: Bit 2 =0 Wait for byte location in next frame Algorithm #2: Bit 2 =0 FAS Found & No Check Sequence ...
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... The CRC Frame Find Block will force the Frame Find Block to initiate a basic frame search when CRC multiframe alignment has not been found for 8 ms. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER -3 bit error rate and -3 bit error rate ...
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... CAS multiframe. The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe alignment signals have been received in error, or PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER -3 bit 48 ...
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... RED Alarm declaration is removed when the counter reaches 0. This algorithm biases OOF occurrences, leading to declaration of red alarm when intermittent loss of frame alignment occurs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER -3 mean bit error 49 ...
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... When the internal HDLC receiver is disabled, the serial data extracted by the FRMR TSB is output on the RDLSIG pin updated on the falling clock edge of the RDLCLK pin. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 50 ...
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... The SIGX selectively debounces the bits, and serializes the results onto the 2048 kbit/s serial stream BRSIG output. Buffered signalling data is aligned with its associated voice PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 51 ...
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... Configuration Register. Common Channel Signalling (CCS) is supported in time slot 16 either through the internal HDLC Transmitter (XFDL) or through a serial data input and clock PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 52 ...
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... CRC word (if CRC insertion has been enabled flag (if CRC insertion has not been enabled) is transmitted. The XFDL then returns to the transmission of flag characters. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 53 ...
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... BTCLK or RCLKO), DJAT will track the jitter of the input clock. This permits the phase jitter to pass through unattenuated, inhibiting the loss of data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 54 ...
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... Hz UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK divided by 24 and that of the input data clock. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 55 ...
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... MHz, the minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK/24 are shown in Figure 9. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 CCITT G.823 unacceptable Region 100 Jitter Frequency, Hz PM6341 E1XC E1 FRAMER/TRANSCEIVER 35 DJAT minimum tolerance acceptable 0.2 10k 100k ...
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... The output jitter for jitter frequencies from more than 0.1 dB greater than the input jitter, excluding residual jitter. Jitter frequencies above 8.8 Hz are attenuated at a level per octave, as shown in Figure 10. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 200 49 PM6341 E1XC E1 FRAMER/TRANSCEIVER 42.4 39 34.9 300 308 Hz 100 ± ...
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... DJAT block, the reference signal for the digital PLL, and the clock source used to derive the output TCLKO signal. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 G.737, G738, G.739, G.742 max DJAT response 100 1k 40 Jitter Frequency, Hz PM6341 E1XC E1 FRAMER/TRANSCEIVER Unacceptable Region -1 9.5 10k 58 ...
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... The drivers, with the step-up transformer, amplify the output pulses to their final levels. The TIP and RING drivers also supply the high current capability required to drive the low impedance output load. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 59 ...
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... TAIS bit is programmed high. This is useful when the internal loopback modes are used. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 symmetrical line. A separate build out is PM6341 E1XC E1 FRAMER/TRANSCEIVER 60 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 optional 470nF ± 10% "snubbing netw ork" 0.68µ F ± 20% , 50V 47½ ± 10% 1nF ± 10 .703 Zo=120½ 1=2.7½ +/-5% , 1/8W G .703 Zo= 75½ 1=6.2½ +/-5% , 1/8W PM6341 E1XC E1 FRAMER/TRANSCEIVER T R 1:1 ...
Page 78
... E1XC Phase Status Word (MSB) CDRC block Configuration CDRC block Interrupt Enable CDRC block Interrupt Status Alternate Loss of Signal XPLS block Line Length Configuration XPLS block Control/Status XPLS block CODE Indirect Address XPLS block CODE Indirect Data DJAT block Interrupt Status PM6341 E1XC E1 FRAMER/TRANSCEIVER 62 ...
Page 79
... FRMR block CRC Error Count - LSB FRMR block CRC Error Count - MSB TS16 AIS Alarm Status Reserved TPSC block Configuration TPSC block µP Access Status TPSC block Timeslot Indirect Address/Control TPSC block Timeslot Indirect Data Buffer XFDL block Configuration XFDL block Interrupt Status PM6341 E1XC E1 FRAMER/TRANSCEIVER 63 ...
Page 80
... PMON block FEBE Count (LSB) PMON block FEBE Count (MSB) PMON block CRC Count (LSB) PMON block CRC Count (MSB) PMON block LCV Count (LSB) PMON block LCV Count (MSB) Reserved RSLC block Configuration RSLC block Interrupt Enable/Status PM6341 E1XC E1 FRAMER/TRANSCEIVER 64 ...
Page 81
... Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect E1XC operation unless otherwise noted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 65 ...
Page 82
... The TRSLIP bit allows the ELST block to be used to measure, through SLIP indications, the frequency difference between the recovered receive line clock PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default WORDERR 0 CNTNFAS 0 ELSTBYP 0 TRSLIP 0 SRPCM 0 SRSMFP 0 SRCMFP 0 TRKEN 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 66 ...
Page 83
... RFP pulses high for 1 RCLKO cycle during bit 1 of frame 1 of the 16 frame signalling multiframe, indicating the signalling multiframe alignment of the RDPCM/RPCM data stream. (Even when signalling multiframing is disabled, the RFP output continues to indicate the position of bit every 16 frame.) PM6341 E1XC E1 FRAMER/TRANSCEIVER th frame.) 67 ...
Page 84
... CRC multiframe alignment of the RPCM/RDPCM data stream. This mode allows both multiframe alignments to be decoded externally from the single RFP signal. Note that if the signalling and CRC multiframe alignments are coincident, RFP will pulse high for 1 RCLKO cycle every 16 frames. PM6341 E1XC E1 FRAMER/TRANSCEIVER 68 ...
Page 85
... The ROHM, BRXSMFP and BRXCMFP bits select the output signal seen on the backplane output BRFPO. The following table summarizes the configurations: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X RXDMAGAT 0 ROHM 0 BRX2RAIL 0 BRXSMFP 0 BRXCMFP 0 Unused X PM6341 E1XC E1 FRAMER/TRANSCEIVER 69 ...
Page 86
... RCLKO cycle if ELST is by-passed) during bit 1 of frame 1 of the 16 frame signalling multiframe, indicating the signalling multiframe alignment of the BRPCM data stream. (Even when signalling multiframing is disabled, the BRFPO output continues to indicate the position of bit 1 of every 16 PM6341 E1XC E1 FRAMER/TRANSCEIVER th frame). th frame.) 70 ...
Page 87
... BRFPO will pulse high for 1 BRCLK cycle (or RCLKO cycle if ELST is by- passed) every 16 frames Backplane receive overhead output: BRFPO is high for timeslot 0 and timeslot 16 of each 256-bit frame, indicating the overhead of the BRPCM data stream. PM6341 E1XC E1 FRAMER/TRANSCEIVER 71 ...
Page 88
... Time Slot 16 or the Time Slot 0 National Use bits. If the TRAN block Configuration DLEN bit is logic 1 and the TRAN block Configuration SIGEN PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RXDMASIG 0 Unused X TXDMASIG 0 Unused X RDLINTE 0 RDLEOME 0 TDLINTE 0 TDLUDRE 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 72 ...
Page 89
... When TDLINTE is set to logic 0, an interrupt event in the XFDL does not cause an interrupt on INTB. TDLUDRE: The TDLUDRE bit enables the XFDL transmit data underrun interrupt to also generate an interrupt on the microprocessor interrupt, INTB. This allows a PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 73 ...
Page 90
... INTB output. When TDLUDRE is set to logic 0, an underrun event in the XFDL does not cause an interrupt on INTB. Upon reset of the E1XC, these bits are cleared to zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 74 ...
Page 91
... The RDPINV and RDNINV bits enable the Receive Interface to logically invert the signals received on multifunction pins SDP/RDP/RDD and PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X SDOEN 0 RDIEN 0 RDNINV 0 RDPINV 0 RUNI 0 RFALL 0 Unused X PM6341 E1XC E1 FRAMER/TRANSCEIVER 75 ...
Page 92
... RDD and RLCV inputs, or the RDP and RDN inputs, on the falling RCLKI edge. When RFALL is set to logic 0, the interface is enabled to sample the inputs on the rising RCLKI edge. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 76 ...
Page 93
... The transition to transmitting AIS on the TDP and TDN outputs is done in such a way as to not introduce any bipolar violations. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default FIFOBYP 0 TAISEN 0 TDNINV 0 TDPINV 0 TUNI 0 FIFOFULL 0 TRISE 0 TRZ 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 77 ...
Page 94
... TDP and TDN output signals as NRZ waveforms with duration equal to the TCLKO period, updated on the selected edge of TCLKO. The TRZ bit can only be used when TUNI and TRISE are set to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 78 ...
Page 95
... When the system is reset, the contents of the register are set to logic 0, enabling the Transmit Interface to output NRZ formatted positive and negative pulse data on the TDP and TDN outputs, updated on the falling TCLKO edge. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 79 ...
Page 96
... CRC multiframe. This mode allows both multiframe alignments to be PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X BTXCLK 0 Unused X BTX2RAIL 0 BTXMFP 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 80 ...
Page 97
... BTCLK cycle at a multiple of 16 frames. When BTXMFP is set to logic 0, a rising edge on the BTFP indicates the first bit in each frame. Upon reset of the E1XC, these bits are cleared to zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 81 ...
Page 98
... TDLSIG value is written into bit 8 of Time Slot 0 of non-frame alignment signal frames. The other enable bits operate in an analogous fashion. A clock pulse PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default PATHCRC 0 Unused X Unused X TXSA4EN 1 TXSA5EN 0 TXSA6EN 0 TXSA7EN 0 TXSA8EN 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 82 ...
Page 99
... International/National Control register. Upon reset of the E1XC, all bits are logic 0 except TXSA4EN. By default kbit/s data link is inserted into Sa4 from the TDLSIG input. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 83 ...
Page 100
... When OCLKSEL1 is set to logic 0, the DJAT FIFO output clock is driven with PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default HSBPSEL 0 XCLKSEL 0 OCLKSEL1 0 OCLKSEL0 0 PLLREF1 0 PLLREF0 0 TCLKISEL 0 SMCLKO 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 84 ...
Page 101
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 0 Transmit clock used by TRAN ( either the 2.048MHz BTCLK or the 2.048MHz RCLKO, as selected by BTXCLK) 1 BTCLK input 0 RCLKO output 1 TCLKI input PM6341 E1XC E1 FRAMER/TRANSCEIVER 85 ...
Page 102
... PM6341 E1XC E1 FRAMER/TRANSCEIVER Effect on Output Transmit Data Jitter attenuated. TCLKO is a smooth 2.048 MHz. TCLKO referenced to BTCLK. TCLKO referenced to RCLKO. TCLKO referenced to TCLKI. Jitter attenuated. TCLKO is a smooth 2.048MHz. TCLKO ...
Page 103
... PM6341 E1XC E1 FRAMER/TRANSCEIVER Effect on Output Transmit Data No jitter attenuation. TCLKO is equal to internal transmit clock, either BTCLK, gapped BTCLK, or RCLKO. Same as above. These modes are only compatible with the digital transmit outputs. Do not use the ...
Page 104
... ISSUE 8 XCLK Freq =0 49.152MHz = 16.384MHz =0 jitter-free 16.384MHz = PM6341 E1XC E1 FRAMER/TRANSCEIVER Effect on Output Transmit Data TCLKI is a jitter- free 16.384MHz clock. TCLKO is equal to TCLKI÷8. Same as above. XCLK is a jitter- free 16.384MHz clock. TCLKO is equal to XCLK÷8. 88 ...
Page 105
... rence fo r Jitte r A tten . LKSE PM6341 E1XC E1 FRAMER/TRANSCEIVER FIF O ou tpu data clo LKSEL1 EL0 "Jitter-free" 1 2.0 48M LKO 0 " ...
Page 106
... Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default DJAT X RSLC X FRMR/SA X XPLS X ELST X RFDL X XFDL X CDRC X PM6341 E1XC E1 FRAMER/TRANSCEIVER 90 ...
Page 107
... RDLCLK for each enable that is logic 1. Any combination enable bits is allowed resulting in a data rate between 4 kbit/s and 20 kbit/s. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X SACE 0 SACI X RXSA4EN 1 RXSA5EN 0 RXSA6EN 0 RXSA7EN 0 RXSA8EN 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 91 ...
Page 108
... Upon reset of the E1XC, all bits are logic 0 except RXSA4EN. By default kbit/s data link is extracted from Sa4 and presented on the RDLSIG output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 92 ...
Page 109
... RZ pulse outputs from DJAT are internally connected to the receive positive and negative pulse inputs of CDRC. When DDLB is set to PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X PAYLB 0 LINELB 0 DMLB 0 DDLB 0 Unused X Unused X PM6341 E1XC E1 FRAMER/TRANSCEIVER 93 ...
Page 110
... When DMLB is set to logic 0, the diagnostic metallic loopback mode is disabled. Upon reset of the E1XC, these register bits are cleared to zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 94 ...
Page 111
... When IOTST is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X PMCTST 0 DBCTRL 0 IOTST 0 HIZDATA 0 HIZIO 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 95 ...
Page 112
... The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is also held in a high- impedance state which inhibits microprocessor read cycles. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 96 ...
Page 113
... E1XC. ID[6:0] = 0000000 binary indicates the E1XC rev A. ID[6:0] = 0000001 binary indicates the E1XC rev B. The chip identification bit, TYPE, is set to logic 1 representing the E1XC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default TYPE 1 ID[6] 0 ID[5] 0 ID[4] 0 ID[3] 0 ID[2] 0 ID[1] 0 ID[0] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 97 ...
Page 114
... A hardware reset clears the RESET bit, thus deasserting the software reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X RESET 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 98 ...
Page 115
... PSB[8] is toggled only under the following conditions (all other bit value transitions leave PSB[8] unchanged): PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default PSB[7] X PSB[6] X PSB[5] X PSB[4] X PSB[3] X PSB[2] X PSB[1] X PSB[0] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 99 ...
Page 116
... LSB register because, once the Phase Status Word (LSB) register has been read, the phase status word counter is unfrozen and the contents may change immediately. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Current PSB[7:6] Effect on PSB[8] 11 toggle 00 toggle PM6341 E1XC E1 FRAMER/TRANSCEIVER 100 ...
Page 117
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X PSB[8] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 101 ...
Page 118
... RCLKI instead of being recovered from the RDP and RDN inputs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default AMI 0 LOS1 0 LOS0 0 DCR 0 Reserved 0 ALGSEL 0 O162 0 Unused X LOS0 Threshold (PCM periods 175 PM6341 E1XC E1 FRAMER/TRANSCEIVER 102 ...
Page 119
... If O162 is a logic 1, a line code violation is indicated if a bipolar violation is of the same polarity as the last bipolar violation, as per ITU-T Recommendation O.162. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 103 ...
Page 120
... When the E1XC is reset, Z4DE, HDB3E, LOSE, and LCVE bits are set to logic 0, disabling any interrupt generation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default LCVE 0 LOSE 0 HDB3E 0 Z4DE 0 Unused X Unused X Unused X Unused X PM6341 E1XC E1 FRAMER/TRANSCEIVER 104 ...
Page 121
... Z4DI: The Z4DI bit is set high if four consecutive spaces occur. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default LCVI X LOSI X HDB3I X Z4DI X Unused X Unused X Unused X LOS X PM6341 E1XC E1 FRAMER/TRANSCEIVER 105 ...
Page 122
... The LOS bit is the loss of signal status logic 1 if the number of consecutive spaces exceeds the programmed threshold. The status is deasserted upon the reception of a single mark. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 106 ...
Page 123
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default ALTLOSE 0 ALTLOSI X Unused X Unused X Unused X Unused X Unused X ALTLOS X PM6341 E1XC E1 FRAMER/TRANSCEIVER 107 ...
Page 124
... When SM is set to logic 0, the ILS[2:0] bits are ignored and the default G.703 120 is selected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RPT ILS[2] 0 ILS[1] 0 ILS[0] 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER waveform template 108 ...
Page 125
... The eight available templates are selected via the following values of ILS[2:0]: ILS[2:0] Build-out 000 Reserved 001 Reserved 011 Reserved 010 Reserved 110 Reserved 111 Reserved 101 G.703 75 100 G.703 120 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 109 ...
Page 126
... TAN or TAN output pins occurs. When DPME is set to logic 0, detection of a driver performance monitor alarm condition is disabled from generating an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X TAIS 0 DPMV X DPMI X DPME 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 110 ...
Page 127
... Unused X Unused X CRA2 0 CRA1 0 CRA0 0 CRA0 Internal Code Register 0 CODE register #0 - first code applied 1 CODE register #1 0 CODE register #2 1 CODE register #3 0 CODE register #4 1 CODE register #5 0 CODE register #6 1 CODE register #7 - last code applied PM6341 E1XC E1 FRAMER/TRANSCEIVER 111 ...
Page 128
... DATA SHEET PMC-910419 See the Operation section for more details on setting up custom waveform templates. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 112 ...
Page 129
... CRD[3:0] bits. CRD3 is the most significant bit. See the Operation section for more details on setting up custom waveform templates. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X CRD3 0 CRD2 0 CRD1 0 CRD0 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 113 ...
Page 130
... FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X OVRI X UNDI X PM6341 E1XC E1 FRAMER/TRANSCEIVER 114 ...
Page 131
... Upon reset of the E1XC, the default value set to decimal 47 (2FH). Consult the Operations section for clarification of divisor selection criteria. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default N1[7] 0 N1[6] 0 N1[5] 1 N1[4] 0 N1[3] 1 N1[2] 1 N1[1] 1 N1[0] 1 PM6341 E1XC E1 FRAMER/TRANSCEIVER 115 ...
Page 132
... Upon reset of the E1XC, the default value set to decimal 47 (2FH). Consult the Operations section for clarification of divisor selection criteria. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default N2[7] 0 N2[6] 0 N2[5] 1 N2[4] 0 N2[3] 1 N2[2] 1 N2[1] 1 N2[0] 1 PM6341 E1XC E1 FRAMER/TRANSCEIVER 116 ...
Page 133
... EMPTY or FULL alarm conditions. CENT can only be set to logic 1 if SYNC is logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X WIDEN 1 CENT 0 UNDE 0 OVRE 0 SYNC 1 LIMIT 1 PM6341 E1XC E1 FRAMER/TRANSCEIVER 117 ...
Page 134
... When LIMIT is set to logic 0, the PLL is allowed to operate normally. Upon reset of the E1XC, the LIMIT and SYNC bits are set to logic 1, and the OVRE, UNDE, and CENT bits are set to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 118 ...
Page 135
... E1 frame format output from the ELST. SETTING OR TO LOGIC RESERVED SETTING AND SHOULD NOT BE USED. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default ACCEL 0 Unused X Unused X Unused X Unused X Unused PM6341 E1XC E1 FRAMER/TRANSCEIVER 119 ...
Page 136
... The SLIPI bit is set if a slip occurred since the last read of the Interrupt Status register. The SLIPI bit is cleared just after the Interrupt Status register read operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X SLIPE 0 SLIPD X SLIPI X PM6341 E1XC E1 FRAMER/TRANSCEIVER 120 ...
Page 137
... One timeslot of idle code data will be corrupted if the register is written to when the framer is out of frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default PM6341 E1XC E1 FRAMER/TRANSCEIVER 121 ...
Page 138
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default CRCEN 0 CASDIS 0 AFAA 0 CHKSEQ 0 CASA 0 REFR 0 REFCRCE 0 REFRDIS 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 122 ...
Page 139
... REFR bit. A logic 1 in the REFRDIS bit position causes the FRMR to remain "locked in frame" once initial frame alignment has been found. A logic 0 allows reframing to occur based on the various error criteria (FER, excessive CRC errors, etc.). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 123 ...
Page 140
... T16C. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default FASC 0 BIT2C 0 SMFASC 0 T16C 0 RADEB 0 RMADEB 0 CMFACT X EXCRCE X PM6341 E1XC E1 FRAMER/TRANSCEIVER 124 ...
Page 141
... REFCRCE bit of the Frame Alignment Options register. The EXCRCE bit is reset to logic 0 after the register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 125 ...
Page 142
... A logic one in the CMFERE bit enables the generation of an interrupt when an error has been detected in the CRC multiframe alignment signal. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X OOFE 0 OOSMFE 0 OOCMFE 0 COFAE 0 FERE 0 SMFERE 0 CMFERE 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 126 ...
Page 143
... When the CRCEE bit is a logic one, an interrupt is generated when calculated CRC differs from the received CRC remainder. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RRAE 0 RRMAE 0 AISDE 0 T16AISDE 0 REDE 0 AISE 0 FEBEE 0 CRCEE 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 127 ...
Page 144
... Framing Status outputs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X OOFI X OOSMFI X OOCMFI X COFAI X FERI X SMFERI X CMFERI X PM6341 E1XC E1 FRAMER/TRANSCEIVER 128 ...
Page 145
... Maintenance/Alarm Status events. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RRAI X RRMAI X AISDI X T16AISDI X REDI X AISI X FEBEI X CRCEI X PM6341 E1XC E1 FRAMER/TRANSCEIVER 129 ...
Page 146
... The OOCMF bit is a logic one when the CRC multiframe alignment has been lost. The OOCMF bit becomes a logic zero once CRC multiframe has been regained. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X OOF X OOSMF X OOCMF X Unused X Unused X Unused X Unused X PM6341 E1XC E1 FRAMER/TRANSCEIVER 130 ...
Page 147
... The T16AISD is a logic one after an all-ones byte has been detected in time slot 16 for 2 consecutive frames while out of signalling multiframe alignment. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RRA X RRMA X AISD X T16AISD X RED X AIS X Unused X Unused X PM6341 E1XC E1 FRAMER/TRANSCEIVER 131 ...
Page 148
... The AIS bit is a logic one when an out of frame all-ones condition has persisted for 100 ms. The AIS bit returns to a logic zero when the AIS condition has been absent for 100 ms. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 132 ...
Page 149
... National Use Bits. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Si1 X Si0 X RAWRA X Sn0 X Sn1 X Sn2 X Sn3 X Sn4 X Bit Position Sn0 Sn1 RAWRA PM6341 E1XC E1 FRAMER/TRANSCEIVER Sn2 Sn3 Sn4 133 ...
Page 150
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused RAWRMA PM6341 E1XC E1 FRAMER/TRANSCEIVER 134 ...
Page 151
... This register contains the least significant byte of the 10-bit CRC error counter value, updated every second. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default CRCE7 X CRCE6 X CRCE5 X CRCE4 X CRCE3 X CRCE2 X CRCE1 X CRCE0 X PM6341 E1XC E1 FRAMER/TRANSCEIVER 135 ...
Page 152
... CRC error in one second; whereas, PMON relies on externally initiated transfers which may not be one second apart. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default OVR X NEWDATA X Unused X Unused X Unused X Unused X CRCE9 X CRCE8 X PM6341 E1XC E1 FRAMER/TRANSCEIVER 136 ...
Page 153
... The bit returns to a logic zero when the time slot 16 AIS condition has been absent for 3 ms. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X TS16AISE 0 TS16AISI X TS16AIS X Unused X Unused X Unused X Unused X PM6341 E1XC E1 FRAMER/TRANSCEIVER -3 mean bit error 137 ...
Page 154
... TRAN block. When the PCCE bit is set to logic 0, the per- timeslot functions are disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X IND 0 PCCE 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 138 ...
Page 155
... Status Register should be polled until the BUSY bit goes low before another µP access request is initiated. A µP access request is typically completed within 480 ns. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default BUSY X Unused X Unused X Unused X Unused X Unused X Unused X Unused X PM6341 E1XC E1 FRAMER/TRANSCEIVER 139 ...
Page 156
... R/WB is set to a logic 0, an write to the internal TPSC register is requested. The reserved bit must be set to 0 for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default R/ PM6341 E1XC E1 FRAMER/TRANSCEIVER 140 ...
Page 157
... Data Control byte for Time Slot 2 • • • • • • 3EH Data Control byte for Time Slot 30 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default PM6341 E1XC E1 FRAMER/TRANSCEIVER 141 ...
Page 158
... IDLE Code byte for Time Slot 30 5FH IDLE Code byte for Time Slot 31 The bits within each control byte are allocated as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 142 ...
Page 159
... ADI - data inversion on timeslot bits 2,4,6,8 1 INV - data inversion on all timeslot bits X Data substitution on - IDLE code replaces PCM timeslot data 0 Data substitution on - A-Law digital milliwatt pattern * replaces TPCM timeslot data. 1 Data substitution on - µ-Law digital milliwatt pattern * replaces TPCM timeslot data. PM6341 E1XC E1 FRAMER/TRANSCEIVER 143 ...
Page 160
... Bit 3 Bit 4 Bit PM6341 E1XC E1 FRAMER/TRANSCEIVER Bit 6 Bit 7 Bit Bit 6 Bit 7 Bit ...
Page 161
... DS[0] bit in the PCM Control Byte is set to a logic 0. The IDLE Code is transmitted from MSB (bit 7) to LSB (bit 0). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function IDLE7 IDLE6 IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 145 ...
Page 162
... Datalink Options register, the interrupt generated on the TDLINT output is also generated on the microprocessor INTB pin. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X EOM 0 INTE 0 ABT 0 CRC PM6341 E1XC E1 FRAMER/TRANSCEIVER 146 ...
Page 163
... FCS word is appended to the last data byte transmitted and a continuous stream of flags is generated. The EOM bit is automatically cleared before transmission of the next data packet begins. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 147 ...
Page 164
... The UDR bit can only be cleared by writing a logic 0 to the UDR bit position in this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X INT X UDR 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 148 ...
Page 165
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default TD7 X TD6 X TD5 X TD4 X TD3 X TD2 X TD1 X TD0 X PM6341 E1XC E1 FRAMER/TRANSCEIVER 149 ...
Page 166
... EN bit, therefore, the RFDL state machine will begin searching for flags and an interrupt will be generated when the first flag is detected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused PM6341 E1XC E1 FRAMER/TRANSCEIVER 150 ...
Page 167
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X INTC1 0 INTC0 0 INT 0 Description Disable interrupts (All sources) Enable interrupt when FIFO receives data Enable interrupt when FIFO has 2 bytes of data Enable interrupt when FIFO has 3 bytes of data PM6341 E1XC E1 FRAMER/TRANSCEIVER 151 ...
Page 168
... DATA SHEET PMC-910419 The contents of the Enable/Status register should only be changed when the RFDL block is disabled to prevent any erroneous interrupt generation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 152 ...
Page 169
... FLG bit is logic 1. EOM: The End of Message bit (EOM) follows the RDLEOM output set when: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default FE X OVR X FLG X EOM X CRC X NVB2 X NVB1 X NVB0 X PM6341 E1XC E1 FRAMER/TRANSCEIVER 153 ...
Page 170
... The underrun condition is reflected in the Status register by forcing all bits to logic zero on the first Status register read immediately following the Received Data register read which caused the underrun condition. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 154 ...
Page 171
... The underrun condition will be signalled in the next Status read by returning all zeros. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RD7 X RD6 X RD5 X RD4 X RD3 X RD2 X RD1 X RD0 X PM6341 E1XC E1 FRAMER/TRANSCEIVER 155 ...
Page 172
... BRPCM. BRSIG presents the frozen signalling. If MTKC is a logic 1, each BRPCM and BRSIG time slot may have an unique idle code. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default ACCEL 0 Unused X Unused X Unused X MTKC 0 Reserved 0 IND 0 PCCE 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 156 ...
Page 173
... Upon reset of the E1XC, the ACCEL, MTKC, IND, and PCCE bits are all set to logic 0 disabling µP indirect access and per-timeslot functions. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 157 ...
Page 174
... Status Register should be polled until the BUSY bit goes low before another µP access request is initiated. A µP access request is typically completed within 480 ns. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default BUSY X Unused X Unused X Unused X Unused X Unused X Unused X Unused X PM6341 E1XC E1 FRAMER/TRANSCEIVER 158 ...
Page 175
... R/WB is set to a logic 1, a read from the internal SIGX register is requested, when R/WB is set to a logic 0, a write to the internal SIGX register is requested. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default R/ PM6341 E1XC E1 FRAMER/TRANSCEIVER 159 ...
Page 176
... Signalling Data Register for for Time Slot 15 31H Signalling Data Register for Time Slot 17 • • • • • • PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default D[7] X D[6] X D[5] X D[4] X D[3] X D[2] X D[1] X D[0] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 160 ...
Page 177
... Configuration and Signalling Trunk Conditioning for Time Slot 30 7FH Configuration and Signalling Trunk Conditioning for Time Slot 31 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 161 ...
Page 178
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default A TS ‘n+16’ ‘n+16’ ‘n+16’ ‘n+16’ ‘n’ ‘n’ ‘n’ ‘n’ X PM6341 E1XC E1 FRAMER/TRANSCEIVER 162 ...
Page 179
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default A TS ‘n-16’ ‘n-16’ ‘n-16’ ‘n-16’ ‘n’ ‘n’ ‘n’ ‘n’ X PM6341 E1XC E1 FRAMER/TRANSCEIVER 163 ...
Page 180
... TS0 and TS16 can be replaced with trunk conditioning data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default TCD[6] X TCD[5] X TCD[4] X TCD[3] X TCD[2] X TCD[1] X TCD[0] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 164 ...
Page 181
... When debouncing is selected, per-timeslot signalling transitions are ignored until two consecutive, equal values are sampled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RINV[1] X RINV[0] X RTKCE X RDEBE X A’ X B’ X C’ X D’ X PM6341 E1XC E1 FRAMER/TRANSCEIVER 165 ...
Page 182
... Configuration Register must be set to logic 1. When these bits are enabled, bits RINV[1:0] and RDEBE are ORed with their primary input equivalents to generate the applied configuration signals. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 166 ...
Page 183
... TDLSIG input or from the HDLC transmitter. Reserved. CAS enabled. TS16 data is taken from either BTSIG stream or from the TPSC Data Contol byte as selected on a per timeslot basis via the SIGSRC bit. The format of the BTSIG input data stream is PMC compatible. PM6341 E1XC E1 FRAMER/TRANSCEIVER 167 ...
Page 184
... BTPCM stream. When INDIS and FDIS are logic 0, the bit values used for the International and National bits are dependent upon the values of the GENCRC and FEBEDIS configuration bits, as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 168 ...
Page 185
... CRC multiframe alignment signal is used for the International bit in the NFAS frames, with the Si[1:0] bits in the International/National Control Register used for the spare bits. Bit positions Sn[4:0] in the register are used for the National bits in NFAS frames. PM6341 E1XC E1 FRAMER/TRANSCEIVER 169 ...
Page 186
... TS16 of frame 0 of the signalling multiframe to be inverted (i.e., the correct PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default MTRK 0 FPATINV 0 SPLRINV 0 SPATINV 0 REMAIS 0 MFAIS 0 TS16AIS 0 AIS 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 170 ...
Page 187
... A logic 1 in the AIS bit position forces the output streams to logic 1. When the E1XC is reset, the contents of this register are set to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 171 ...
Page 188
... The Si[1], Si[0], and Sn[4:0] bits should be programmed to a logic 1 when not being used to carry information. When the E1XC is reset, the contents of the register are set to logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Si[1] 1 Si[0] 1 Unused X Sn[4] 1 Sn[3] 1 Sn[2] 1 Sn[1] 1 Sn[0] 1 PM6341 E1XC E1 FRAMER/TRANSCEIVER 172 ...
Page 189
... When the E1XC is reset, the contents of the register are set to logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X X[1] 1 Unused X X[3] 1 X[4] 1 PM6341 E1XC E1 FRAMER/TRANSCEIVER 173 ...
Page 190
... A logic 0 indicates that no overrun has occurred. The OVR bit is cleared by reading this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X INTE 0 XFER X OVR X PM6341 E1XC E1 FRAMER/TRANSCEIVER 174 ...
Page 191
... When the E1XC is reset, the contents of the PMON count registers are unknown until the first latching of performance data is performed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM6341 E1XC E1 FRAMER/TRANSCEIVER 175 ...
Page 192
... The FER counts are suppressed when the FRMR has lost frame alignment (OOF in the FRMR Framing Status register is set). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X FER[6] X FER[5] X FER[4] X FER[3] X FER[2] X FER[1] X FER[0] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 176 ...
Page 193
... Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default FEBE[7] X FEBE[6] X FEBE[5] X FEBE[4] X FEBE[3] X FEBE[2] X FEBE[1] X FEBE[0] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 177 ...
Page 194
... FRMR has lost frame alignment (OOF in the FRMR Framing Status register is set). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X FEBE[9] X FEBE[8] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 178 ...
Page 195
... Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default CRCE[7] X CRCE[6] X CRCE[5] X CRCE[4] X CRCE[3] X CRCE[2] X CRCE[1] X CRCE[0] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 179 ...
Page 196
... CRC error events are suppressed when the FRMR is out of CRC-4 multiframe alignment (OOCMF bit in the FRMR Framing Status register is set). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X CRCE[9] X CRCE[8] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 180 ...
Page 197
... Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default LCV[7] X LCV[6] X LCV[5] X LCV[4] X LCV[3] X LCV[2] X LCV[1] X LCV[0] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 181 ...
Page 198
... These registers indicate the number of LCV error events that occurred during the previous accumulation interval. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X LCV[12] X LCV[11] X LCV[10] X LCV[9] X LCV[8] X PM6341 E1XC E1 FRAMER/TRANSCEIVER 182 ...
Page 199
... When THS is set to logic 1, the slicing threshold is 50% of the peak amplitude and is intended for G.703 2048 kbit/s applications. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X THS 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 183 ...
Page 200
... When the E1XC is reset, the SQE bit is set to logic 0, disabling a squelch event from generating an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused SQI X SQE 0 PM6341 E1XC E1 FRAMER/TRANSCEIVER 184 ...