PM7367-PI PMC-Sierra Inc, PM7367-PI Datasheet
PM7367-PI
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PM7367-PI Summary of contents
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... FREEDM™-32P32 Frame Engine and Datalink Manager Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 PM7367 Datasheet Issue No. 3: June 2007 FREEDM-32P32 Datasheet Released 1 ...
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Legal Information Copyright Copyright 2007 PMC-Sierra, Inc. All rights reserved. The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, no part of this document may be reproduced or ...
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Contacting PMC-Sierra PMC-Sierra 100-2700 Production Way Burnaby, BC Canada V5A 4X1 Tel: +1 (604) 415-6000 Fax: +1 (604) 415-6200 Document Information: Corporate Information: Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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Revision History Issue Issue Date No. 3 June 2007 2 August 2001 1 November 1999 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 Details of Change Added RoHS information. Added Patent ...
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Table of Contents Legal Information........................................................................................................................... 2 Copyright................................................................................................................................. 2 Disclaimer ............................................................................................................................... 2 Trademarks ............................................................................................................................. 2 Patents .................................................................................................................................... 2 Contacting PMC-Sierra.................................................................................................................. 3 Revision History............................................................................................................................. 4 1 Features ................................................................................................................................ 15 2 Applications........................................................................................................................... 17 3 References............................................................................................................................ 18 4 Block Diagram....................................................................................................................... 19 5 Description ............................................................................................................................ ...
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Target Machine............................................................................................... 54 8.5.4 CBI Bus Interface ........................................................................................... 55 8.5.5 Error / Bus Control ......................................................................................... 56 8.6 Transmit DMA Controller ............................................................................................. 56 8.6.1 Data Structures .............................................................................................. 57 8.6.2 Task Priorities................................................................................................. 67 8.6.3 DMA Transaction Controller ........................................................................... 67 8.6.4 Read ...
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Functional Timing................................................................................................................ 233 13.1 Receive Link Input Timing ......................................................................................... 233 13.2 Transmit Link Output Timing ..................................................................................... 234 13.3 PCI Interface ............................................................................................................. 236 13.4 BERT Interface.......................................................................................................... 243 14 Absolute Maximum Ratings ................................................................................................ 245 15 D.C. Characteristics ............................................................................................................ 246 16 FREEDM-32P32 ...
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List of Registers Register 0x000 : FREEDM-32P32 Master Reset........................................................................ 78 Register 0x0: ............................................................................................................................... 79 Register 0x004 : FREEDM-32P32 Master Interrupt Enable........................................................ 80 Register 0x008 : FREEDM-32P32 Master Interrupt Status......................................................... 84 Register 0x00C: FREEDM-32P32 Master Clock / BERT Activity Monitor and ...
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Register 0x298 : RMAC Packet Descriptor Reference Large Buffer Free Queue Start........................................................................................................................ 139 Register 0x29C : RMAC Packet Descriptor Reference Large Buffer Free Queue Write....................................................................................................................... 140 Register 0x2A0 : RMAC Packet Descriptor Reference Large Buffer Free Queue Read....................................................................................................................... 141 Register ...
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Register 0x38C : THDL Indirect Channel Data #3 .................................................................... 174 Register 0x3A0 : THDL Indirect Block Select............................................................................ 178 Register 0x3A4 : THDL Indirect Block Data .............................................................................. 180 Register 0x3B0 : THDL Configuration ....................................................................................... 182 Register 0x400 : TCAS Indirect Link ...
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List of Figures Figure 1 Block Diagram ............................................................................................................. 19 Figure 2 Pin Diagram................................................................................................................. 22 Figure 3 HDLC Frame ............................................................................................................... 35 Figure 4 CRC Generator ........................................................................................................... 36 Figure 5 Partial Packet Buffer Structure.................................................................................... 39 Figure 6 Receive Packet Descriptor.......................................................................................... 42 Figure ...
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Figure 34 PCI Bus Request Cycle........................................................................................... 240 Figure 35 PCI Initiator Abort Termination................................................................................ 240 Figure 36 PCI Exclusive Lock Cycle ....................................................................................... 241 Figure 37 PCI Fast Back to Back ............................................................................................ 243 Figure 38 Receive BERT Port Timing ..................................................................................... 243 Figure ...
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List of Tables Table 1 Line Side Interface Signals (132) ................................................................................. 23 Table 2 PCI Host Interface Signals (51).................................................................................... 26 Table 3 Miscellaneous Interface Signals (41) ........................................................................... 30 Table 4 – Production Test Interface Signals (0 - Multiplexed) .................................................... 32 ...
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Table 34 PCI Interface (Figure 44).......................................................................................... 250 Table 35 JTAG Port Interface (Figure 45) ............................................................................... 251 Table 36 FREEDM-32P32 Ordering Information .................................................................... 253 Table 37 FREEDM-32P32 Thermal Information ..................................................................... 253 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ ...
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Features • Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller. • Supports bi-directional HDLC channels assigned to a maximum of 32 channelized links. The number of time-slots assigned to an HDLC channel ...
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Provides 8 kbytes of on-chip memory for partial packet buffering in each direction. This memory can be configured to support a variety of different channel configurations from a single channel with 8 kbytes of buffering to 32 channels, each ...
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Applications • DCC Processing in SONET/SDH interfaces • Packet-based DSLAM equipment. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 FREEDM-32P32 Datasheet Released 17 ...
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References 1. International Organization for Standardization, ISO Standard 3309-1993, "Information Technology - Telecommunications and information exchange between systems - High-level data link control (HDLC) procedures - Frame structure", December 1993. 2. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering ...
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Block Diagram Figure 1 Block Diagram . RSTB RBCLK RBD Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 FREEDM-32P32 Datasheet Released PMCTEST TDO TDI TCK TMS TRSTB TBCLK TBD 19 ...
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... Description The PM7367 FREEDM-32P32 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 32 bi-directional channels. For channelized links, the FREEDM-32P32 allows bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 32 independently timed links. ...
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In the transmit direction, the PCI Host provides packets to transmit using a transmit ready queue. For each provisioned HDLC channel, the FREEDM-32P32 DMA's partial packets across the PCI bus and into the transmit partial packet buffer. The partial packets ...
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Pin Diagram The FREEDM-32P32 is manufactured in a 272 pin Plastic ball grid array package. The center 16 balls are not used as signal I/Os and are thermal balls. Figure 2 Pin Diagram Proprietary and Confidential to PMC-Sierra, Inc., ...
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Pin Description Table 1 Line Side Interface Signals (132) Pin Name Type RCLK[0] Input RCLK[1] RCLK[2] RCLK[3] RCLK[4] RCLK[5] RCLK[6] RCLK[7] RCLK[8] RCLK[9] RCLK[10] RCLK[11] RCLK[12] RCLK[13] RCLK[14] RCLK[15] RCLK[16] RCLK[17] RCLK[18] RCLK[19] RCLK[20] RCLK[21] RCLK[22] RCLK[23] RCLK[24] RCLK[25] ...
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Pin Name Type RD[18] RD[19] RD[20] RD[21] RD[22] RD[23] RD[24] RD[25] RD[26] RD[27] RD[28] RD[29] RD[30] RD[31] RBD Tristate Output RBCLK Tristate Output TCLK[0] Input TCLK[1] TCLK[2] TCLK[3] TCLK[4] TCLK[5] TCLK[6] TCLK[7] TCLK[8] TCLK[9] TCLK[10] TCLK[11] TCLK[12] TCLK[13] TCLK[14] TCLK[15] ...
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Pin Name Type TCLK[29] TCLK[30] TCLK[31] TD[0] Output TD[1] TD[2] TD[3] TD[4] TD[5] TD[6] TD[7] TD[8] TD[9] TD[10] TD[11] TD[12] TD[13] TD[14] TD[15] TD[16] TD[17] TD[18] TD[19] TD[20] TD[21] TD[22] TD[23] TD[24] TD[25] TD[26] TD[27] TD[28] TD[29] TD[30] TD[31] TBD ...
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Table 2 PCI Host Interface Signals (51) Pin Name Type PCICLK Input PCICLKO Output AD[0] I/O AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] ...
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Pin Name Type PAR I/O FRAMEB I/O TRDYB I/O Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 Pin Function No. When the FREEDM-32P32 is the target, C/BEB[3: input bus. ...
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Pin Name Type IRDYB I/O STOPB I/O IDSEL Input DEVSELB I/O Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 Pin Function No. When the FREEDM-32P32 is not involved in the current ...
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Pin Name Type LOCKB Input REQB Output GNTB Input PCIINTB OD Output PERRB I/O Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 Pin Function No. AD[31:0] bus. When a target, recognizes ...
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Pin Name Type SERRB OD Output Table 3 Miscellaneous Interface Signals (41) Pin Name Type SYSCLK Input RSTB Input PMCTEST Input TCK Input TMS Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, ...
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Pin Name Type TDI Input Tristate TDO Output TRSTB Input VBIAS[3:1] Input EN5V Input NC Open Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 Pin Function No. K3 The test data ...
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Pin Name Type Table 4 – Production Test Interface Signals (0 - Multiplexed) Pin Name Type TA[0] Input TA[1] TA[2] TA[3] TA[4] TA[5] TA[6] TA[7] TA[8] TA[9] TA[10] TA[11]/TRS Input TRDB Input TWRB Input Proprietary and Confidential to PMC-Sierra, Inc., ...
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Pin Name Type TDAT[0] I/O TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] Table 5 – Power and Ground Signals (60) Pin Name Type VDD1 Power VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 ...
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Pin Name Type VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 Notes on Pin Description: 1. All FREEDM-32P32 inputs and bi-directionals present minimum capacitive loading and operate at TTL compatible logic levels. PCI signals ...
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Functional Description 8.1 High-Level Data Link Control Protocol Figure 3 shows a diagram of the synchronous HDLC protocol supported by the FREEDM- 32P32. The incoming stream is examined for flag bytes (01111110 bit pattern) which delineate the opening and ...
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Figure 4 CRC Generator LSB 8.2 Receive Channel Assigner The Receive Channel Assigner block (RCAS) processes serial links. Each link is independent and has its own associated clock. For each link, the RCAS ...
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Line Interface There are 32 identical line interface blocks in the RCAS. Each line interface contains a bit counter, an 8-bit shift register and a holding register, that, together, perform serial to parallel conversion. Whenever the holding register is ...
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Receive HDLC Processor / Partial Packet Buffer The Receive HDLC Processor / Partial Packet Buffer block (RHDL) processes synchronous transmission HDLC data streams. Each channel can be individually configured to perform flag sequence detection, bit de-stuffing ...
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Partial Packet Buffer Processor The partial packet buffer processor controls the 8 Kbyte partial packet RAM which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular channel FIFO ...
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The FIFO algorithm of the partial packet buffer processor is based on a programmable per- channel transfer size. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of transactions. Whenever the partial ...
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Receive DMA Controller The Receive DMA Controller block (RMAC DMA controller which stores received packet data in host computer memory. The RMAC is not directly connected to the host memory PCI bus. Memory accesses are serviced by ...
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Figure 6 Receive Packet Descriptor Bit 31 Bytes In Buffer [15:0] Reserved (16) Table 6 Receive Packet Descriptor Fields Field Data Buffer Start Address[31:0] RCC[6:0] CE Offset[1:0] Status [5:0] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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Field Bytes in Buffer [15:0] Next RPD Pointer [13:0] Receive Buffer Size [15:0] The Receive Buffer Size and Data Buffer Start Address fields are written only by the host. The RMAC reads these fields to determine where to store packet ...
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Figure 7 Receive Packet Descriptor Table RPDTB[31: Packet Descriptor Table Base register RPDR[13:0] = Receive Packet Desriptor Reference RPD_ADDR[31:0] = Receive Packet Descriptor Address RPDTB RPD_ADDR RPD 16384 The Receive Packet Descriptor Table resides in host memory. The ...
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Receive Packet Queues Receive Packet Queues are used to transfer RPDRs between the host and the RMAC. There are three queues: a RPDR Large Buffer Free Queue (RPDRLFQ), a RPDR Small Buffer Free Queue (RPDRSFQ) and a RPDR Ready Queue ...
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Figure 8 RPDRF and RPDRR Queues Receive Packet Descriptor (RPD) Reference Queues Base Address: RQB[31: Queue Base register Index Registers: Large Buffer Free Queue: RPDRLFQS[15:0] = RPDR Large Free Queue Start register RPDRLFQW[15:0] = RPDR Large Free Queue ...
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Note that the maximum value to which an end pointer may be set is FFFF hex, resulting in a maximum offset from the queue base address of (4*(FFFF-1)) = 3FFF8 hex. An end pointer must not be set to 0 ...
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Figure 9 RPDRR Queue Operation Rx Packet Descriptor Reference Ready Queue RPDRRQ_START_ADDR RPDRRQ_READ_ADDR RPDRRQ_WRITE_ADDR RPDRRQ_END_ADDR Receive Channel Descriptor Reference Table On a per-channel basis, the RMAC caches information such as the current DMA information in a Receive Channel Descriptor Reference ...
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Figure 10 Receive Channel Descriptor Reference Table Bit 31 RCC 0 Bytes Available in Buffer[15:0] RCC 1 Bytes Available in Buffer[15:0] RCC 31 Bytes Available in Buffer[15:0] Table 8 Receive Channel Descriptor Reference Table Fields Field Bytes Available in Buffer[15:0] ...
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DMA Transaction Controller The DMA Transaction Controller coordinates the reception of data packets from the Receive Packet Interface and their subsequent storage in host memory. A packet may be received over a number of separate transactions, interleaved with transactions ...
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PCI Controller The General-Purpose Peripheral Component Interconnect Controller block (GPIC) provides a 32-bit Master and Target interface core which contains all the required control functions for Peripheral Component Interconnect (PCI) Bus Revision 2.1 interfacing. Communications between the PCI bus ...
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When an external PCI bus arbitrator issues a Grant in response to the Request from the GPIC, the master state machine monitors the PCI bus to insure that the previous master has completed its transaction and has released the bus ...
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The maximum duration of a master burst cycle is controlled by the value set in the LATENCY TIMER register in the GPIC Configuration Register block. This value is set by the host on boot and is loaded into a counter ...
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All data is passed between the GPIC and the DMA controllers in little Endian format and, in the default mode of operation, the GPIC expects all data on the PCI bus to also be in little Endian format. The GPIC ...
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Figure 11 GPIC Address Map The GPIC responds with medium timing to master accesses. (I.e. DEVSELB is asserted 2 PCICLK cycles after FRAMEB asserted) It inserts three wait states on reads to the internal CBI register space (four wait states ...
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Write transfers to the CBI space always write all 32 bits provided that at least one byte enable is asserted. A write command with all byte enables negated will be ignored. Read transfers always return the 32 bits regardless of ...
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Data Structures The TMAC communicates with the host using Transmit Descriptors (TD), Transmit Descriptor References (TDR), the Transmit Data Reference Ready (TDRR) queue and the Transmit Data Reference Free (TDRF) queue. The TMAC reads packet data from data buffers ...
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Field TCC[6:0] TMAC Next TD Pointer [13:0] ABT IOC Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 Description The V bit is used to indicate that the TMAC ...
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Field Host Next TD Pointer [13:0] Transmit Buffer Size [15:0] Transmit Descriptor Table The Transmit Descriptor Table, which resides in host memory, contains all of the Transmit Descriptors referenced by the TMAC. To access a TD, the TMAC takes a ...
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Figure 13 Transmit Descriptor Table TDTB TD_ADDR Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 TDTB[31: Descriptor Table Base register TDR[13:0] = Transmit Descriptor Reference TD_ADDR[31:0] = Transmit Descriptor ...
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Transmit Queues Pointers to the transmit descriptors (TDs) containing packet(s) ready for transmission are passed from the host to the TMAC using the Transmit Descriptor Reference Ready (TDRR) queue, which resides in host memory. Pointers to transmit descriptor structures whose ...
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Figure 14 TDRR and TDRF Queues Transmit Descriptor Referance Queues Base Address: TQB[31: Queue Base register Index Registers: Ready: TDRRQS[15:0] = TDR Ready Queue Start register TDRRQW[15:0] = TDR Ready Queue Write register TDRRQR[15:0] = TDR Ready Queue ...
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Field Description Status[2:0] The TMAC fills in the Status field to indicate to the host the results of processing the TD. The encoding is: Status[1: Status[ TDR[13:0] The TDR[13:0] field contains the offset of ...
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Figure 15 Transmit Channel Descriptor Reference Table Bit 31 TCC 0, Pri TCC 1, Pri TCC 31, Pri Table 11 Transmit Channel Descriptor Reference Table Fields Field M CE Last TD ...
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Field IOC PiP NA U Host TD Pointer [13:0] DMA Current Address[31:0] V Next TD Pointer [13:0] Transmit Descriptor Linking As described above, the TCDR table contains pointers which the TMAC uses to construct linked lists of data packets to ...
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Figure 16 TD Linking Curr. Next Last Host TDR TDR TDR TDR TCDR Table The host links the TDs vertically while the TMAC links TDs horizontally. Figure 16 shows the TDs for packets P1 and P2 linked by the host ...
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Task Priorities The TMAC must perform a number of tasks concurrently in order to maintain a steady flow of data through the system. The main tasks of the TMAC are managing the Ready Queue (i.e. removing chains of data ...
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Transmit HDLC Controller / Partial Packet Buffer The Transmit HDLC Controller / Partial Packet Buffer block (THDL) contains a partial packet buffer for PCI latency control and a transmit HDLC controller. Packet data retrieved from the PCI host memory ...
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The partial packet buffer processor is divided into three sections: reader, writer and roamer. The roamer is a time-sliced state machine which tracks each channel's FIFO buffer free space and signals the writer to service a particular channel. The writer ...
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The FIFO algorithm of the partial packet buffer processor is based on per-channel software programmable transfer size and free space trigger level. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of ...
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Links containing stream may be channelized. Data at each time-slot may be independently assigned to be sourced from a different channel. The link clock is only active during time-slots ...
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Priority Encoder The priority encoder monitors the line interfaces for requests and synchronizes them to the SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to lowest priority is assigned from line interface TD[0] to ...
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PCI Host Accessible registers (PA) - these registers can be accessed through the PCI Host interface. • PCI Configuration registers (PC) - these register can only be accessed through the PCI Host interface during a PCI configuration cycle. The ...
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PCI Offset Register 0x220 0x224 0x228 - 0x23C RHDL Reserved 0x240 - 0x27C Reserved 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC 0x2C0 0x2C4 0x2C8 - 0x2FC 0x300 0x304 0x308 0x30C 0x310 ...
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PCI Offset Register 0x384 0x388 0x38C THDL Indirect Channel Data #3 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC THDL Reserved 0x3B0 THDL Configuration 0x3B4 - 0x3BC 0x3C0 - 0x3FF Reserved 0x400 0x404 0x408 0x40C 0x410 TCAS Channel Disable 0x414 ...
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PCI Offset 0x10 0x14 - 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 Register CBI Memory Base Address Register Unused Base Address Register Reserved ...
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Normal Register Description Normal mode registers are used to configure and monitor the operation of the FREEDM. 9.1 Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility ...
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Register 0x000 : FREEDM-32P32 Master Reset Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 FREEDM-32P32 Datasheet Released 78 ...
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Register 0x0: Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ...
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Register 0x004 : FREEDM-32P32 Master Interrupt Enable Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 ...
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RFCSEE: The receive frame check sequence error interrupt enable bit (RFCSEE) enables receive FCS error interrupts to the PCI host. When RFCSEE is set high, a mismatch between the received FCS code and the computed CRC residue will cause an ...
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RPQLFE: The receive packet descriptor large buffer free queue cache read interrupt enable bit (RPQLFE) enables receive packet descriptor large free queue cache read interrupts to the PCI host. When RPQLFE is set high, reading a programmable number of RPDR ...
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TDQRDYE: The transmit descriptor ready queue cache read interrupt enable bit (TDQRDYE) enables transmit descriptor ready queue cache read interrupts to the PCI host. When TDQRDYE is set high, reading a programmable number of TDRs from the TDR Ready Queue ...
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Register 0x008 : FREEDM-32P32 Master Interrupt Status Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...
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RFCSEI: The receive frame check sequence error interrupt status bit (RFCSEI) reports receive FCS error interrupts to the PCI host. RFCSEI is set high, when a mismatch between the received FCS code and the computed CRC residue is detected. RFCSEI ...
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RPQRDYI: The receive packet descriptor ready queue write interrupt status bit (RPQRDYI) reports receive packet descriptor ready queue write interrupts to the PCI host. RPQRDYI is set high when the programmable number of RPDRs is written to the RPDR Ready ...
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TDFQEI: The transmit descriptor free queue error interrupt status bit (TDFQEI) reports transmit descriptor free queue error interrupts to the PCI host. TDFQEI is set high when an attempt to write to the transmit free queue fail due to the ...
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Register 0x00C: FREEDM-32P32 Master Clock / BERT Activity Monitor and Accumulation Trigger Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit ...
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TBDA: The transmit BERT data active bit (TBDA) monitors for low to high transitions on the TBD input. TBDA is set high on a rising edge of TDB, and is set low when this register is read. Proprietary and Confidential ...
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Register 0x010 : FREEDM-32P32 Master Link Activity Monitor Bit Type Bit 31 to Bit 16 Bit 15 R Bit 14 R Bit 13 R Bit 12 R Bit 11 R Bit 10 R Bit 9 R Bit 8 R Bit ...
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RLGA[2]: The receive link group #2 active bit (RLGA[2]) monitors for transitions on the RD[11:8] and RCLK[11:8] inputs. RLGA[2] is set high when each of RD[11:8] has been sampled low and sampled high by rising edges of the corresponding RCLK[11:8] ...
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TLGA[0]: The transmit link group #0 active bit (TLGA[0]) monitors for low to high transitions on the TCLK[3:0] inputs. TLGA[0] is set high when rising edges have been observed on all the signals on the TCLK[3:0] inputs, and is set ...
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TLGA[7]: The transmit link group #7 active bit (TLGA[7]) monitors for low to high transitions on the TCLK[31:28] inputs. TLGA[7] is set high when rising edges have been observed on all the signals on the TCLK[31:28] inputs, and is set ...
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Register 0x014 : FREEDM-32P32 Master Line Loopback #1 Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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Register 0x018 : FREEDM-32P32 Master Line Loopback #2 Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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Register 0x020 : FREEDM-32P32 Master BERT Control Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...
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TBSEL[4:0]: The transmit bit error rates testing link select bits (TBSEL[4:0]) controls the over-writing of transmit data on TD[31:0] by data on TBD when transmit bit error rate testing is enabled (TBEN set high) and the selected link is not ...
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Register 0x024 : FREEDM-32P32 Master Performance Monitor Control Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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RABRT1EN: The receive abort accumulate enable bit (RABRT1EN) enables counting of receive HDLC abort events. When RABRT1EN is set high, receipt of an abort code (at least 7 contiguous 1's) will cause the PMON Configurable Accumulator #1 register to increment. ...
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RFCSE2EN: The receive frame check sequence error accumulate enable bit (RFCSE2EN) enables counting of receive FCS error events. When RFCSE2EN is set high, a mismatch between the received FCS code and the computed CRC residue will cause the PMON Configurable ...
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Register 0x040 : GPIC Control Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit ...
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Table 15 Little Endian Format DWORD Address SOE_E: The stop on error enable (SOE_E) bit determines the action the PCI controller will take when a system or parity error occurs. When set high the PCI controller will disconnect the PCI ...
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Register 0x100 : RCAS Indirect Link and Time-slot Select Bit Type Bit 31 to Bit 16 Bit 15 R Bit 14 R/W Bit 13 Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit ...
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RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the channel provision RAM. The address to the channel provision RAM is constructed by concatenating the TSLOT[4:0] and LINK[4:0] bits. Writing a logic ...
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Register 0x104 : RCAS Indirect Channel Data Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...
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PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect read operation has completed. The provision enable flag to be written to the channel provision RAM ...
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Register 0x108 : RCAS Framing Bit Threshold Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...
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Register 0x10C : RCAS Channel Disable Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 R/W Bit ...
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Register 0x180 : RCAS Link #0 Configuration Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...
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E1: The E1 frame structure select bit (E1) configures receive link #0 for channelized E1 operation when CEN is set high. RCLK[0] is held quiescent during the FAS and NFAS framing bytes. The data bit on RD[0] associated with the ...
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Register 0x184 - 0x188 : RCAS Link # Configuration Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit ...
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E1: The E1 frame structure select bit (E1) configures the corresponding receive link for channelized E1 operation when CEN is set high. RCLK[n] is held quiescent during the FAS and NFAS framing bytes. The data bit on RD[n] associated with ...
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Register 0x18C : RCAS Link #3 Configuration Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...
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E1: The E1 frame structure select bit (E1) configures receive link #3 for channelized E1 operation when CEN is set high. RCLK[3] is held quiescent during the FAS and NFAS framing bytes. The data bit on RD[3] clocked in by ...
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Register 0x190-0x1FC : RCAS Link #4 to Link #31 Configuration Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit ...
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E1: The E1 frame structure select bit (E1) configures the corresponding receive link for channelized E1 operation when CEN is set high. RCLK[n] is held quiescent during the FAS and NFAS framing bytes. The data bit on RD[n] clocked in ...
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Register 0x200 : RHDL Indirect Channel Select Bit Type Bit 31 to Bit 16 Bit 15 R Bit 14 R/W Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 ...
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BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, ...
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Register 0x204 : RHDL Indirect Channel Data Register #1 Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R Bit 9 Bit 8 W Bit ...
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DELIN: The indirect delineate enable bit (DELIN) configures the HDLC processor to perform flag sequence delineation and bit de-stuffing on the incoming data stream. The delineate enable bit to be written to the channel provision RAM indirect channel ...
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PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect channel read operation has completed. The provision enable flag to be written to the channel provision RAM, in ...
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Register 0x208 : RHDL Indirect Channel Data Register #2 Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit ...
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OFFSET[1:0]: The packet byte offset (OFFSET[1:0]) configures the partial packet processor to insert invalid bytes at the beginning of a packet stored in the channel FIFO. The value of OFFSET[1: written to the channel provision RAM ...
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Register 0x210 : RHDL Indirect Block Select Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...
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BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and stays high until the access is complete. At which point, BUSY ...
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Register 0x214 : RHDL Indirect Block Data Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...
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Register 0x220 : RHDL Configuration Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 R/W Bit 8 R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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LENCHK: The packet length error check bit (LENCHK) controls the checking of receive packets that are longer than the maximum programmed length. When LENCHK is set high, receive packets are aborted and the remainder of the frame discarded when the ...
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Register 0x224 : RHDL Maximum Packet Length Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 ...
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Register 0x280 : RMAC Control Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 ...
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RAWMAX[1:0]: The RAWMAX[1:0] field determines how ‘raw’ (i.e. non packet delimited) data is written to host memory. Raw data is written to buffers in host memory in the same manner as packet delimited data. Whenever RAWMAX[1: buffers have ...
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Table 19 RPQ_SFN[1:0] Settings RPQ_SFN[1: Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue Reads Reserved FREEDM-32P32 Datasheet Released 132 ...
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Register 0x284 : RMAC Indirect Channel Provisioning Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...
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PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the RMAC internal memory after an indirect read operation has completed. The provision enable flag to be written to the RMAC internal memory ...
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Register 0x288 : RMAC Packet Descriptor Table Base LSW Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit ...
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Register 0x28C : RMAC Packet Descriptor Table Base MSW Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W ...
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Register 0x290 : RMAC Queue Base LSW Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 ...
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Register 0x294 : RMAC Queue Base MSW Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 ...
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Register 0x298 : RMAC Packet Descriptor Reference Large Buffer Free Queue Start Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W ...
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Register 0x29C : RMAC Packet Descriptor Reference Large Buffer Free Queue Write Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 ...
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Register 0x2A0 : RMAC Packet Descriptor Reference Large Buffer Free Queue Read Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 ...
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Register 0x2A4 : RMAC Packet Descriptor Reference Large Buffer Free Queue End Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 ...
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Register 0x2A8 : RMAC Packet Descriptor Reference Small Buffer Free Queue Start Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 ...
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Register 0x2AC : RMAC Packet Descriptor Reference Small Buffer Free Queue Write Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 Bit ...
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Register 0x2B0 : RMAC Packet Descriptor Reference Small Buffer Free Queue Read Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 ...
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Register 0x2B4 : RMAC Packet Descriptor Reference Small Buffer Free Queue End Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 ...
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Register 0x2B8 : RMAC Packet Descriptor Reference Ready Queue Start Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 ...
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Register 0x2BC : RMAC Packet Descriptor Reference Ready Queue Write Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 ...
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Register 0x2C0 : RMAC Packet Descriptor Reference Ready Queue Read Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit ...
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Register 0x2C4 : RMAC Packet Descriptor Reference Ready Queue End Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 ...
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Register 0x300 : TMAC Control Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit ...
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TDQ_RDYN[2:0]: The TDQ_RDYN[2:0] field sets the number of transmit descriptor references (TDRs) that must be read from the TDR Ready Queue before the TDR Ready interrupt (TDQRDYI) is asserted, as follows: Table 20 TDQ_RDYN[2:0] Settings TDQ_RDYN[2:0] 000 001 010 011 ...
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Register 0x304 : TMAC Indirect Channel Provisioning Bit Type Bit 31 to Bit 16 Bit 15 R Bit 14 R/W Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 R/W Bit 6 Bit 5 Bit ...
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PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the TMAC internal memory after an indirect read operation has completed. The provision enable flag to be written to the TMAC internal memory ...
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Register 0x308 : TMAC Descriptor Table Base LSW Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit ...
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Register 0x30C : TMAC Descriptor Table Base MSW Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit ...
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Register 0x310 : TMAC Queue Base LSW Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...
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Register 0x314 : TMAC Queue Base MSW Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 ...
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Register 0x318 : TMAC Descriptor Reference Free Queue Start Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W ...
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Register 0x31C : TMAC Descriptor Reference Free Queue Write Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W ...
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Register 0x320 : TMAC Descriptor Reference Free Queue Read Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 ...
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Register 0x324 : TMAC Descriptor Reference Free Queue End Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit ...
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Register 0x328 :TMAC Descriptor Reference Ready Queue Start Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit ...
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Register 0x32C : TMAC Descriptor Reference Ready Queue Write Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit ...
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Register 0x330 : TMAC Descriptor Reference Ready Queue Read Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W ...
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Register 0x334 : TMAC Descriptor Reference Ready Queue End Bit Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit ...
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Register 0x380 : THDL Indirect Channel Select Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, ...
Page 169
Register 0x384 : THDL Indirect Channel Data #1 Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 Bit 9 Bit 8 W Bit 7 W ...
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DELIN: The indirect delineate enable bit (DELIN) configures the HDLC processor to perform flag sequence insertion and bit stuffing on the outgoing data stream. The delineate enable bit to be written to the channel provision RAM indirect channel ...
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PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect channel read operation has completed. The provision enable flag to be written to the channel provision RAM, in ...
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Register 0x388 : THDL Indirect Channel Data #2 Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 Bit 10 Bit 9 Bit 8 W Bit 7 W Bit ...
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INVERT: The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert the outgoing HDLC stream. The value of INVERT to be written to the channel provision RAM indirect channel write operation, must be set up ...
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Register 0x38C : THDL Indirect Channel Data #3 Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit ...
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The case of a single block transfer size is a special. When BURSTEN is set high and XFER[2:0] = 'b000, the transfer size is variable. The THDL will request the TMAC to transfer as much data as there is free ...
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To prevent lockup, the channel transfer size (XFER[2:0]) can be configured to be less than or equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel transfer size can be set, such that, the total number ...
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LEVEL[3:0] Expedite Trigger Level 0111 24 Blocks (384 bytes free) 32 Blocks 1000 (512 bytes free) 1001 48 Blocks (768 bytes free) 64 Blocks 1010 (1 Kbytes free) 1011 96 Blocks (1.5 Kbytes free) 1100 128 Blocks (2 Kbytes free) ...
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Register 0x3A0 : THDL Indirect Block Select Bit Type Bit 31 to Bit 16 Bit 15 R Bit 14 R/W Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit ...
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BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, ...
Page 180
Register 0x3A4 : THDL Indirect Block Data Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 ...
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Reserved: The reserved bit (Reserved) must be set low for correct operation of the FREEDM-32P32 device. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-1991499, Issue 3 FREEDM-32P32 Datasheet Released 181 ...
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Register 0x3B0 : THDL Configuration Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 Bit 5 Bit 4 Bit ...
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BURSTEN: The burst length enable bit (BURSTEN) controls the use of BURST[2:0] in determining the amount of data requested in a single DMA transaction for channels whose channel transfer size is set to one block (XFER[2:0] = 'b000). BURSTEN has ...
Page 184
Register 0x400 : TCAS Indirect Link and Time-slot Select Bit Type Bit 31 to Bit 16 Bit 15 R Bit 14 R/W Bit 13 Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit ...
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RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the transmit channel provision RAM. The address to the transmit channel provision RAM is constructed by concatenating the TSLOT[4:0] and LINK[4:0] bits. Writing ...
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Register 0x404 : TCAS Indirect Channel Data Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 R/W Bit 7 Bit 6 Bit 5 Bit 4 R/W ...
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PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from transmit channel provision RAM after an indirect read operation has completed. The provision enable flag to be written to the transmit channel provision RAM in ...
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Register 0x408 : TCAS Framing Bit Threshold Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 ...
Page 189
Register 0x40C : TCAS Idle Time-slot Fill Data Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 R/W Bit 6 R/W Bit 5 R/W ...
Page 190
Register 0x410 : TCAS Channel Disable Bit Type Bit 31 to Bit 16 Bit 15 R/W Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 R/W Bit ...
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Register 0x480 : TCAS Link #0 Configuration Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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E1: The E1 frame structure select bit (E1) configures link #0 for channelized E1 operation when CEN is set high. TCLK[0] is held quiescent during the FAS and NFAS framing bytes. The most significant bit of time-slot 1 is placed ...
Page 193
Register 0x484-0x488 : TCAS Link #1 to Link #2 Configuration Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit ...
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E1: The E1 frame structure select bit (E1) configures the corresponding link for channelized E1 operation when CEN is set high. TCLK[n] is held quiescent during the FAS and NFAS framing bytes. The most significant bit of time-slot 1 is ...
Page 195
Register 0x48C : TCAS Link #3 Configuration Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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E1: The E1 frame structure select bit (E1) configures link #3 for channelized E1 operation when CEN is set high. TCLK[3] is held quiescent during the FAS and NFAS framing bytes. The most significant bit of time-slot 1 is placed ...
Page 197
Register 0x490-0x4FC : TCAS Link #4 to Link #31 Configuration Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit ...
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E1: The E1 frame structure select bit (E1) configures the corresponding link for channelized E1 operation when CEN is set high. TCLK[n] is held quiescent during the FAS and NFAS framing bytes. The most significant bit of time-slot 1 is ...
Page 199
Register 0x500 : PMON Status Bit Type Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 R Bit 4 R Bit 3 ...
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C1DET: The configurable event #1 detect bit (C1DET) indicates the status of the PMON Configurable Count #1 register. C1DET is set high when selected events have occurred during the latest PMON accumulation interval. C1DET is set low if no selected ...