TP82C54-2 Intel Corporation, TP82C54-2 Datasheet
TP82C54-2
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TP82C54-2 Summary of contents
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CHMOS PROGRAMMABLE INTERVAL TIMER Compatible with all Intel and most Y other microprocessors High Speed ‘‘Zero Wait State’’ Y Operation with 8 MHz 8086 88 and 80186 188 Handles Inputs from MHz for 82C54-2 Available in EXPRESS ...
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Pin Number Symbol DIP PLCC D -D 1-8 2 CLK OUT GATE GND 12 14 OUT GATE CLK GATE ...
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Block Diagram DATA BUS BUFFER This 3-state bi-directional 8-bit buffer is used to in- terface the 82C54 to the system bus (see Figure 3) Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC ...
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Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag (See detailed explanation of ...
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OPERATIONAL DESCRIPTION General After power-up the state of the 82C54 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it ...
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Write Operations The programming procedure for the 82C54 is very flexible Only two conventions need to be remem- bered 1) For each Counter the Control Word must be written before the initial count is written 2) The initial count ...
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COUNTER LATCH COMMAND The second method uses the ‘‘Counter Latch Com- mand’’ Like a Control Word this command is written to the Control Word Register which is selected when Also like a Control Word the e 1 ...
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The read-back command may also be used to latch status information of ...
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Write into Counter Write into Counter Write into Counter Write ...
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If an initial count is written while GATE still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this ...
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MODE 2 RATE GENERATOR This Mode functions like a divide-by-N counter It is typicially used to generate a Real Time Clock inter- rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for ...
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OUT will be high for ( counts and low for counts b NOTE A GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED ...
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After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe ...
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Operation Common to All Modes Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE ...
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ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias Storage Temperature b Supply Voltage Operating Voltage Voltage on any Input GND Voltage on any Output GND Power Dissipation D C CHARACTERISTICS ( ...
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A C CHARACTERISTICS (Continued) WRITE CYCLE Symbol Parameter t Address Stable Before Stable Before Address Hold Time After Pulse Width WW t Data Setup Time Before WR DW ...
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WAVEFORMS WRITE READ RECOVERY 82C54 231244 –14 231244 –15 231244–16 17 ...
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CLOCK AND GATE A C TESTING INPUT OUTPUT WAVEFORM INPUT OUTPUT A C Testing Inputs are driven for a logic ‘‘1’’ and 0 45V for a logic ‘‘0 ’’ Timing measurements are made ...