P8088 Intel Corporation, P8088 Datasheet

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P8088

Manufacturer Part Number
P8088
Description
8-bit HMOS microprocessor, 5 MHz
Manufacturer
Intel Corporation
Datasheet

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P80882
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The Intel 8088 is a high performance microprocessor implemented in N-channel depletion load silicon gate
technology (HMOS-II) and packaged in a 40-pin CERDIP package The processor has attributes of both 8-
and 16-bit microprocessors It is directly compatible with 8086 software and 8080 8085 hardware and periph-
erals
8-Bit Data Bus Interface
16-Bit Internal Architecture
Direct Addressing Capability to 1 Mbyte
of Memory
Direct Software Compatibility with 8086
CPU
14-Word by 16-Bit Register Set with
Symmetrical Operations
24 Operand Addressing Modes
August 1990
Figure 1 8088 CPU Functional Block Diagram
8-BIT HMOS MICROPROCESSOR
8088 8088-2
8088
231456 –1
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Y
Y
Y
Byte Word and Block Operations
8-Bit and 16-Bit Signed and Unsigned
Arithmetic in Binary or Decimal
Including Multiply and Divide
Two Clock Rates
Available in EXPRESS
5 MHz for 8088
8 MHz for 8088-2
Standard Temperature Range
Extended Temperature Range
Figure 2 8088 Pin Configuration
Order Number 231456-006
231456 – 2

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P8088 Summary of contents

Page 1

HMOS MICROPROCESSOR 8-Bit Data Bus Interface Y 16-Bit Internal Architecture Y Direct Addressing Capability to 1 Mbyte Y of Memory Direct Software Compatibility with 8086 Y CPU 14-Word by 16-Bit Register Set with Y Symmetrical Operations 24 Operand Addressing ...

Page 2

The following pin function descriptions are for 8088 systems in either minimum or maximum mode The ‘‘local bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8088 (without regard to additional bus buffers) Symbol Pin ...

Page 3

Table 1 Pin Description (Continued) Symbol Pin No Type NMI 17 I NON-MASKABLE INTERRUPT is an edge triggered input which causes a type 2 interrupt A subroutine is vectored to via an interrupt vector lookup table located in system memory ...

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Table 1 Pin Description (Continued) Symbol Pin No Type HOLD HOLD indicates that another master is requesting a local bus ‘‘hold’’ HLDA acknowledged HOLD must be active HIGH The processor receiving the ‘‘hold’’ ...

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Table 1 Pin Description (Continued) Symbol Pin No Type RQ GT0 REQUEST GRANT pins are used by other local bus masters to force the RQ GT1 processor to release the local bus at the end of ...

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FUNCTIONAL DESCRIPTION Memory Organization The processor provides a 20-bit address to memory which locates the byte being referenced The memo organized as a linear array million bytes addressed as 00000(H) to FFFFF(H) The ...

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Certain locations in memory are reserved for specific CPU operations (See Figure 4) Locations from ad- dresses FFFF0H through FFFFFH are reserved for operations including a jump to the initial system ini- tialization routine Following RESET the CPU will al- ...

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Figure 5 Multiplexed Bus Configuration 8 231456 – 5 ...

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Figure 6 Demultiplexed Bus Configuration Figure 7 Fully Buffered System Using Bus Controller 8088 231456 – 6 231456 – ...

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Bus Operation The 8088 address data bus is broken into three parts the lower eight address data bits (AD0 – AD7) the middle eight address bits (A8 – A15) and the upper four address bits (A16– A19) The ad- ...

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In the event that a ‘‘NOT READY’’ indication is given by the addressed device ‘‘wait’’ states (Tw) are in- serted between T3 and T4 Each inserted ‘‘wait’’ state is of the ...

Page 12

Interrupts result in a transfer of control to a new pro- gram location A 256 element table containing ad- dress pointers to the interrupt service program loca- tions resides in absolute locations 0 through 3FFH (See Figure 4) which ...

Page 13

Figure 9 Interrupt Acknowledge Sequence External Synchronization via TEST As an alternative to interrupts the 8088 provides a single software-testable input pin (TEST) This input is utilized by executing a WAIT instruction The sin- gle WAIT instruction is repeatedly executed ...

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The basic difference between the interrupt acknowl- edge cycle and a read cycle is that the interrupt ac- knowledge (INTA) signal is asserted in place of the read (RD) signal and the address bus is floated (See Figure 9) ...

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SSO provides the SO status information in the minimum mode This output occurs on pin 34 in minimum mode only and SSO pro- vide the complete bus status in minimum mode Figure 10 Medium Complexity System ...

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... Voltage on Any Pin with Respect to Ground Power Dissipation D C CHARACTERISTICS ( (Plastic CASE and for P8088-2 only CASE T is guaranteed as long not exceeded) A CASE (V 5V 10% for 8088 ...

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... A C CHARACTERISTICS ( (Plastic CASE and for P8088-2 only CASE T is guaranteed as long not exceeded) A CASE (V 5V 10% for 8088 MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS Symbol Parameter TCLCL ...

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A C CHARACTERISTICS (Continued) TIMING RESPONSES Symbol Parameter TCLAV Address Valid Delay TCLAX Address Hold Time TCLAZ Address Float Delay TLHLL ALE Width TCLLH ALE Active Delay TCHLL ALE Inactive Delay TLLAX Address Hold Time to ALE Inactive TCLDV ...

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A C TESTING INPUT OUTPUT WAVEFORM A C Testing Inputs are driven for a logic ‘‘1’’ and 0 45V for a logic ‘‘0’’ Timing measurements are made for both a logic ‘‘1’’ and logic ...

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WAVEFORMS (Continued) BUS TIMING MINIMUM MODE SYSTEM (Continued) NOTES 1 All signals switch between V and RDY is sampled near the end Two INTA cycles run back-to-back The 8088 ...

Page 21

A C CHARACTERISTICS MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS Symbol Parameter TCLCL CLK Cycle Period TCLCH CLK Low Time TCHCL CLK High Time TCH1CH2 CLK Rise Time TCL2CL1 CLK Fall Time TDVCL Data in Setup Time TCLDX ...

Page 22

A C CHARACTERISTICS (Continued) TIMING RESPONSES Symbol Parameter TCLML Command Active Delay (Note 1) TCLMH Command Inactive Delay (Note 1) TRYHSH READY Active to Status Passive (Note 3) TCHSV Status Active Delay TCLSH Status Inactive Delay TCLAV Address Valid ...

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A C TESTING INPUT OUTPUT WAVEFORM A C Testing Inputs are driven for a logic ‘‘1’’ and 0 45V for a logic ‘‘0’’ Timing measurements are made for both a logic ‘‘1’’ and logic ...

Page 24

WAVEFORMS (Continued) BUS TIMING MAXIMUM MODE SYSTEM (USING 8288) NOTES 1 All signals switch between V and RDY is sampled near the end Cascade address is valid between first ...

Page 25

WAVEFORMS (Continued) ASYNCHRONOUS SIGNAL RECOGNITION NOTE 1 Setup requirements for asynchronous signals only to guarantee recognition at next CLK REQUEST GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY) NOTE 1 The coprocessor may not drive the busses outside the region shown without ...

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Instruction Set Summary Mnemonic and Description DATA TRANSFER MOV Move e Register Memory to from Register Immediate to Register Memory Immediate to Register Memory to Accumulator Accumulator to Memory Register Memory to Segment Register Segment Register to ...

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Instruction Set Summary (Continued) Mnemonic and Description ARITHMETIC ADD Add e Reg Memory with Register to Either Immediate to Register Memory Immediate to Accumulator ADC Add with Carry e Reg Memory with Register to Either Immediate to Register ...

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Instruction Set Summary (Continued) Mnemonic and Description LOGIC Invert NOT e SHL SAL Shift Logical Arithmetic Left e SHR Shift Logical Right e SAR Shift Arithmetic Right e ROL Rotate Left e ROR Rotate Right e RCL ...

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Instruction Set Summary (Continued) Mnemonic and Description JMP Unconditional Jump e Direct Within Segment Direct Within Segment-Short Indirect Within Segment Direct Intersegment Indirect Intersegment RET Return from CALL e Within Segment Within Seg Adding Immed to SP Intersegment ...

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Instruction Set Summary (Continued) Mnemonic and Description PROCESSOR CONTROL CLC Clear Carry e CMC Complement Carry e STC Set Carry e CLD Clear Direction e STD Set Direction e CLI Clear Interrupt e STI Set Interrupt e ...

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