KU80960CA-25 Intel Corporation, KU80960CA-25 Datasheet
KU80960CA-25
Specifications of KU80960CA-25
Related parts for KU80960CA-25
KU80960CA-25 Summary of contents
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... Kbyte On-Chip Data RAM — Sustains 128 bits per Clock Access Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. ...
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HIGH-PERFORMANCE EMBEDDED PROCESSOR CONTENTS 1.0 PURPOSE .................................................................................................................................................. 1 2.0 80960CA OVERVIEW................................................................................................................................. 1 2.1 The C-Series Core ..............................................................................................................................2 2.2 Pipelined, Burst Bus ...........................................................................................................................2 2.3 Flexible DMA Controller ......................................................................................................................2 2.4 Priority Interrupt Controller ..................................................................................................................2 2.5 Instruction Set Summary ...
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CONTENTS LIST OF FIGURES Figure 1 80960CA Block Diagram .............................................................................................................. 1 Figure 2 80960CA PGA Pinout—View from Top (Pins Facing Down) ...................................................... 13 Figure 3 80960CA PGA Pinout —View from Bottom (Pins Facing Up) .................................................... 14 Figure 4 80960CA PQFP ...
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CONTENTS LIST OF FIGURES (continued) Figure 39 Using External READY ............................................................................................................... 55 Figure 40 Terminating a Burst with BTERM ............................................................................................... 56 Figure 41 BOFF Functional Timing ............................................................................................................ 57 Figure 42 HOLD Functional Timing ............................................................................................................ 58 Figure 43 DREQ and DACK ...
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PURPOSE This document provides electrical characteristics for the 33, 25 and 16 MHz versions of the 80960CA. For a detailed description of any 80960CA functional topic—other than parametric performance—consult the 80960CA Product Overview (Order No. 270669) or the i960 ...
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The C-Series Core The C-Series core is a very high performance microarchitectural implementation of the 80960 Core Architecture. The C-Series core can sustain execu- tion of two instructions per clock (66 MIPs at 33 MHz). To ...
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Instruction Set Summary Table 1 summarizes the 80960CA instruction set by logical groupings. See the i960 CA Microprocessor User’s Manual for a complete description of the instruction set. Data Arithmetic Movement Load Add Store Subtract Move Multiply Load Address ...
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PACKAGE INFORMATION 3.1 Package Introduction This section describes the pins, pinouts and thermal characteristics for the 80960CA in the 168-pin Ceramic Pin Grid Array (PGA) package and the 196- pin Plastic Quad Flat Package (PQFP). For ...
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Table 3. 80960CA Pin Description — External Bus Signals (Sheet Name Type A31:2 O ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most S significant address bit the least significant. During ...
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Table 3. 80960CA Pin Description — External Bus Signals (Sheet Name Type READY I READY is an input which signals the termination of a data transfer. READY is used to S(L) indicate that read ...
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Table 3. 80960CA Pin Description — External Bus Signals (Sheet Name Type BOFF I BUS BACKOFF, when asserted, suspends the current access and causes the bus S(L) pins to float. When BOFF is deasserted, the ADS signal ...
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Table 4. 80960CA Pin Description — Processor Control Signals (Sheet Name Type RESET I RESET causes the chip to reset. When RESET is asserted, all external signals A(L) return to the reset state. When ...
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Table 4. 80960CA Pin Description — Processor Control Signals (Sheet Name Type CLKIN I CLOCK INPUT is an input for the external clock needed to run the processor. The A(E) external clock is internally divided as prescribed ...
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Table 5. 80960CA Pin Description — DMA and Interrupt Unit Control Signals Name Type DREQ3:0 I DMA REQUEST causes a DMA transfer to be requested. Each of the four signals A(L) requests a transfer on a single ...
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Mechanical Data 3.3.1 80960CA PGA Pinout Tables 6 and 7 list the 80960CA pin names with package location. Figure 2 depicts the complete Table 6. 80960CA PGA Pinout — In Signal Order Address Bus Data Bus Signal Pin ...
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Table 7. 80960CA PGA Pinout — In Pin Order Pin Signal Pin Signal FAIL ONCE DREQ1 C6 V ...
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D25 D24 D21 D19 D17 D16 D15 2 D29 D27 D23 D20 D18 V D14 CC 3 READY D31 D26 D22 HOLDA BTERM D28 5 BE3 HOLD ...
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BOFF FAIL STEST ONCE DREQ0 NC 6 DREQ1 DREQ2 ...
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PQFP Pinout Tables 8 and 9 list the 80960CA pin names with package location. Figure 4 shows the 80960CA PQFP pinout as viewed from the top side. Table 8. 80960CA PQFP Pinout — In Signal Order Address Bus ...
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Table 9. 80960CA PQFP Pinout — In Pin Order Pin Signal Pin Signal D23 D22 ...
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Figure 4. 80960CA PQFP Pinout (View from Top Side) 80960CA-33, -25, - Pin 1 196 F_CA004A 17 ...
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Package Thermal Specifications The 80960CA is specified for operation when T (case temperature) is within the range may be measured in any environment to deter- C mine whether the 80960CA is within specified ...
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Table 11. 80960CA PGA Package Thermal Characteristics Thermal Resistance — °C/Watt Airflow — ft./min (m/sec) Parameter 0 200 (0) (1.01) Junction-to-Case (Case measured as 1.5 1.5 shown in Figure 5) Case-to-Ambient 17 14 (No Heatsink) Case-to-Ambient 13 9 (With Heatsink)* ...
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Stepping Register Information Upon reset, register g0 contains die stepping infor- mation. Figure 6 shows how g0 is configured. The most significant byte contains an ASCII 0. The upper middle byte contains an ASCII C. The ...
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ELECTRICAL SPECIFICATIONS 4.1 Absolute Maximum Ratings Parameter Maximum Rating Storage Temperature ................................–65 Case Temperature Under Bias .................–65 Supply Voltage wrt. V ............................. –0. 6.5V SS Voltage on Other Pins wrt. V ...........–0. 4.2 Operating ...
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DC Specifications (80960CA-33, -25, -16 under the conditions described in Section 4.2, Operating Conditions.) Symbol Parameter V Input Voltage for all pins except RESET Low IL V Input High Voltage for all pins except RESET IH ...
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AC Specifications Table 16. 80960CA AC Characteristics (33 MHz) (80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Input Clock (1,9) T CLKIN Frequency F T CLKIN Period C ...
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Table 16. 80960CA AC Characteristics (33 MHz) (Continued) (80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Relative Output Timings (1,2,3,8) T A31:2 Valid to ADS Rising ...
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Table 17. 80960CA AC Characteristics (25 MHz) (80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Input Clock (1,9) T CLKIN Frequency F T CLKIN Period C T CLKIN Period Stability ...
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Table 17. 80960CA AC Characteristics (25 MHz) (Continued) (80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Relative Output Timings (1,2,3,8) T A31:2 Valid to ADS Rising AVSH1 ...
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Table 18. 80960CA AC Characteristics (16 MHz) (80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Input Clock (1,9) T CLKIN Frequency F T CLKIN Period C T CLKIN Period Stability ...
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Table 18. 80960CA AC Characteristics (16 MHz) (Continued) (80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Relative Output Timings (1,2,3,8) T A31:2 Valid to ADS Rising AVSH1 ...
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AC Test Conditions The AC Specifications in Section 4.5 are tested with the 50 pF load shown in Figure 7. Figure 16 shows how timings vary with load capacitance. Specifications are measured at the 1.5V crossing point, unless otherwise ...
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PCLK2:1 Outputs Outputs Figure 10. Output Delay and Float Waveform PCLK2:1 Inputs: (READY, HOLD, BTERM, BOFF, DREQ3:0, D31:0 on reads) Figure 11. Input Setup and Hold Waveform OUTPUT DELAY - The maximum output delay ...
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PCLK2:1 1.5V NMI, XINT7:0 Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform 1.5V PCLK2:1 Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA T IH Min 1.5V HOLD HOLDA OUTPUT DELAY ...
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PCLK2:1 Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA T IH BOFF 1.5V Figure 14. Bus Backoff (BOFF) Timings 32 1.5V 1. Max Min Min 1.5V Valid 1.5V T ...
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PCLK2:1 ADS A31:2, BE3:0, W/R, LOCK, SUP, D/C, DMA D31:0 WAIT DT/R DEN D31:0 Figure 15. Relative Timings Waveforms 4.5.3 Derating Curves nom + 10 nom + 5 nom 50 100 Note: PCLK Load = 50pF Figure 16. Output ...
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C (pF All outputs except: LOCK, DMA, SUP, HOLDA, BREQ DACK3:0, EOP3:0/TC3:0, FAIL Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and ...
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RESET, BACKOFF AND HOLD ACKNOWLEDGE Table 19 lists the condition of each processor output pin while RESET is asserted (low). Table 19. Reset Conditions State During Reset Pins (HOLDA inactive) A31:2 Floating D31:0 Floating BE3:0 Driven high (Inactive) W/R ...
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BUS WAVEFORMS 36 Figure 19. Cold Reset Waveform ...
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Figure 20. Warm Reset Waveform 80960CA-33, -25, -16 37 ...
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Figure 21. Entering the ONCE State 38 ...
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CLKIN T IH RESET 1.5V PCLK2:1 (Case 1) Max Min PCLK2:1 (Case 2) Note: Case 1 and Case 2 show two possible polarities of PCLK2:1 Figure 22. Clock Synchronization in the 2-x Clock Mode 2x CLK 1.5V CLKIN T ...
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Byte Function Order Bit 31- Value 0.. PCLK ADS A31:4, SUP , DMA, D/C, BE3:0, LOCK BLAST DEN A3:2 WAIT D31:0 Figure 24. ...
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Byte Bus Function Order Width Bit 22 21 20-19 31- Value 0.. PCLK ADS A31:2, BE3:0 W/R BLAST DT/R DEN DMA, D/C, SUP, LOCK WAIT D31:0 Figure 25. Non-Burst, Non-Pipelined Read Request ...
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Byte Function Order Bit 22 21 31- Value 0.. PCLK ADS A31:2, BE3:0 W/R BLAST DT/R DEN SUP, DMA, D/C, LOCK WAIT D31:0 Figure 26. Non-Burst, Non-Pipelined Write Request With Wait ...
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Byte Bus Function Order Width Bit 22 21 20-19 31- 32-Bit Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK BLAST DEN 00 A3:2 WAIT D31:0 ...
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Byte Function Order Bit 22 21 31- Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0 Figure 28. Burst, Non-Pipelined Read Request ...
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Byte Bus Function Order Width Bit 22 21 20-19 31- 32-bit Value 0.. PCLK ADS A31:4, SUP , DMA, D/C, BE3:0, LOCK BLAST DEN A3:2 WAIT D31:0 ...
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Byte Function Order Bit 22 21 31- Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0 Figure 30. Burst, Non-Pipelined Write Request ...
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Byte Bus Function Order Width Bit 31- 20- 16-bit Value 0.. PCLK ADS SUP, DMA, D/C, LOCK, A31:4, BE3/BHE, BE0/BLE W/R BLAST DT/R DEN A3:2 A3 ...
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Byte Function Order Bit 22 21 31- Value 0.. PCLK ADS SUP, DMA, D/C, LOCK, A31:4 W/R BLAST DT/R DEN A3:2 BE1/A1, BE0/A0 WAIT D31:0 Figure 32. Burst, Non-Pipelined Read ...
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Byte Bus Function Order Width Bit 22 21 20-19 31- Value 0.. PCLK ADS A31:4, SUP, Valid DMA, D/C, LOCK W/R A3:2 Valid BE3:0 D31:0 WAIT BLAST DT/R DEN Non-Pipelined ...
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Byte Bus Function Order Width Bit 22 21 20-19 31- Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, LOCK W/R A3:2 BE3:0 D31:0 WAIT BLAST DT/R DEN Non-Pipelined Request Concludes ...
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Byte Bus Function Order Width Bit 31- 20- 32-bit Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R A3:2 00 D31:0 WAIT BLAST DT/R DEN Non-pipelined Request Concludes, Pipelined ...
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Byte Bus Function Order Width Bit 22 21 20-19 31- 32-bit Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R 00 A3:2 D31:0 WAIT BLAST DT/R DEN ...
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Byte Bus Function Order Width Bit 22 21 20-19 31- 16-bit Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE0/BLE, BE3/BHE, LOCK W/R A3 A3:2 BE1/A1 D31:0 ...
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Byte Bus Function Order Width Bit 31- 20- 8-bit Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, LOCK W/R A3:2 BE1/A1, A1 BE0/A0 D31:0 ...
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Quad-Word Read Request RAD RDD Ready Enabled PCLK ADS A31:4, SUP, DMA, INST, Valid D/C, BE3:0, LOCK W/R BLAST DT/R DEN READY BTERM A3 WAIT D0 D1 D31:0 Figure 39. Using ...
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PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0, LOCK W/R BLAST DT/R DEN READY BTERM A3:2 00 WAIT D31:0 Note: READY adds memory access time to data transfers, whether or not the bus access is a burst ...
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ADS BLAST READY BOFF SUSPEND REQUEST A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R D31:0, (WRITES) Begin Request BOFF may not be asserted Note: READY/BTERM must be enabled; N Figure 41. BOFF Functional Timing Regenerate ADS BURST BURST NON-BURST MAY ...
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Word Read Request N PCLK2:1 ADS A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R BLAST HOLD HOLDA Figure 42. HOLD Functional Timing 58 Word Read Request Hold State N = RAD RAD XDA N XDA ...
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PCLK2:1 ADS ! (BLAST & READY & !WAIT) (See Note) DACKx (All Modes) DREQx (Case 1) DREQx (Case 2) Note: 1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-By and some packing and unpacking modes in which ...
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PCLK2 DREQ ADS DACK TC Note: Terminal Count becomes active during the last bus request of a buffer transfer. If the last LOAD/STORE bus request is executed as multiple bus accesses, the TC will be active for ...
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Byte Offset Word Offset 0 1 Short Request (Aligned) Byte, Byte Requests Short-Word Load/Store Short Request (Aligned) Byte, Byte Requests Word Request (Aligned) Byte, Short, Byte, Requests Word Load/Store Double-Word Load/Store Figure 47. A Summary of Aligned and ...
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Byte Offset 0 1 Word Offset Triple-Word Load/Store Quad-Word Load/Store Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued One Three-Word Request (Aligned) ...
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Write Request N = WAD XDA Ready Disabled PCLK ADS A31:4, SUP, Valid DMA, INST, D/C, BE3:0 LOCK Valid W/R BLAST DT/R DEN A3:2 Valid WAIT D31:0 Out READY, BTERM Figure 49. Idle Bus Operation 80960CA-33, -25, ...
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REVISION HISTORY This data sheet supersedes data sheet 270727-005. Specification changes in the 80960CA data sheet are a result of design changes. The sections significantly changed since the previous revision are: Section Table 11. 80960CA PGA ...