PM7347-BI PMC-Sierra Inc, PM7347-BI Datasheet

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PM7347-BI

Manufacturer Part Number
PM7347-BI
Description
Saturn user network interface for L2/E3/T3
Manufacturer
PMC-Sierra Inc
Datasheet

Specifications of PM7347-BI

Case
BGA
Dc
03+

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
SATURN® USER NETWORK INTERFACE
for J2/E3/T3
S/UNI®-JET
Data Sheet
Issue 3: June 2001
PM7347
S/UNI
Released
JET
-
TM
S/UNI®-JET Data Sheet
Released

Related parts for PM7347-BI

PM7347-BI Summary of contents

Page 1

... SATURN® USER NETWORK INTERFACE Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 PM7347 S/UNI TM - JET S/UNI®-JET for J2/E3/T3 Data Sheet Released Issue 3: June 2001 S/UNI®-JET Data Sheet Released ...

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Legal Information Copyright © 2001 PMC-Sierra, Inc. The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written ...

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Contacting PMC-Sierra PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal ...

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Revision History Issue No. Issue Date 3 June 2001 2 March 2000 1 April 1999 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Details of Change Included Application examples, Description, and ...

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Table of Contents 1 Features.....................................................................................................................17 2 Applications ...............................................................................................................21 3 References ................................................................................................................22 4 Definitions ..................................................................................................................24 5 Application Examples ................................................................................................26 6 Block Diagram ...........................................................................................................28 7 Description.................................................................................................................29 8 Pin Diagram ...............................................................................................................32 9 Pin Description...........................................................................................................34 10 Functional Description ...............................................................................................54 10.1 DS3 Framer.......................................................................................................54 10.2 E3 ...

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Microprocessor Interface ..................................................................................76 11 Normal Mode Register Description............................................................................81 12 Test Features Description........................................................................................249 12.1 Test Mode 0 Details.........................................................................................251 12.2 JTAG Test Port ................................................................................................255 13 Operation .................................................................................................................259 13.1 Software Initialization Sequence.....................................................................259 13.2 Register Settings for Basic Configurations .....................................................260 13.3 PLCP Frame ...

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 S/UNI®-JET Data Sheet Released 7 ...

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List of Registers Register 300H: S/UNI-JET Configuration 1.......................................................................82 Register 301H: S/UNI-JET Configuration 2.......................................................................85 Register 302H: S/UNI-JET Transmit Configuration ...........................................................87 Register 303H: S/UNI-JET Receive Configuration............................................................89 Register 304H: S/UNI-JET Data Link and FERF/RAI Control...........................................91 Register 305H: S/UNI-JET Interrupt Status.......................................................................95 Register 006H: S/UNI-JET ...

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Register 324H: CPPM Framing Error Event Count LSB .................................................124 Register 325H: CPPM Framing Error Event Count MSB ................................................124 Register 326H: CPPM FEBE Count LSB ........................................................................125 Register 327H: CPPM FEBE Count MSB .......................................................................125 Register 330H: DS3 FRMR Configuration.......................................................................126 Register 331H: DS3 ...

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Register 353H: RDLC Data .............................................................................................180 Register 354H: RDLC Primary Address Match ...............................................................181 Register 355H: RDLC Secondary Address Match ..........................................................182 Register 358H: TDPR Configuration ...............................................................................183 Register 359H: TDPR Upper Transmit Threshold ...........................................................185 Register 35AH: TDPR Lower Interrupt Threshold ...........................................................186 Register 35BH: ...

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Register 390H: TTB Control ............................................................................................222 Register 391H: TTB Trail Trace Identifier Status .............................................................224 Register 392H: TTB Indirect Address..............................................................................225 Register 393H: TTB Indirect Data ...................................................................................226 Register 394H: TTB Expected Payload Type Label ........................................................227 Register 395H: TTB Payload Type Label Control/Status ................................................228 ...

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List of Figures Figure 1 S/UNI-JET Operating as an ATM PHY in an ATM Switch ................................26 Figure 2 S/UNI-JET Operating as a Framer Device in Frame Relay Equipment............27 Figure 3 Block Diagram ...................................................................................................28 Figure 4 Framing algorithm (CRC_REFR = 0) ...

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Figure 34 Receive Unipolar E3 Stream.........................................................................297 Figure 35 Receive Bipolar J2 Stream ...........................................................................297 Figure 36 Receive Unipolar J2 Stream .........................................................................298 Figure 37 Generic Receive Stream ...............................................................................298 Figure 38 Receive DS3 Overhead ................................................................................299 Figure 39 Receive G.832 E3 Overhead ........................................................................300 Figure ...

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Figure 69 Framer Mode J2 Transmit Input Stream .......................................................315 Figure 70 Framer Mode J2 Transmit Input Stream With TGAPCLK.............................315 Figure 71 Framer Mode J2 Receive Output Stream .....................................................316 Figure 72 Framer Mode J2 Receive Output Stream with RGAPCLK ...........................316 Figure ...

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List of Tables Table 1 Supported Operating Formats............................................................................17 Table 2 Transmission System Sublayer Processing Acceptance and Output ................29 Table 3 Summary of Receive Detection Features ..........................................................29 Table 4 Multiframe Format ..............................................................................................58 Table 5 C1 Octet Pattern.................................................................................................74 Table 6 Register Memory ...

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Table 34 PLCP Overhead Processing ..........................................................................264 Table 35 PLCP Path Overhead Identifier Codes ..........................................................266 Table 36 DS3 PLCP Trailer Length...............................................................................266 Table 37 E3 PLCP Trailer Length .................................................................................267 Table 38 DS3 Frame Overhead Operation ...................................................................268 Table 39 G.751 E3 Frame Overhead ...

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Features The S/UNI®-JET is a single chip Asynchronous Transfer Mode (ATM) User Network Interface (UNI) operating at 44.736 Mbit/s, 34.368 Mbit/s, and 6.312 Mbit/s that: • Conforms to AF-Physical (PHY)-0054.000, AF-PHY-0034.000 and AF-PHY-0029.000. • Implements ATM Direct Cell Mapping ...

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Uses the PMC-Sierra™ PM4351 COMET, PM4341 T1XC and PM6341 E1XC T1 and E1 framer/line interface chips for DS1 and E1 applications. • Provides programmable pseudo-random test pattern generation, detection, and analysis features. • Provides integral transmit and receive HDLC ...

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Provides cell descrambling, header check sequence (HCS) error detection, idle cell filtering, header descrambling (for use with PPP packets), and accumulates the number of received idle cells, the number of received cells written to the FIFO, and the number ...

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Provides programmable pseudo-random test sequence generation ( bit length • sequences conforming to ITU-T O.151 standards). Diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from ...

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Applications • ATM or SMDS Switches, Multiplexers, and Routers • SONET/SDH Mux E3/DS3 Tributary Interfaces • PDH Mux J2/E3/DS3 Line Interfaces • DS3/E3/J2 Digital Cross Connect Interfaces • DS3/E3/J2 PPP Internet Access Interfaces • DS3/E3/J2 Frame Relay Interfaces • ...

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References • ANSI T1.627 - 1993, "Broadband ISDN - ATM Layer Functionality and Specification". • ANSI T1.107a - 1990, "Digital Hierarchy - Supplement to Formats Specifications (DS3 Format Applications)". • ANSI T1.107 - 1995, "Digital Hierarchy - Formats Specifications". ...

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ITU-T Recommendation G.832 - "Transport of SDH Elements on PDH Networks: Frame and Multiplexing Structures", 1993. • ITU-T Recommendation Q.921 - "ISDN User-Network Interface - Data Link Layer Specification", March, 1993. • NTT Technical Reference, "NTT Technical Reference for ...

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Definitions The following table defines the abbreviations for the S/UNI-JET. AIC Application Identification Channel AIS Alarm Indication Signal ATM Asynchronous Transfer Mode BIP Bit Interleaved Parity CMOS Complementary Metal Oxide Semiconductor COFA Change of Frame Alignment CPERR Path Parity ...

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RAI Receive Alarm Indication RBOC Bit Oriented Code Detector RDLC Data Link Receiver RED Receive Error Detection SBGA Super Ball Grid Array TM SATURN® Compatible Interface Specification for PHY and ATM SCI-PHY layer devices SMDS Switched Multi-Megabit Data Service SONET ...

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... PM7344 QDSX S/UNI-MPH J2/E3/T3 Line Card J2/E3/T3 LIU PM7347 S/UNI-JET As a J2/E3/T3 framer, the S/UNI-JET can be used in router, frame relay switch, and multiplexer applications. Refer to Figure 2. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 S/UNI®-JET Data Sheet ...

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... Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 PM7366 IP Switch/Router Core Switch Fabric PM7366 Packet Processor Memory PM7364 FREEDM- 32 S/UNI®-JET Data Sheet Released Uplink Side Unchannelized J2/E3/T3 Card J2/E3/T3 LIU PM7347 PM7366 S/UNI- FREEDM-8 JET 27 ...

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Block Diagram Figure 3 Block Diagram XBOC Tx FEAC TPOS/TDATO Line TNEG/TOHM Encode TCLK RCLK Line RPOS/RDATI Decode RNEG/RLCV/ROHM RBOC RDLC Rx Rx FEAC HDLC Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: ...

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Description The PM7346 S/UNI-JET is an ATM physical layer processor with integrated DS3, E3, and J2 framers. It supports PLCP sublayer DS1, DS3, E1, and E3 processing and ATM cell delineation. The S/UNI-JET contains: • An Integral DS3 framer ...

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Transmission System Sublayer Processing J2 In the E3 receive direction, the S/UNI-JET frames to G.751 and G.832 E3 signals with a maximum average reframe times of 135 µs for G.751 frames and 250 µs for G.832 frames. LCVs, LOS, framing ...

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The S/UNI-JET provides cell delineation for ATM cells using the PLCP framing format using the header check sequence octet in the ATM cell header as specified by ITU-T Recommendation I.432. DS1, DS3, E1, and E3-based PLCP frame formats ...

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Pin Diagram The S/UNI-JET is packaged in a 256-pin SBGA package with a body size and a pin pitch of 1.27 mm. Quadrant A11/A20 to K11/K20 VSS VSS VSS ...

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Quadrant L11/L20 to Y11/Y20 PHY_ADR[1] PHY_ADR[0] ATMB VSS RCA P RFCLK RADR[2] R VDD VDD T RDAT[15] RDAT[14] U RDAT[11] RDAT[10] V VSS VDD W VSS VDD Y VSS VSS 20 19 Quadrant ...

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Pin Description Pin Name Type TPOS Output TDATO TNEG Output TOHM Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. C6 The Transmit Digital Positive Pulse (TPOS) contains ...

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Pin Name Type TCLK Output RPOS Input RDATI Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. By default, both TNEG and TOHM are updated on the falling edge ...

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Pin Name Type RNEG Input RLCV ROHM RCLK Input TOHINS Input Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. C5 The Receive Digital Negative Pulse (RNEG) contains the ...

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Pin Name Type TOH Input TOHFP Output TOHCLK Output REF8KI Input Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. H3 When configured for DS3 operation, Transmit DS3/E3/J2 Overhead ...

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Pin Name Type TPOHINS Input TPOH Input TDATI Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. V14 The Transmit Path Overhead Insertion (TPOHINS) controls the insertion of PLCP ...

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Pin Name Type TPOHFP Output TFPO TMFPO TGAPCLK Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. W14 The Transmit Path Overhead Frame Position (TPOHFP) is valid when the ...

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Pin Name Type TCELL TPOHCLK Output TIOHM Input TFPI TMFPI Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. The Transmit Cell Indication (TCELL) is valid when the TCELL ...

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Pin Name Type TICLK Input ROHFP Output ROH Output ROHCLK Output Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. V15 The Transmit Input Clock (TICLK) provides the transmit ...

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Pin Name Type REF8KO Output RPOHFP RFPO RMFPO RPOH Output ROVRHD Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. U12 The Reference 8kHz Output (REF8KO 8kHz ...

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Pin Name Type RPOHCLK Output RSCLK RGAPCLK LCD Output RDATO FRMSTAT Output ATM8 Input Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. W13 The Receive PLCP Overhead Clock ...

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Pin Name Type TDAT[15] Input TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TPRTY Input TSOC Input TENB Input Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: ...

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Pin Name Type TADR[2] Input TADR[1] TADR[0] TCA Output TFCLK Input Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. F18 The Transmit Address (TADR[2:0]) bus is used for ...

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Pin Name Type DTCA Output RDAT[15] Output RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin ...

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Pin Name Type RPRTY Output RSOC Output RENB Input RADR[2] Input RADR[1] RADR[0] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. R18 The Receive Parity (RPRTY) signal indicates ...

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Pin Name Type RCA Output RFCLK Input DRCA Output PHY_ADR[2] Input PHY_ADR[1] PHY_ADR[0] CSB Input Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 Pin Function No. N19 The Receive Multi-PHY Cell ...

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Pin Name Type WRB Input RDB Input D[7] I/O D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[10] Input A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RSTB Input ALE Input INTB Output TCK Input TMS Input TDI Input ...

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Pin Name Type TDO Output TRSTB Input BIAS Input VDD[1] Power VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] VDD[9] VDD[10] VDD[11] VDD[12] VDD[13] VDD[14] VDD[15] VDD[16] VDD[17] VDD[18] VDD[19] VDD[20] VDD[21] VDD[22] VDD[23] VDD[24] VDD[25] VDD[26] VDD[27] VDD[28] VDD[29] VDD[30] ...

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Pin Name Type VSS[1] Ground VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] ...

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Pin Name Type VSS[50] Ground VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] NC[1] No Connect NC[2] NC[3] NC[4] NC[5] NC[6] NC[7] NC[8] NC[9] NC[10] NC[11] NC[12] NC[13] NC[14] NC[15] NC[16] NC[17] NC[18] NC[19] NC[20] NC[21] NC[22] NC[23] NC[24] ...

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Pin Name Type NC[45] No Connect NC[46] NC[47] NC[48] NC[49] NC[50] NC[51] NC[52] Notes 1. All S/UNI-JET inputs and bi-directionals present minimum capacitive loading and operate at TTL logic levels. 2. All S/UNI-JET outputs and bi-directionals have at least 3 ...

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Functional Description The S/UNI-JET contains the following blocks: • DS3, E3, J2 Framer • DS3, E3, J2 Transmitter • RBOC Bit oriented code detector and XBOC Bit oriented code detector • RDLC PMDL receiver and TDPR PMDL transmitter • ...

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While the T3-FRMR is synchronized to the DS3 M-frame, the F-bit and M-bit positions in the DS3 stream are examined. An OOF defect is detected when three F-bit errors out of eight or 16 consecutive F-bits are observed (as selected ...

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Valid X-bits are extracted by the T3-FRMR to provide indication of far end receive failure (FERF). A FERF defect is detected if the extracted X-bits are equal and are logic zero (X1=X2=0); the defect is removed if the extracted X-bits ...

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The Payload Type bits and buffers them so that they can be read by the microprocessor. • The Timing Marker bit and asserts the Timing Marker indication when the value of the extracted bit has been in the same ...

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E3 LOF detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1 ms ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an OOF condition ...

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The J2-FRMR frames signal with an average reframe time of 5.07 ms. An alternate framing algorithm that uses the CRC-5 check to detect static mimic patterns is also available. Once in frame, the J2-FRMR provides indications of ...

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When the CRC_REFR bit is set to logic zero, the J2-FRMR uses only the frame alignment sequence to find frame, searching for three consecutive correct frame alignment sequences. The frame find block searches for the entire 9-bit sequence (spread over ...

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Figure 5 Framing Algorithm (CRC_REFR = 1) Reset or Out of Fram e Using this algorithm, the J2-FRMR will find frame in 10.22 ms, on average when starting the search in the worst possible position, given a 10 algorithm will ...

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J2 extended LOF detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1 ms ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an OOF ...

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The Status Register contains bits that indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and ...

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When in frame, the SPLR extracts the path overhead octets and outputs them bit serially on output RPOH, along with the RPOHCLK and RPOHFP outputs. Framing octet errors and path overhead identifier octet errors are indicated as frame errors. Bit ...

Page 65

Figure 6 Cell delineation State Diagram HUNT ALPHA consecutive incorrect HCS's (cell by cell) The values of ALPHA and DELTA determine the robustness of the delineation method. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines ...

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The PRGD can be programmed to generate any pseudo-random pattern with length bits or any user programmable bit pattern from bits in length. The PRGD can also insert single bit errors or a bit ...

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The RXCP-50 descrambles the cell payload field using the self synchronizing descrambler with a 43 polynomial The header portion of the cells can optionally be descrambled also. Note: Cell payload scrambling is enabled by default in ...

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Figure 7 HCS Verification State Diagram No Errors Detected (Pass Cell) DELTA consecutive correct HCS's (From PRES YNC state) In normal operation, the HCS verification state machine remains in the 'Correction' state. Incoming cells containing no HCS errors are passed ...

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Filling the receive FIFO. • Indicating when the receive FIFO contains cells. • Maintaining the receive FIFO read and write pointers. • Detecting FIFO overrun and underrun conditions. The FIFO interface is “UTOPIA Level 2"-compliant. It accepts a read ...

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When enabled for M23 operation, the C-bits are forced to logic one with the exception of the C- bit Parity ID bit (first C-bit of the first M-subframe), which is forced to toggle every M-frame. The T3-TRAN supports diagnostic modes ...

Page 71

In G.751 E3 mode, the E3-TRAN : • Inserts the RAI bit (bit 11 of the frame) either via a register bit or, optionally, when the E3-FRMR declares OOF. • Inserts the National Use reserved bit (bit 12 of the ...

Page 72

XBOC Bit Oriented Code Generator The Bit Oriented Code Generator (XBOC) Block transmits 63 of the possible 64 bit oriented codes (BOC) in the C-bit parity FEAC channel. A BOC is a 16-bit sequence consisting of eight ones, a ...

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Abort sequences (01111111 sequence where the 0 is transmitted first) can be continuously transmitted at any time by setting a control bit. During packet transmission, an underrun situation can occur if data is not written to the TDPR Transmit Data ...

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Table 5 C1 Octet Pattern Stuff Length The SPLT block generates a stuff length pattern of 18, 19 octets determined by the phase alignment of the start of the G.751 E3 frame and ...

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Maintaining the transmit FIFO read and write pointers. • Detecting a FIFO overrun condition. The FIFO interface is “UTOPIA Level 2” compliant and accepts a write clock (TFCLK), a write enable signal (TENB), the start of a cell (TSOC) ...

Page 76

The S/UNI-JET identification code is 073460CD hexadecimal. 10.23 Microprocessor Interface The microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. Normal mode registers are required for normal operation. Test mode ...

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Address Register 31AH PMON Parity Error Event Count LSB 31BH PMON Parity Error Event Count MSB 31CH PMON Path Parity Error Event Count LSB 31DH PMON Path Parity Error Event Count MSB 31EH PMON FEBE/J2-EXZS Event Count LSB 31FH PMON ...

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Address Register 349H J2 FRMR Error/X-bit Interrupt Status 34AH-34BH J2 FRMR Reserved 34CH J2 TRAN Configuration 34DH J2 TRAN Diagnostics 34EH J2 TRAN TS97 Signaling 34FH J2 TRAN TS98 Signaling 350H RDLC Configuration 351H RDLC Interrupt Control 352H RDLC Status ...

Page 79

Address Register 380H TXCP-50 Configuration 1 381H TXCP-50 Configuration 2 382H TXCP-50 Transmit Cell Status 383H TXCP-50 Interrupt Enable/Status 384H TXCP-50 Idle Cell Header Control 385H TXCP-50 Idle Cell Payload Control 386H TXCP-50 Transmit Cell Counter LSB 387H TXCP-50 Transmit ...

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Address Register 40CH S/UNI-JET Identification Register 40DH - 7FFH Reserved for S/UNI-JET Test Notes 1. For all register accesses, CSB must be low. 2. Writing any value to any of the PMON(314H to 31FH), RXCP-50(369H to 370H) or TXCP-50(386H to ...

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Normal Mode Register Description Normal mode registers are used to configure and monitor the operation of the S/UNI-JET . Normal mode registers (as opposed to test mode registers) are selected when A[10] is low. Notes on Normal Mode Register ...

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Register 300H: S/UNI-JET Configuration 1 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W PLOOP The PLOOP bit controls the DS3, E3, or ...

Page 83

LOOPT The LOOPT bit selects the transmit timing source. When a logic one is written to LOOPT, the transmitter is loop-timed to the receiver. When loop timing is enabled, the receive clock (RCLK) is used as the transmit timing source. ...

Page 84

DS27_53 The DS27_53 bit is used to select between the long data structure (27-byte words in 16-bit mode and 53-byte words in 8-bit mode) and the short data structure (26-byte words in 16-bit mode and 52-byte words in 8-bit mode) ...

Page 85

Register 301H: S/UNI-JET Configuration 2 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W RXMFPO The RXMFPO bit controls which of the outputs ...

Page 86

TXMFPI The TXMFPI bit controls which of the inputs TMFPI or TFPI is valid. If TXMFPI is a logic one, then TMFPI will be expected. If TXMFPI is a logic zero, then TFPI will be expected. This bit is effective ...

Page 87

Register 302H: S/UNI-JET Transmit Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TNEGINV The TNEGINV bit provides polarity control for outputs ...

Page 88

TICLK The TICLK bit selects the transmit clock used to update the TPOS/TDATO and TNEG/TOHM outputs. When a logic zero is written to TICLK, the buffered version of the input transmit clock, TCLK, is used to update TPOS/TDATO and TNEG/TOHM ...

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Register 303H: S/UNI-JET Receive Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W RNEGINV The RNEGINV bit provides polarity control for input ...

Page 90

LOFINT[1:0] The LOFINT[1:0] bits determine the integration period used for asserting and de-asserting E3 and DS3 LOF or J2 extended LOF on the FRMLOF register bit of the S/UNI-JET FRMR LOF Status Register (x9CH) and on the FRMSTAT[4:1] output pins ...

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Register 304H: S/UNI-JET Data Link and FERF/RAI Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W DLINV The DLINV bit provides polarity ...

Page 92

For G.751 E3 streams, the National Use bit is sourced by the TDPR block if TNETOP and the NATUSE bit (from the E3 TRAN Configuration Register 341H) are both logic zero. If either TNETOP or NATUSE is logic one, the ...

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RBLEN The RBLEN bit enables: the receive RED alarm (persistent OOF) indication to automatically generate a FERF indication in the DS3 transmit stream BIP8 error detection in the E3 G.832 Framer to generate a FEBE indication in the ...

Page 94

LCDEN The LCDEN bit enables the receive-out-of-cell-delineation indication to automatically generate a FERF indication (RAI in G.751 or J2 mode) in the transmit stream. This bit operates regardless of framer selected (DS3, E3, or J2) but only in ATM mode. ...

Page 95

Register 305H: S/UNI-JET Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R SPLRI/TTBI, TXCP50I, RXCP50I, RBOCI/PRGDI, FRMRI/LOFI, PMONI, TDPRI, RDLCI These ...

Page 96

Register 006H: S/UNI-JET Identification, Master Reset, and Global Monitor Update Bit Type Bit 7 R/W Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R This register is used ...

Page 97

Register 307H: S/UNI-JET Clock Activity Monitor and Interrupt Identification Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R RFCLKA The RFCLKA bit monitors ...

Page 98

Register 308H: SPLR Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 Bit 0 R/W EXT The EXT bit disables the internal transmission system sublayer timeslot ...

Page 99

FORM[1:0] The FORM[1:0] bits select the PLCP frame format as shown below. These bits must be set to “11” direct mapped mode is being used (PLCPEN=0 and EXT=1). Refer to Table 11. Table 11 SPLR FORM[1:0] Configurations FORM[1] ...

Page 100

Register 309H: SPLR Interrupt Enable Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W OOFE The OOFE bit enables interrupt generation when a PLCP ...

Page 101

FEBEE The FEBEE bit enables interrupt generation when the S/UNI-JET detects a PLCP FEBE. The interrupt is enabled when a logic one is written. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue ...

Page 102

Register 30AH: SPLR Interrupt Status Bit Type Bit 7 Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R OOFI The OOFI bit is set to logic one when ...

Page 103

COLSSI The COLSSI bit is set to logic one when a PLCP change of link status signal code is detected. The link status signal code is contained in the path status octet (G1). Link status signal codes are required in ...

Page 104

Register 30BH: SPLR Status Bit Type Bit 7 Bit 6 R Bit 5 R Bit 4 R Bit 3 Bit 2 R Bit 1 R Bit 0 R OOFV The OOFV bit indicates the current PLCP OOF defect state. When ...

Page 105

LSS[2:0] The LSS[2:0] bits contain the current link status signal code. Link status signal codes are required in systems implementing the IEEE-802.6 DQDB protocol. LSS[2:0] is updated when two consecutive and identical link status signal codes are received. Proprietary and ...

Page 106

Register 30CH: SPLT Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 Bit 0 R/W EXT The EXT bit disables the internal transmission system sublayer timeslot ...

Page 107

FIXSTUFF The FIXSTUFF bit controls the transmit PLCP frame octet/nibble stuffing used for DS3 and G.751 E3 PLCP frame formats. When a logic zero is written to FIXSTUFF, stuffing is determined by the REF8KI input. When a logic one is ...

Page 108

FORM[1] FORM[ Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 PLCP or ATM direct-mapped Framing Format / Cell alignment DS1 / byte E1 / byte S/UNI®-JET Data ...

Page 109

Register 30DH: SPLT Control Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W SRCC1 The SRCC1 bit value ORed with input TPOHINS selects the ...

Page 110

SRCB1 The SRCB1 bit value ORed with input TPOHINS selects the source for the B1 octet on a bit by bit basis. If the OR results in a logic zero, the internally calculated bit interleaved parity value is inserted in ...

Page 111

Register 30EH: SPLT Diagnostics and G1 Octet Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LSS[2:0] The LSS[2:0] bits control the value ...

Page 112

DPFRM The DPFRM bit controls the insertion of parity errors in the path overhead identification (POHID) octets. When DPFRM is written with a logic one, a parity error is inserted in each POHID octet. When DPFRM is written with a ...

Page 113

Register 30FH: SPLT F1 Octet Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W F1[7:0] The F1[7:0] bits contain the value inserted in ...

Page 114

Register 310H: Change of PMON Performance Meters Bit Type Bit 7 Bit 6 Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R FEBECH The FEBECH bit is set to logic one ...

Page 115

Register 311H: PMON Interrupt Enable/Status Bit Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 R/W Bit 1 R Bit 0 R OVR The OVR bit indicates the overrun status of the PMON holding registers. A ...

Page 116

Register 314H: PMON LCV Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 315H: PMON LCV Event Count MSB ...

Page 117

Register 316H: PMON Framing Bit Error Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R 317H: PMON Framing Bit Error ...

Page 118

Register 318H: PMON Excessive Zero Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 319H: PMON Excessive Zero Count MSB ...

Page 119

Register 31AH: PMON Parity Error Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 31BH: PMON Parity Error Event ...

Page 120

Register 31CH: PMON Path Parity Error Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 31DH: PMON Path Parity ...

Page 121

Register 31EH: PMON FEBE/J2-EXZS Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 31FH: PMON FEBE/J2-EXZS Event Count MSB ...

Page 122

Register 321H: CPPM Change of CPPM Performance Meters Bit Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 R Bit 1 R Bit 0 R BIPECH The BIPECH bit is set to logic one if one ...

Page 123

Register 322H: CPPM B1 Error Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 323H: CPPM B1 Error Count MSB ...

Page 124

Register 324H: CPPM Framing Error Event Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 325H: CPPM Framing Error Event ...

Page 125

Register 326H: CPPM FEBE Count LSB Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Register 327H: CPPM FEBE Count MSB Bit Type ...

Page 126

Register 330H: DS3 FRMR Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W CBE The CBE bit enables the DS3 C-bit parity ...

Page 127

M3O8 The M3O8 bit controls the DS3 OOF decision criteria. When a logic one is written to M3O8, DS3 OOF is declared when three of eight framing bits (F-bits) are in error. When a logic zero is written to M3O8, ...

Page 128

Register 331H: DS3 FRMR Interrupt Enable (ACE=0) Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LOSE The LOSE bit enables interrupt generation ...

Page 129

REDE The REDE bit enables an interrupt to be generated when a change of state of the DS3 RED indication occurs. The DS3 RED indication is visible in the REDV bit location of the DS3 FRMR Status Register. When REDE ...

Page 130

Register 331H: DS3 FRMR Additional Configuration Register (ACE=1 in Register 333H) Bit Type Bit 7 Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W DALGO The DALGO bit determines ...

Page 131

EXZSO The EXZSO bit enables only summed zero occurrences to be accumulated in the PMON EXZS Count Registers. When EXZSO is set to logic one, any excessive zeros occurrences over an 85 bit period increments the PMON EXZS counter by ...

Page 132

AISONES The AISONES bit controls the pattern used to detect the AIS (AIS) when both AISPAT and AISC bits in DS3 FRMR Configuration Register are logic zero; if either AISPAT or AISC are logic one, the AISONES bit is ignored. ...

Page 133

Register 332H: DS3 FRMR Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R LOSI The LOSI bit is set to logic ...

Page 134

REDI The REDI bit indicates that a change of state of the DS3 RED indication has occurred. The DS3 RED indication is visible in the REDV bit location of the DS3 FRMR Status Register. When the REDI bit is a ...

Page 135

Register 333H: DS3 FRMR Status Bit Type Bit 7 R/W Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R LOSV The LOSV bit indicates the current LOS defect ...

Page 136

CBITV The CBITV bit indicates the application identification channel (AIC) state. CBITV is set to logic one (indicating the presence of the C-bit parity application) when the AIC bit is set high for 63 consecutive M-frames. CBITV is set to ...

Page 137

Register 334H: DS3 TRAN Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 Bit 1 Bit 0 R/W CBIT The CBIT bit enables the DS3 C-bit parity application. When ...

Page 138

CBTRAN The CBTRAN bit controls the C-bit values during AIS transmission. When CBTRAN is written with a logic zero, the C-bits are overwritten with zeros during AIS transmission as specified in ANSI T1.107. When CBTRAN is written with a logic ...

Page 139

Register 335H: DS3 TRAN Diagnostic Bit Type Bit 7 R/W Bit 6 R/W Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W DFEBE The DFEBE bit controls the insertion of FEBEs in ...

Page 140

DLCV The DLCV bit controls the insertion of a single LCV in the DS3 stream. When DLCV is written with a logic one, a LCV is inserted by generating an incorrect polarity of violation in the next B3ZS signature. The ...

Page 141

Register 338H: E3 FRMR Framing Options Bit Type Bit 7 Unused Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W REFR A transition from logic zero to logic one ...

Page 142

UNI The UNI bit selects the mode of the receive data interface. When UNI is logic one, the E3- FRMR expects unipolar data on the RDATI input and accepts LCV indications on the RLCV input. When UNI is logic zero, ...

Page 143

Register 339H: E3 FRMR Maintenance Options Bit Type Bit 7 Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TMARKDET The TMARKDET bit determines the persistency check performed on ...

Page 144

WORDERR The WORDERR bit selects whether the framing bit error indication pulses accumulated in PMON indicate all bit errors in the framing pattern or only one error for one or more errors in the framing pattern. When WORDERR is logic ...

Page 145

Register 33AH: E3 FRMR Framing Interrupt Enable Bit Type Bit 7 Bit 6 Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W OOFE The OOFE bit is an interrupt enable. When OOFE ...

Page 146

Register 33BH: E3 FRMR Framing Interrupt Indication and Status Bit Type Bit 7 Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R OOF The OOF bit indicates the ...

Page 147

COFAI The COFAI bit indicates that a change of frame alignment between the previous alignment and the newly found alignment has occurred. When COFAI is logic one, the last high-to-low transition on the OOF signal resulted in the new frame ...

Page 148

Register 33CH: E3 FRMR Maintenance Event Interrupt Enable Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W NATUSEE The NATUSEE bit is an ...

Page 149

FERFE The FERFE bit is an interrupt enable. When FERFE is logic one, an interrupt is generated on the INTB output when the Far End Receive Failure indication bit (bit 1 of the G.832 Maintenance and Adaptation byte), or when ...

Page 150

Register 33DH: E3 FRMR Maintenance Event Interrupt Indication Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R NATUSEI The NATUSEI bit is a ...

Page 151

FERFI The FERFI bit is a transition indication. When FERFI is logic one, a change of state of the Far End Receive Failure indication bit (bit 1 of the G.832 Maintenance and Adaptation byte), or when the RAI bit (bit ...

Page 152

Register 33EH: E3 FRMR Maintenance Event Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R NATUSE The NATUSE bit reflects the state ...

Page 153

AISD The AISD bit reflects the state of the AIS detection circuitry. When AISD is logic one, less than eight zeros (in G.832 mode), or less than 5 zeros (in G.751 mode), were detected during one complete frame period while ...

Page 154

Register 340H: E3 TRAN Framing Options Bit Type Bit 7 Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W FORMAT[1:0] The FORMAT[1:0] bits determine the framing mode used for ...

Page 155

Register 341H: E3 TRAN Status and Diagnostic Options Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W NATUSE The NATUSE bit determines the default ...

Page 156

DFERR The DFERR bit selects whether the framing pattern is corrupted for diagnostic purposes. When DFERR is logic one, the framing pattern inserted into the output data stream is inverted. When DFERR is logic zero, the unaltered framing pattern inserted ...

Page 157

Register 342H: E3 TRAN BIP-8 Error Mask Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W MBIP[7:0] The MBIP[7:0] bits act as an ...

Page 158

Register 343H: E3 TRAN Maintenance and Adaptation Options Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TIMEMK The TIMEMK bit determines the ...

Page 159

FERF/RAI The FERF/RAI bit reflects the value to be inserted in the Far End Receive Failure indication bit (bit 1 of the G.832 Maintenance and Adaptation byte), or the value of the RAI bit (bit 11 of the frame in ...

Page 160

Register 344H: J2-FRMR Configuration Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W UNI When the UNI bit is set to logic zero, the ...

Page 161

SFRME When the Single Framing Bit Error (SFRME) bit is set to logic one, then the J2-FRMR will indicate (to the PMON) a single framing error for every J2 multi-frame which contains one or more framing errors. When the SFRME ...

Page 162

Register 345H: J2-FRMR Status Bit Type Bit 7 R Bit 6 R Bit 5 Bit 4 R Bit 3 R Bit 2 Bit 1 R Bit 0 R LOS, LOF, RAI, RLOF, PHYAIS, PLDAIS These register bits reflect the current ...

Page 163

Register 346H: J2-FRMR Alarm Interrupt Enable Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LOSE When LOSE is logic one, the J2-FRMR ...

Page 164

RLOF_THR The RLOF Threshold bit determines the number of consecutive a-bits that are required for the state of RLOF to change. When RLOF_THR is logic zero, RLOF is asserted when the a-bit has been logic one for three consecutive frames, ...

Page 165

Register 347H: J2-FRMR Alarm Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 Bit 1 R Bit 0 R LOSI The LOSI bit is set to logic one ...

Page 166

PLDAISI The PLDAISI bit is set to logic one if a change in the condition of PLDAIS occurs. PLDAISI is cleared when this register is read. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: ...

Page 167

Register 348H: J2-FRMR Error/Xbit Interrupt Enable Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 Bit 1 R/W Bit 0 R/W CRCEE When CRCEE is logic one, the J2-FRMR will ...

Page 168

XBIT_DEB When XBIT_DEB is set to logic zero, the x-bit indications in the J2-FRMR Error/Xbit Interrupt Status Register reflect the most recent value of the x-bits. When XBIT_DEB is set to logic one, the x-bit indications change value only when ...

Page 169

Register 349H: J2-FRMR Error/Xbit Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R CRCEI The CRCEI bit is set to logic ...

Page 170

X1, X2, X3 The X1, X2, and X3 bits reflect the most recent (debounced if XBIT_DEB is set to logic one) value of bits 785, 786, and 787 respectively of frame three of each multiframe. These bits are the spare ...

Page 171

Register 34CH: J2-TRAN Configuration Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W RLOF The RLOF bit controls the state of the A-bit. When ...

Page 172

Register 34DH: J2-TRAN Diagnostic Bit Type Bit 7 Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W DFERR The DFERR bit controls the insertion of framing alignment signal errors. ...

Page 173

Register 34EH: J2-TRAN TS97 Signaling Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TS97[1:8] The TS97[1:8] bits control what is inserted into ...

Page 174

Register 34FH: J2-TRAN TS98 Signaling Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W TS98[1:8] The TS98[1:8] bits control what is inserted into ...

Page 175

Register 350H: RDLC Configuration Bit Type Bit 7 Bit 6 Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W EN The EN bit controls the overall operation of the RDLC. When EN ...

Page 176

Reserved This register bit should be set to logic zero for proper operation. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-1990267, Issue 3 S/UNI®-JET Data Sheet Released 176 ...

Page 177

Register 351H: RDLC Interrupt Control Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W INTC[6:0] The INTC[6:0] bits control the assertion of FIFO ...

Page 178

Register 352H: RDLC Status Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Consecutive reads of the RDLC Status and Data Registers should ...

Page 179

PBS[2:0] Data Status 010 The data byte read from the FIFO is the dummy byte that was written into the FIFO when the HDLC abort sequence (01111111) was detected. This indicates that the data link became inactive. 011 Unused. 100 ...

Page 180

Register 353H: RDLC Data Bit Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Consecutive reads of the RDLC Status and Data Registers should ...

Page 181

Register 354H: RDLC Primary Address Match Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W PA[7:0] The first byte received after a flag ...

Page 182

Register 355H: RDLC Secondary Address Match Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W SA[7:0] The first byte received after a flag ...

Page 183

Register 358H: TDPR Configuration Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and ...

Page 184

EOM The EOM bit indicates that the last byte of data written in the Transmit Data Register is the end of the present data packet. If the CRC bit is set then the 16-bit FCS word is appended to the ...

Page 185

Register 359H: TDPR Upper Transmit Threshold Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W UTHR[6:0] The UTHR[6:0] bits define the TDPR FIFO fill ...

Page 186

Register 35AH: TDPR Lower Interrupt Threshold Bit Type Bit 7 Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LINT[6:0] The LINT[6:0] bits define the TDPR FIFO fill ...

Page 187

Register 35BH: TDPR Interrupt Enable Bit Type Bit 7 Bit 6 Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LFILLE The LFILLE enables a transition to logic one on LFILLI to ...

Page 188

Register 35CH: TDPR Interrupt Status/UDR Clear Bit Type Bit 7 Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR ...

Page 189

BLFILL The BLFILL bit is set to logic one if the current FIFO fill level is below the LINT[7:0] level or is empty. FULL The FULL bit reflects the current condition of the TDPR FIFO. If FULL is a logic ...

Page 190

Register 35DH: TDPR Transmit Data Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR ...

Page 191

Register 360H: RXCP-50 Configuration 1 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 Bit 4 Bit 3 Bit 2 R/W Bit 1 R/W Bit 0 R/W DISCOR The DISCOR bit controls the HCS error correction algorithm. When DISCOR ...

Page 192

DDSCR The DDSCR bit controls the descrambling of the cell payload with the polynomial x When DDSCR is set to logic one, cell payload descrambling is disabled. When DDSCR is set to logic zero, payload descrambling is enabled. Proprietary and ...

Page 193

Register 361H: RXCP-50 Configuration 2 Bit Type Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W HCSFTR[1:0] The HCS filter bits, HCSFTR[1:0] indicate the number ...

Page 194

IN52 The IN52 bit defines the number of bytes contained in incoming cells. When IN52 is a logic zero, incoming cells are 53-bytes in length. When IN52 is a logic one, incoming cells are 52- bytes in length. In order ...

Page 195

Register 362H: RXCP-50 FIFO/UTOPIA Control & Configuration Bit Type Bit 7 R/W Bit 6 Bit 5 R/W Bit 4 R/W Bit 3 Bit 2 Bit 1 Bit 0 R/W FIFORST The FIFORST bit is used to reset the four-cell receive ...

Page 196

RXPTYP The RXPTYP bit selects even or odd parity for output RXPRTY. When set to logic one, output RXPRTY is the even parity bit for outputs RDAT[15:0]. When RXPTYP is set to logic zero, RXPRTY is the odd parity bit ...

Page 197

Register 363H: RXCP-50 Interrupt Enables and Counter Status Bit Type Bit 7 R Bit 6 R Bit 5 Bit 4 R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LCDE The LCDE bit enables the generation ...

Page 198

OVR The OVR bit is the overrun status of the RXCP-50 Performance Monitoring Count Registers. A logic one in this bit position indicates that a previous transfer (indicated by XFERI being logic one) has not been acknowledged before the next ...

Page 199

Register 364H: RXCP-50 Status/Interrupt Status Bit Type Bit 7 R Bit 6 R Bit 5 Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R LCDI The LCDI bit is set high when there is ...

Page 200

LCDV The LCDV bit gives the Loss of Cell Delineation state. When LCD is logic one, an out of cell delineation (OCD) defect has persisted for the number of cells specified in the LCD Count Threshold Register. When LCD is ...

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