FW82371AB Intel Corporation, FW82371AB Datasheet
FW82371AB
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FW82371AB Summary of contents
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... Independent Timing Drives PIO Mode 4 and Bus Master IDE Transfers Mbytes/sec Supports “Ultra DMA/33” Synchronous DMA Mode Transfers Mbytes/sec © INTEL CORPORATION 1997 4/9/97 2:23 PM PIIX4aDS INTEL CONFIDENTIAL (until publication date) Integrated 16 x 32-bit Buffer for IDE ® and PCI Burst Transfers Supports Glue-less “ ...
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The 82371AB PCI ISA IDE Xcelerator (PIIX4 multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function PCI-to-ISA bridge, PIIX4 ...
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PCICLK AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# STOP# Interface DEVSEL# SERR# PAR IDSEL PHOLD# PHLKA# CLKRUN# RCIN# PWROK CPURST RSTDRV INIT PCIRST# IRQ0//GPO14 IRQ8#/GPI6 IRQ12/M INTR NMI IRQ[15,14,11:9,7:3,1] SERIRQ/GPI7 PRIQ[A:C] PIRQD IRQ9OUT#/GPO29 SMI# STPCLK# EXTSMI# SLP# SUSCLK BATLOW#/GPI9 THRM#/GPI8 LID//GPI10 RI#/GPI12 ...
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ARCHITECTURAL OVERVIEW....................................................................................................................12 2.0. SIGNAL DESCRIPTION ................................................................................................................................15 2.1. PIIX4 Signals ..............................................................................................................................................16 2.1.1. PCI Bus Interface.................................................................................................................................16 2.1.2. ISA Bus Interface.................................................................................................................................18 2.1.3. X-Bus Interface ....................................................................................................................................21 2.1.4. DMA Signals ........................................................................................................................................23 2.1.5. Interrupt Controller/APIC Signals.........................................................................................................24 2.1.6. CPU Interface Signals .........................................................................................................................26 2.1.7. Clocking ...
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CLASSC—Class Code Register (Function 0) .....................................................................................56 4.1.7. HEDT—Header Type Register (Function 0)........................................................................................56 4.1.8. IORT—ISA I/O Recovery Timer Register (Function 0) .......................................................................56 4.1.9. XBCS—X-Bus Chip Select Register (Function 0) ...............................................................................57 4.1.10. PIRQRC[A:D]—PIRQX Route Control Registers (Function 0) .........................................................59 4.1.11. SERIRQC—Serial ...
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TMRCNT—Timer Count Registers (IO) .......................................................................................82 4.2.4. NMI Registers ......................................................................................................................................83 4.2.4.1. NMISC—NMI Status and Control Register (IO) ...........................................................................83 4.2.4.2. NMIEN—NMI Enable Register (Shared with Real-Time Clock Index Register) (IO) ...................84 4.2.5. Real Time Clock Registers ..................................................................................................................84 4.2.5.1. RTCI—Real-Time ...
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RID—Revision Identification Register (Function 2) ...........................................................................104 6.1.6. CLASSC—Class Code Register (Function 2) ...................................................................................104 6.1.7. MLT—Master Latency Timer Register (Function 2) ..........................................................................105 6.1.8. HEDT—Header Type Register (Function 2)......................................................................................105 6.1.9. INTLN—Interrupt Line Register (Function 2).....................................................................................105 6.1.10. INTPN—Interrupt Pin (Function 2) ..................................................................................................106 ...
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DEVRESH—Device Resource H (Function 3)................................................................................133 7.1.24. DEVRESI—Device Resource I (Function 3) ...................................................................................133 7.1.25. DEVRESJ Device Resource J (Function 3) .................................................................................134 7.1.26. PMREGMISC Miscellaneous Power Management (Function 3) ..................................................134 7.1.27. SMBBA—SMBUS Base Address (Function 3)................................................................................135 7.1.28. SMBHSTCFG SMBUS ...
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I/O Accesses .....................................................................................................................................154 8.1.2. Memory Address Map........................................................................................................................154 8.1.3. BIOS Memory ....................................................................................................................................155 8.2. PCI Interface.............................................................................................................................................157 8.2.1. Transaction Termination ....................................................................................................................157 8.2.2. Parity Support ....................................................................................................................................157 8.2.3. PCI Arbitration....................................................................................................................................157 8.3. ISA/EIO Interface......................................................................................................................................158 8.4. DMA Controller .........................................................................................................................................158 8.4.1. DMA Transfer Modes.........................................................................................................................159 8.4.2. DMA Transfer ...
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Control Register D ......................................................................................................................187 8.9.2. RTC Update Cycle.............................................................................................................................188 8.9.3. RTC Interrupts ...................................................................................................................................188 8.9.4. Lockable RAM Ranges......................................................................................................................188 8.9.5. RTC External Connections ................................................................................................................188 8.10. X-Bus Support ........................................................................................................................................188 8.11. Reset Support.........................................................................................................................................189 8.12. Stand-Alone I/O APIC Support ...............................................................................................................190 9.0. IDE CONTROLLER ...
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Suspend/Resume and Power Plane Control ..........................................................................................228 11.4.1. System Suspend..............................................................................................................................228 11.4.2. System Resume ..............................................................................................................................230 11.4.3. System Suspend and Resume Control Signaling............................................................................232 11.4.3.1. Power Supply Timings ..............................................................................................................232 11.4.3.2. Power Level Active Status Signal Timings ...............................................................................233 11.4.3.3. Power Management Signal Timings (Powered ...
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ARCHITECTURAL OVERVIEW PIIX4 is a multi-function PCI device that integrates many system-level functions. Figure 1 shows an example system block diagram using PIIX4. Host Bus Second Level Cache PCI Bus (3.3V or 5V, 30/33 MHz) Hard CD ...
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PIIX4 can be configured for a full ISA bus or a subset of the ISA bus called the Extended IO (EIO) bus. The use of the EIO bus allows unused signals to be configured as general purpose inputs and outputs. ...
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RTC PIIX4 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered ...
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SIGNAL DESCRIPTION This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, or asserted ...
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PIIX4 Signals 2.1.1. PCI BUS INTERFACE Name Type AD[31:0] I/O PCI ADDRESS/DATA. AD[31: multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical byte address (32 bits). During subsequent ...
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Name Type IDSEL I INITIALIZATION DEVICE SELECT. IDSEL is used as a chip select during PCI configuration read and write cycles. PIIX4 samples IDSEL during the address phase of a transaction. If IDSEL is sampled active, and the bus command ...
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Name Type STOP# I/O STOP. STOP# indicates that PIIX4 Target, is requesting an initiator to stop the current transaction Initiator, STOP# causes PIIX4 to stop the current transaction. STOP output when PIIX4 ...
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Name Type IOCHRDY I/O I/O CHANNEL READY. Resources on the ISA Bus negate IOCHRDY to indicate that wait states are required to complete the cycle. This signal is normally high. IOCHRDY is an input when PIIX4 owns the ISA Bus ...
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Name Type MEMW# I/O MEMORY WRITE. MEMW# is the command to a memory slave that it may latch data from the ISA data bus. MEMW output when PIIX4 owns the ISA Bus. MEMW input ...
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Name Type SMEMW# O STANDARD MEMORY WRITE. PIIX4 asserts SMEMW# to request an ISA memory slave to accept data from the data lines. If the access is below the 1-Mbyte range (00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or ISA master ...
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Name Type RTCALE/ O REAL TIME CLOCK ADDRESS LATCH ENABLE. RTCALE is used to latch the GPO25 appropriate memory address into the RTC. A write to port 70h with the appropriate RTC memory address that will be written ...
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DMA SIGNALS Name Type DACK[0,1,2,3]# O DMA ACKNOWLEDGE. The DACK# output lines indicate that a request for DMA service has been granted by PIIX4 or that a 16-bit master has been granted the DACK[5,6,7]# bus. The active level (high ...
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INTERRUPT CONTROLLER/APIC SIGNALS Name Type APICACK#/ O APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4 after its GPO12 internal buffers are flushed in response to the APICREQ# signal. When the I/O APIC samples this ...
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Name Type IRQ 3:7, 9:11, I INTERRUPT REQUESTS 3:7, 9:11, 14:15. The IRQ signals provide both system 14:15 board components and ISA Bus I/O devices with a mechanism for asynchronously interrupting the CPU. These interrupts may be programmed for either ...
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CPU INTERFACE SIGNALS Name Type A20M# OD ADDRESS 20 MASK. PIIX4 asserts A20M# to the CPU based on combination of Port 92 Register, bit 1 (FAST_A20), and A20GATE input signal. During Reset: High-Z CPURST OD CPU RESET. ...
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Name Type NMI OD NON-MASKABLE INTERRUPT. NMI is used to force a nonmaskable interrupt to the CPU. PIIX4 generates an NMI when either SERR# or IOCHK# is asserted, depending on how the NMI Status and Control Register is programmed. The ...
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CLOCKING SIGNALS Name Type CLK48 I 48-MHZ CLOCK. 48-MHz clock used by the internal USB host controller. This signal may be stopped during suspend modes. PCICLK I FREE-RUNNING PCI CLOCK. A clock signal running ...
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Name Type PDCS3# O PRIMARY DISK CHIP SELECT FOR 3F0 3F7 RANGE. For ATA control register block. If the IDE signals are configured for Primary and Secondary, this output signal is connected to the corresponding signal on the Primary IDE ...
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Name Type PDIOR# O PRIMARY DISK IO READ. In normal IDE this is the command to the IDE device that it may drive data onto the PDD[15:0] lines. Data is latched by PIIX4 on the negation edge of ...
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Name Type SDA[2:0] O SECONDARY DISK ADDRESS[2:0]. These signals indicate which byte in either the ATA command block or control block is being addressed. If the IDE signals are configured for Primary and Secondary, these signals are connected to the ...
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Name Type SDDREQ I SECONDARY DISK DMA REQUEST. This input signal is directly driven from the IDE device DMARQ signal asserted by the IDE device to request a data transfer, and used in conjunction with the ...
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Name Type SIORDY I SECONDARY IO CHANNEL READY. In normal IDE mode, this input signal is directly driven by the corresponding IDE device IORDY signal Ultra DMA/33 read cycle, this signal is used as STROBE, with the PIIX4 ...
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Name Type EXTSMI# I/OD EXTERNAL SYSTEM MANAGEMENT INTERRUPT. EXTSMI falling edge triggered input to PIIX4 indicating that an external device is requesting the system to enter SMM mode. When enabled, a falling edge on EXTSMI# results ...
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Name Type SUSB#/ O SUSPEND PLANE B CONTROL. Control signal asserted during power GPO15 management suspend states. SUSB# is primarily used to control the secondary power plane. This signal is asserted during STR and STD suspend states. If the power ...
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Name Type GPO[30:0] O GENERAL PURPOSE OUTPUTS. These output signals can be controlled via the GPIREG register located in Function 3 (Power Management) System IO Space at address PMBase+34h GPO pin is not multiplexed with another ...
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Signal Multiplexed Default Name With GPO0 GPO GPO[1:7] LA[17:23] GPO GPO8 GPO GPO[9:11] GNT[A:C]# GPO GPO12 APICACK# GPO GPO13 APICCS# GPO GPO14 IRQ0 GPO GPO15 SUSB# SUSB# GPO16 SUSC# SUSC# GPO17 CPU_STP# CPU_STP# GPO18 PCI_STP# PCI_STP# GPO19 ZZ ZZ GPO20 ...
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Signal Multiplexed Default Name With GPO24 RTCCS# RTCCS# GPO25 RTCALE RTCALE GPO26 KBCCS# KBCCS# GPO[27:28] GPO GPO29 IRQ9OUT# GPO GPO30 GPO 38 INTEL CONFIDENTIAL (until publication date) Table 2. GPO Signals Control Register and Bit (PCI Function 1) ...
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OTHER SYSTEM AND TEST SIGNALS Name Type CONFIG1 I CONFIGURATION SELECT 1. This input signal is used to select the type of microprocessor being used in the system. If CONFIG1=0, the system contains a Pentium microprocessor. If CONFIG1=1, the ...
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Power Planes PIIX4 has three primary internal power planes. These power planes permit parts of PIIX4 to power down to conserve battery life. Table 3 shows the internal planes and their uses. Table 3. PIIX4 Internal Power ...
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Power Sequencing Requirements There are no power sequencing requirements for the various V be tied system requiring 5V tolerance tolerant system, this signal must power up before or simultaneous ...
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REGISTER ADDRESS SPACE PIIX4 internal registers are organized into four functions—ISA Bridge with integrated AT compatibility logic, IDE Controller, USB Host Controller, and Enhanced Power Management. Each function has its registers divided into one set of PCI ...
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PCI CONFIGURATION REGISTERS (FUNCTION 0) Table 4. PCI Configuration Registers—Function 0 (PCI to ISA Bridge) Offset Address Mnemonic 00–01h VID Vendor Identification 02–03h DID Device Identification 04–05h PCICMD PCI Command 06–07h PCISTS PCI Device Status 08h RID Revision Identification ...
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IO SPACE REGISTERS Table 5. ISA-Compatible Registers Address Aliased Type Addresses 0000h 0010h R/W 0001h 0011h R/W 0002h 0012h R/W 0003h 0013h R/W 0004h 0014h R/W 0005h 0015h R/W 0006h 0016h R/W 0007h 0017h R/W 0008h 0018h ...
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Table 5. ISA-Compatible Registers Address Aliased Type Addresses 2 3 0070h 0072h, 0074h, WO 0076h 2 3 0070h 0072h, 0074h, WO 0076h 2 4 0071h 0073h, R/W 0075h, 0077h 0072h R/W 0073h R/W 5,6 0080h 0090h R/W 5 0081h 0091h ...
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Table 5. ISA-Compatible Registers Address Aliased Type Addresses 00B2h R/W 00B3h R/W 00C0h 00C1h R/W 00C2h 00C3h R/W 00C4h 00C5h R/W 00C6h 00C7h R/W 00C8h 00C9h R/W 00CAh 00CBh R/W 00CCh 00CDh R/W 00CEh 00CFh R/W 00D0h 00D1h ...
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IDE Configuration The PIIX4 PCI function 1 contains an IDE Controller capable of standard Programmed IO (PIO) transfers as well as Bus Master transfer capability. This function also supports the “Ultra DMA/33” synchronous DMA mode of data transfer. The ...
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IO SPACE REGISTERS Table 7. PCI Bus Master IDE I/O Registers Offset From Mnemonic Base Address 00h BMICP Bus Master IDE Command (primary) 01h — Reserved 02h BMISP Bus Master IDE Status (primary) 03h — Reserved 04–07h ...
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Table 8. PCI Configuration Registers—Function 2 (USB Interface) Address Offset Mnemonic 3Ch INTLN Interrupt Line 3Dh INTPN Interrupt Pin 3E–5Fh — Reserved 60h SBRNUM Serial Bus Release Number 61–BFh — Reserved C0–C1h LEGSUP Legacy Support C2–FFh — Reserved 3.3.2. IO ...
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Power Management Configuration The PIIX4 PCI function 3 contains enhanced Power Management logic with support for Device Management, Suspend and Resume states, and System Clock Control. This function also supports a System Management Bus (SMBus) Host and ...
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Table 10. PCI CONFIGURATION REGISTERS (FUNCTION 3) Address Offset Mnemonic 7C–7Fh DEVRESJ Device Resource J 80h PMREGMISC Miscellaneous Power Management 81–8Fh — Reserved 90–93h SMBBA SMBus Base Address 94–D1h — Reserved D2h SMBHSTCFG SMBus Host Configuration D3h SMBREV SMBus Revision ...
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Table 11. Power Management I/O Registers Offset From Mnemonic Base Address 30–33h GPIREG General Purpose Input 34–37h GPOREG General Purpose Output NOTES: 1. The base address is programmable via the PMBA Register (40–43h; function 3) Table 12. System ...
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PCI TO ISA/EIO BRIDGE REGISTER DESCRIPTIONS This section describes in detail the registers associated with the PIIX4 PCI-to-ISA Bridge function. This includes ISA/EIO configuration, AT compatible and PCI-based DMA control, standard AT and serial interrupt logic, counter/timers, real time ...
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PCICMD—PCI COMMAND REGISTER (FUNCTION 0) Address Offset: 04–05h Default Value: 0007h Attribute: Read/Write This 16-bit register provides basic control over the PIIX4’s ability to respond to PCI cycles. Bit 15:10 Reserved. Read Fast Back-to-Back ...
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PCISTS—PCI DEVICE STATUS REGISTER (FUNCTION 0) Address Offset: 06–07h Default Value: 0280h Attribute: Read/Write The PCISTS Register reports the occurrence of a PCI master-abort by PIIX4 or a PCI target-abort when PIIX4 is a master. The register also indicates ...
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CLASSC—CLASS CODE REGISTER (FUNCTION 0) Address Offset: 09 0Bh Default Value: 060100h Attribute: Read Only This register identifies the Base Class Code, Sub-Class Code, and Device Programming interface for PIIX4 PCI function 0. Bit 23:16 Base Class ...
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Bit 7 DMA Reserved Page Register Aliasing Control (DMAAC). When DMAAC=0, PIIX4 aliases PCI I/O accesses in the 90–9Fh range to the 80–8Fh range. In this case, PIIX4 only forwards PCI write accesses to 90–9Fh to the ISA Bus. ISA ...
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Bit 10 Micro Controller Address Location Enable. 1=Enable MCCS# and positive PCI decode for address locations 62h and 66h. 0=Disable MCCS# and positive PCI decode for accesses to these locations. 9 1-Meg Extended BIOS Enable. When bit 9=1, ...
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PIRQRC[A:D]—PIRQX ROUTE CONTROL REGISTERS (FUNCTION 0) Address Offset : 60h (PIRQRCA#)–63h (PIRQRCD#) Default Value: 80h Attribute: R/W These registers control the routing of the PIRQ[A:D]# signals to the IRQ inputs of the interrupt controller. Each PIRQx# can be independently ...
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TOM—TOP OF MEMORY REGISTER (FUNCTION 0) Address Offset: 69h Default Value: 02h Attribute: Read/Write This register enables the forwarding of ISA or DMA memory cycles to the PCI Bus and sets the top of main memory accessible ...
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MSTAT—MISCELLANEOUS STATUS REGISTER (FUNCTION 0) Address Offset: 6A–6Bh Default Value: 0000h Attribute: Read/Write This register provides miscellaneous status and control functions. Bit 15 SERR# Generation Due To Delayed Transaction Time-out—R/WC. PIIX4 sets this bit when it ...
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APICBASE—APIC BASE ADDRESS RELOCATION REGISTER (FUNCTION 0) Address Offset: 80h Default Value: 00h Attribute: Read/Write This register provides the modifier for the APIC base address. APIC is mapped in the memory space at the locations FEC0_xy00h and ...
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Bit 7:4 Reserved. 3 SERR# Generation Enable (Due To Delayed Transaction Time-out). 1=Enable. 0=Disable. 2 USB Passive Release Enable (USBPR). 1=Enable. 0=Disable. When enabled, this allows PIIX4 to use Passive Release while transferring control information or data for USB transactions. ...
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Bit 7:6 DMA CH 3 Select. This field defines the type of DMA performed on this channel. Bits[7:6] DMA Type 00 Normal ISA DMA (default) 01 PC/PCI DMA 10 Distributed DMA 11 Reserved 5:4 DMA CH 2 Select. ...
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GENCFG—GENERAL CONFIGURATION REGISTER (FUNCTION 0) Address Offset: B0–B3h Default Value: 0000h Attribute: Read/Write This register provides general system configuration for PIIX4, including signal and GPIO selects, ISA/EIO select, IDE signal configuration, and IDE signal enables. Bit 31 KBCCS#/GPO26 Signal ...
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Bit 16 SERIRQ/GPI7 Signal Pin Select. 0=GPI7 (default). 1=SERIRQ signal. This bit selects the functionality multiplexed onto the SERIRQ pin. 15 SMBALERT#/GPI11 Signal Pin Select. 0=SMBALERT# signal (default). 1=GPI11. This bit selects the functionality multiplexed onto the SMBALERT# ...
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Bit 1 Positive or Subtractive Decode Configuration. 0=Subtractive Decode (default). 1=Positive Decode. This bit determines how PIIX4 decodes accesses on the PCI bus for forwarding to ISA. If set for positive decode, PIIX4 positively decodes (with medium decode timing) and ...
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Bit 2 Upper RAM Enable. 0=Accesses to RTC Upper 128-byte extended bank at I/O address 72–73h is disabled. Accesses will be forwarded to ISA bus as determined by bit 5 of this register (default). 1=Accesses to 72–73h are ...
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DCM—DMA Channel Mode Register (IO) I/O Address: Channels 0–3—0Bh; Channels 4–7—0D6h Default Value: Bits[7:2]=0; Bits[1:0]=undefined (CPURST or Master Clear) Attribute: Write Only Each channel has a 6-bit DMA Channel Mode Register. The Channel Mode Registers provide control over DMA ...
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DR—DMA Request Register (IO) I/O Address: Channels 0–3—09h; Channels 4–7—0D2h Default Value: Bits[1:0]=undefined; Bits[7:2]=0 (CPURST or Master Clear) Attribute: Write Only The Request Register is used by software to initiate a DMA request. The DMA responds to ...
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RWAMB—Read/Write All Mask Bits (IO) I/O Address: Channels 0–3—0Fh; Channels 4–7—0DEh Default Value: Bit[3:0]=1; Bit[7:4]=0 (CPURST or Master Clear) Attribute: Read/Write A channel’s mask bit is automatically set to 1 when the Current Byte/Word Count Register reaches terminal count ...
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DBADDR—DMA Base and Current Address Registers (IO) I/O Address: DMA Channel 0—000h DMA Channel 1—002h DMA Channel 2—004h DMA Channel 3—006h Default Value: Undefined (CPURST or Master Clear) Attribute: Read/Write This Register works in conjunction with the ...
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DLPAGE—DMA Low Page Registers (IO) I/O Address: DMA Channel 0—087h DMA Channel 1—083h DMA Channel 2—081h DMA Channel 3—082h Default Value: Undefined (CPURST or Master Clear) Attribute: Read/Write This register works in conjunction with the Current Address Register. After ...
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DCLM—DMA Clear Mask Register (IO) I/O Address: Channel 0–3—00Eh; Channel 4–7—0DCh Default Value: All bits undefined Attribute: Write Only This command clears the mask bits of all four channels, enabling them to accept DMA requests. Bit 7:0 ...
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Bit 7:5 ICW/OCW select. These bits should be 000 when programming PIIX4. 4 ICW/OCW select. Bit 4 must select ICW1. After the fixed initialization sequence to ICW1, ICW2, ICW3, and ICW4, the controller base address is ...
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ICW3—Initialization Command Word 3 Register (IO) I/O Address: INT CNTRL-2—0A1h Default Value: All bits undefined Attribute: Write Only On CNTRL-2 (the slave controller), ICW3 is the slave identification code broadcast by CNTRL-1. Bit 7:3 Reserved. Must be ...
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OCW1—Operational Control Word 1 Register (IO) I/O Address: INT CNTRL-1—021h; INT CNTRL-2—0A1h Default Value: 00h Attribute: Read/Write OCW1 sets and clears the mask bits in the Interrupt Mask Register (IMR). Each interrupt request line may be selectively masked or ...
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Bit 2:0 Interrupt Level Select (L2, L1, L0). L2, L1, and L0 determine the interrupt level acted upon when the SL bit is active (bit 6). When the SL bit is inactive, bits [2:0] do not have a ...
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ELCR1—Edge/Level Control Register (IO) I/O Address: INT CNTRL-1—4D0h Default Value: 00h Attribute: Read/Write ELCR1 register allows IRQ[3: edge or level programmable on an interrupt by interrupt basis. IRQ0, IRQ1 and IRQ2 are not programmable and are always ...
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COUNTER/TIMER REGISTERS 4.2.3.1. TCW—Timer Control Word Register (IO) I/O Address: 043h Default Value: All bits undefined Attribute: Write Only The Timer Control Word Register specifies the counter selection, the operating mode, the counter byte programming order and ...
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Bit 7:6 Read Back Command. When bits[7:6]=11, the Read Back Command is selected during a write to the Timer Control Word Register. Following the Read Back Command, I/O reads from the selected counter’s I/O addresses produce the current latch status, ...
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TMRSTS—Timer Status Registers (IO) I/O Address: Counter 0—040h; Counter 1—041h; Counter 2—042h Default Value: Bits[6:0]=X; Bit 7=0 Attribute: Read Only Each counter’s status byte can be read following an Interval Timer Read Back Command. If latch status ...
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NMI REGISTERS The NMI logic incorporates two different 8-bit registers. The CPU reads the NMISC Register to determine the NMI source (bits set to a 1). After the NMI interrupt routine processes the interrupt, software clears the NMI status ...
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NMIEN—NMI Enable Register (Shared with Real-Time Clock Index Register) (IO) I/O Address: 070h Default Value: Bit[6:0]=undefined; Bit 7=1 Attribute: Write Only This port is shared with the real-time clock. Do not modify the contents of this register ...
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RTCD—Real-Time Clock Data Register (IO) I/O Address: 071h Default Value: Undefined Attribute: Read/Write The data port for accesses to the RTC standard RAM bank. Bit 7:0 Standard RAM Data Port. Data written to standard RAM bank address selected via ...
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ADVANCED POWER MANAGEMENT (APM) REGISTERS This section describes two power management registers—APMC and APMS Registers. These registers are located in normal I/O space and must be accessed (via the PCI Bus) with 8-bit accesses. 4.2.6.1. APMC—Advanced Power ...
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P92—Port 92 Register (IO) I/O Address: 92h Default Value: 00h Attribute: Read/Write Bit 7:2 Reserved. Returns 0 when read. 1 FAST_A20. 1=Causes A20M# signal to be asserted to 0. 0=A20M# signal determined by A20GATE signal. This signal is internally ...
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RC—Reset Control Register (IO) I/O Address: CF9h Default Value: 00h Attribute: Read/Write Bits 1 and 2 in this register are used by PIIX4 to generate a hard reset or a soft reset. During a hard reset, PIIX4 ...
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IDE CONTROLLER REGISTER DESCRIPTIONS (PCI FUNCTION 1) This section describes in detail the registers associated with PIIX4 IDE Controller function. This includes Programmed I/O (PIO), Bus Master, and “Ultra DMA/33” synchronous DMA functionality. 5.1. IDE Controller PCI Configuration Registers ...
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Bit 3 Special Cycle Enable (Not Implemented). This bit is hardwired Bus Master Function Enable (BME). 1=Enable. 0=Disable. 1 Memory Space Enable (Not Implemented). This bit is hardwired I/O Space Enable (IOSE). ...
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RID—REVISION IDENTIFICATION REGISTER (FUNCTION 1) Address Offset: 08h Default Value: Initial Stepping=00h. Refer to PIIX4 Specification Updates for other values programmed here. Attribute: Read Only This 8-bit register contains device stepping information. Writes to this register have no effect. ...
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HEDT—HEADER TYPE REGISTER (FUNCTION 1) Address Offset: 0Eh Default Value: 00h Attribute: Read Only This register identifies the IDE Controller module as a single function device. Bit 7:0 Device Type (DEVICET). 00. Multi-function device capability for PIIX4 ...
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IDETIM—IDE TIMING REGISTER (FUNCTION 1) Address Offset: 40–41h=Primary Channel; 42–43h=Secondary Channel Default Value: 0000h Attribute: Read/Write Only This register controls PIIX4’s IDE interface and selects the timing characteristics of the PCI Local Bus IDE cycle for PIO and standard ...
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Bit 4 Fast Timing Bank Drive Select 1 (TIME1). When TIME1=0, accesses to the data port of the enabled I/O address range use the 16-bit compatible timing. When TIME1=1 and the currently selected drive (via a copy of ...
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SIDETIM—SLAVE IDE TIMING REGISTER (FUNCTION 1) Address Offset: 44h Default Value: 00h Attribute: Read/Write Only This register controls PIIX4’s IDE interface and selects the timing characteristics for the slave drives on each IDE channel. This allows for programming of ...
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UDMACTL—ULTRA DMA/33 CONTROL REGISTER (FUNCTION 1) Address Offset: 48h Default Value: 00h Attribute: Read/Write This register enables each individual channel and drive for Ultra DMA/33 operation. For non-Ultra DMA/33 operation, this register should be left programmed to ...
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Bit 15:14 Reserved. 13:12 Secondary Drive 1 Cycle Time (SCT1). These bit settings determine the minimum data write strobe Cycle Time (CT) and minimum Ready to Pause time (RP). Bits[13:12] Time 00 CT=4 PCICLK, RP=6 PCICLK 01 CT=3 PCICLK, RP=5 ...
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Table 13. Ultra DMA/33 Timing Mode Settings Bit Setting Mode 0 (120 ns Strobe Period) Cycle Time Bit Settings Table 14. DMA/PIO Timing Values (Based on PIIX4 Cable Mode and System Speed) PIIX4 Drive IORDY Recovery Mode Sample ...
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IDE Controller IO Space Registers The PCI IDE function uses 16 bytes of I/O space, allocated via the BMIBA register. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. The description of ...
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BMISX—BUS MASTER IDE STATUS REGISTER (IO) Address Offset: Primary Channel—Base + 02h; Secondary Channel—Base + 0Ah Default Value: 00h Attribute: Read/Write Clear This register provides status information about the IDE device and state of the IDE DMA ...
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Table 15. Interrupt/Activity Status Combinations Bit 2 Bit Error condition. If the IDE DMA Error bit is 1, there is a problem transferring data to/from memory. Specifics of the error have to be determined using bus-specific information. ...
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USB HOST CONTROLLER REGISTER DESCRIPTIONS (PCI FUNCTION 2) This section describes in detail the registers associated with the PIIX4 USB Host Controller function. This includes UHCI compatible registers and Legacy Keyboard registers. 6.1. USB Host Controller PCI ...
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PCICMD—PCI COMMAND REGISTER (FUNCTION 2) Address Offset: 04 05h Default Value: 00h Attribute: Read/Write This register controls access to the I/O space registers. Bit 15:10 Reserved. Read 0. 9 Fast Back to Back Enable (Not Implemented). This bit is ...
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Bit 11 Signaled Target-Abort Status (STA)—R/WC. This bit is set when the Serial Bus module function is targeted with a transaction that the Serial Bus module terminates with a target abort. Software resets STA writing ...
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MLT—MASTER LATENCY TIMER REGISTER (FUNCTION 2) Address Offset: 0Dh Default Value: 00h Attribute: Read/Write MLT is an 8-bit register that controls the amount of time (in terms of PCI clocks) the USB module can do transactions on the PCI ...
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INTPN—INTERRUPT PIN (FUNCTION 2) Address Offset: 3Dh Default Value: 04h Attribute: Read only This register indicates which PCI interrupt pin is used for the Universal Serial Bus module interrupt. The USB interrupt is internally ORed to the ...
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LEGSUP—LEGACY SUPPORT REGISTER (FUNCTION 2) PCI Address Offset: C0 C1h Default: 2000h Attribute: Read/Write Clear This register provides control and status capability for the legacy keyboard and mouse functions. Bit 15 End Of A20GATE Pass-Through Status (A20PTS)—R/WC. This bit ...
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Bit 5 A20Gate Pass-Through Enable (A20PTEN)—R/W. 1=Enable A20GATE pass-through sequence. 0 (default)=Disable. When enabled, the logic will pass through the following A20GATE command sequence: Cycle Address Data Write 64h D1h Write 60h xxh Read 64h N/A Write 64h ...
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MISCSUP—MISCELLANEOUS SUPPORT REGISTER (FUNCTION 2) Address Offset: FFh Default Value: XXh Attribute: Read/Write (Byte accesses only) This register provides miscellaneous control capability for the PIIX4. The following programming model must be followed to read the RTC Index register. 1. ...
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Bit 6 Configure Flag (CF). HCD software sets this bit as the last action in its process of configuring the Host Controller. This bit has no effect on the hardware provided only as a semaphore service ...
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Table 16. Run/Stop, Debug Bit Interaction SWDBG Run/Stop (Bit 5) (Bit executing a command, the Host Controller completes the command and then stops. The 1.0 ms frame counter is reset and command list execution resumes from ...
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Bit 2 Resume Detect. The Host Controller sets this bit to 1 when it receives a “RESUME” signal from a USB device. This is only valid if the Host Controller global suspend state (bit 3 ...
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FRNUM—FRAME NUMBER REGISTER (IO) I/O Address: Base + (06 07h) Default Value: 0000h Attribute: Read/Write (Writes must be Word Writes) Bits [10:0] of this register contain the current frame number which is included in the frame SOF packet. This ...
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SOFMOD—START OF FRAME (SOF) MODIFY REGISTER (IO) I/O Address: Base + (0Ch) Default Value: 40h Attribute: Read/Write This 1-byte register is used to modify the value used in the generation of SOF timing on the USB. Only ...
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PORTSC—PORT STATUS AND CONTROL REGISTER (IO) I/O Address: Base + (10 11h) Port 0 Base + (12 13h) Port 1 Default: 0080h Access: Read/Write (WORD writeable only) After a Power-up reset, Global reset, or Host Controller reset, the initial ...
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Bit 5:4 Line Status—RO. These bits reflect the D+ (bit 4) and D– (bit 5) signals lines’ logical levels. These bits are used for fault detect and recovery as well as for USB diagnostics. This field is updated ...
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POWER MANAGEMENT REGISTER DESCRIPTIONS This section describes in detail the registers associated with the PIIX4 Power Management function. This includes device monitoring, suspend and resume functionality, clock control, and SMBus operation. 7.1. Power Management PCI Configuration Registers (PCI Function ...
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Bit 3 Special Cycle Enable (Not Implemented). This bit is hardwired Bus Master Enable (Not Implemented). This bit is hardwired Memory Space Enable (Not Implemented). This bit is hardwired ...
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RID—REVISION IDENTIFICATION REGISTER (FUNCTION 3) Address Offset: 08h Default Value: Initial Stepping=00h. Refer to PIIX4 Specification Updates for other values programmed here. Attribute: Read Only This 8-bit register contains device stepping information. Writes to this register have no effect. ...
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INTLN—INTERRUPT LINE REGISTER (FUNCTION 3) Address Offset: 3Ch Default Value: 00h Attribute: Read/Write Software programs this register with interrupt information concerning the Power Management module. Bit 7:0 Interrupt Line. The value in this register has no affect ...
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CNTA—COUNT A (FUNCTION 3) Address Offset: 44–47h Default Value: 00h Attribute: Read/Write This register contains the initial counts of the idle timers for devices 0–11, the selection bits for the timer granularity of the timers for devices 0, 1, ...
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Bit 23 Reserved. Read as 0. 22:18 Bus Master Timer Count (BM_CNT)—R/W. Specifies the initial and reload count of the device 8 (parallel port and PCI bus master) idle timer. 17:16 Reserved. Read Device 8 ...
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GPICTL—GENERAL PURPOSE INPUT CONTROL (FUNCTION 3) Address Offset: 4C–4Fh Default Value: 00h Attribute: Read/Write This register contains the enable bits, the polarity bits and edge selection bits for the General Purpose IO in device monitors 1–13. Bit 31:28 Reserved. ...
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Bit 23 Reserved. 22:21 LPT DMA select (LPT_DMA_SEL)—R/W. Selects the active DACK signal used to reload the idle timer for device 8 (parallel port). Enabled by RES_EN_DEV8 bit. Bits[22:21] DACK Signal 00 DACK0 01 DACK1 10 DACK3 11 ...
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DEVACTA—DEVICE ACTIVITY A (FUNCTION 3) Address Offset: 54–57h Default Value: 00h Attribute: Read/Write This register contains bits that enable Device Activity as Global Timer Reload events or Clock Events (Burst or Break). Bit 31 Device 5 Reload Select (BRLD_SEL_DEV5)—R/W. ...
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DEVACTB—DEVICE ACTIVITY B (FUNCTION 3) Address Offset: 58–5Bh Default Value: 00h Attribute: Read/Write This register contains the Clock Event and Global Timer Reload enables for IRQs, PCI access, PME events, Video. Bit 31:25 Reserved. 25 APMC Enable ...
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DEVRESA—DEVICE RESOURCE A (FUNCTION 3) Address Offset: 5C–5Fh Default Value: 00h Attribute: Read/Write Bit 31 Device 8 EIO Enable (EIO_EN_DEV8)—R/W. 1=Enable PCI access to the device 8 enabled I/O ranges to be claimed by PIIX4 and forwarded to the ...
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Bit 9:8 Microsoft* Sound System Decode Select (MSS_SEL)—R/W. Selects the Microsoft Sound System decode range enabled with bit 7. This field is decoded as follows: Bits[9:8] MSS Decode 00 530h–537h 01 604h–60Bh 10 E80h–E87h 11 F40h–F47h 7 Microsoft ...
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DEVRESB—DEVICE RESOURCE B (FUNCTION 3) Address Offset: 60–63h Default Value: 00h Attribute: Read/Write Bit 31 Game Port EIO Enable (GAME_EIO_EN)—R/W. 1=Enable PCI bus decode for accesses to the Game Port enabled decode ranges to be claimed by PIIX4 and ...
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Bit 15:0 Device 9 Generic Decode Base Address (BASE_DEV9)—R/W. Specifies the 16-bit I/O base address range (AD[15:0]) for the device 9 I/O range. When this field is combined with MASK_DEV9 field, an I/O range is defined starting from ...
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Bit 19:16 Device 10 Generic Decode Mask (MASK_DEV10)—R/W. Specifies the 4-bit I/O base address mask used to determine the IO address range size for device 10 accesses. MASK_DEV10 (bits[19:16]) correspond to AD[3:0]. A ‘1’ bit position indicates that ...
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Bit 14:8 Reserved. 7 Device 12 Memory Monitor Enable (MEM_EN_DEV12)—R/W. 1=Enable PCI bus decode for accesses to the memory address range selected by the MBASE_DEV12 and MMASK_DEV12 fields. 0=Disable. The EIO enable bit, or trap enable bit for ...
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DEVRESH—DEVICE RESOURCE H (FUNCTION 3) Address Offset: 74–77h Default Value: 00h Attribute: Read/Write Bit 31:15 Memory Decode Base Address (MBASE_DEV13)—R/W. Specifies the 17-bit memory base address range (AD[31:15]) for the device 13 memory range. When this field is combined ...
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DEVRESJ—DEVICE RESOURCE J (FUNCTION 3) Address Offset: 7C–7Fh Default Value: 00h Attribute: Read/Write Bit 31:21 Reserved. 20 Generic I/O Decode 1 Enable (IO_EN_GDEC1)—R/W. 1=Enable accesses to the I/O address range selected by the IO_MASK_GDEC1 and IO_BASE_GDEC1 fields ...
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SMBBA—SMBUS BASE ADDRESS (FUNCTION 3) Address Offset: 90 93h Default Value: 00000001h Attribute: Read/Write This register contains the base address of the SMBus I/O Registers. Bit 31:16 Reserved. Hardwired to 0s. Must be written as 0s. 15:4 Index Register ...
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SMBSHDW1—SMBUS SLAVE SHADOW PORT 1 (FUNCTION 3) Address Offset: D4h Default Value: 00h Attribute: Read/Write Bit 7:1 SMBus Slave Address for shadow port 1 (SLVPORT1)—R/W. Specifies the address used to match against incoming SMBus addresses for shadow ...
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Power Management IO Space Registers The “Base” address is programmed in the PIIX4 PCI Configuration Space for Function 3, Offset 40h–43h. 7.2.1. PMSTS—POWER MANAGEMENT STATUS REGISTER (IO) I/O Address: Base + (00h) Default Value: 00h Attribute: Read/Write Bit 15 ...
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PMEN—POWER MANAGEMENT RESUME ENABLE REGISTER (IO) I/O Address: Base + (02h) Default Value: 00h Attribute: Read/Write Bit 15:11 Reserved. 10 RTC Enable (RTC_EN)—R/W. 1=Enable the generation of a resume event upon setting of the RTC_STS bit. 0=Disable. ...
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Bit 9:3 Reserved. 2 Global Release (GBL_RLS)—R/W. 1=A 1 written to this bit position will cause an SMI generated and BIOS_STS bit set if enabled by the BIOS_EN bit. 0=No SMI# generated. This bit is used by the ...
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Bit 8 USB Status (USB_STS)—R/WC. 1=USB interface has indicated that a USB resume has been driven onto one of the two USB ports while in Power On Suspend. 0=No USB resume has been detected. If the USB_EN bit ...
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PCNTRL—PROCESSOR CONTROL REGISTER (IO) I/O Address: Base + (10h) Default Value: 00h Attribute: Read/Write Bit 31:18 Reserved. 17 Clock Control Status (CC_STS)—RO. 1=PIIX4 clock control active. 0=PIIX4 clock control inactive. 16:14 Reserved. 13 Clock Run Enable (CLKRUN_EN)—R/W. 1=Enable PCI ...
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PLVL2—PROCESSOR LEVEL 2 REGISTER (IO) I/O Address: Base + (14h) Default Value: 00h Attribute: Read/Write (Byte Readable Only) Bit 7:0 Level 2 Power State Entry (LVL2)—R/W. Reads to this register cause PIIX4 to transition into a Stop ...
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GLBSTS—GLOBAL STATUS REGISTER (IO) I/O Address: Base + (18h) Default Value: 00h Attribute: Read/Write Bit 15:12 Reserved. 11 IRQ Resume Status (IRQ_RSM_STS)—R/W. 1=System was resumed from a Powered On Suspend (POS) state due to an interrupt assertion (IRQ[1,3:15]). 0=System ...
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DEVSTS—DEVICE STATUS REGISTER (IO) I/O Address: Base + (1Ch) Default Value: 00h Attribute: Read/Write Bit 31:30 Reserved. 29:16 Device [0–13] Trap Status Bits (TRP_STS_DEV[0–13])—R/WC. 1=An SMI# was generated by an I/O trap to the associated device monitor’s ...
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GLBCTL—GLOBAL CONTROL REGISTER (IO) I/O Address: Base + (28h) Default Value: 00h Attribute: Read/Write Bit 31:27 Reserved. 26 Global Standby Timer Clocking Select B (GSTBY_SELB)—R/W. This bit in conjunction with bit 8 selects the clock source for the Global ...
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DEVCTL—DEVICE CONTROL REGISTER (IO) I/O Address: Base + (2Ch) Default Value: 00h Attribute: Read/Write Bit 31:28 Reserved. 27 Device 8 Bus Master Reload Enable (BM_RLD_DEV8)—R/W. 1=Enable any PCI Bus Master request (PHOLD#, PCIREQA[0:3]) to reload the device ...
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Bit 10 Device 5 Idle Enable (IDL_EN_DEV5)—R/W. 1=Enable the device monitor 5 idle reload events to reload the device monitor 5 idle timer. 0=Disable. 9 Device 4 Trap Enable (TRP_EN_DEV4)—R/W. 1=Enable generation of a trap SMI for accesses to the ...
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GPOREG—GENERAL PURPOSE OUTPUT REGISTER (IO) I/O Address: Base + (34h, 35h, 36h, 37h) Default Value: 7FFFBFFFh Attribute: Read/Write (Byte accesses only) Bit 31 Reserved. 30:0 General Purpose Output (GPO)—R/W. Each bit directly represents the logical value output ...
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Bit 0 Host Busy (HOST_BUSY)—RO. 1=Indicates that the SMBus controller host interface is in the process of completing a command. 0=SMBus controller host interface is not processing a command. None of the other registers should be accessed if this bit ...
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SMBHSTCNT—SMBUS HOST CONTROL REGISTER (IO) I/O Address: Base + (02h) Default Value: 00h Attribute: Read/Write The control register is used to enable SMBus controller host interface functions. Reads to this register clears the host interface’s index pointer ...
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SMBHSTADD—SMBUS HOST ADDRESS REGISTER (IO) I/O Address: Base + (04h) Default Value: 00h Attribute: Read/Write This register is transmitted by the SMBus controller host interface in the slave address field of the SMBus protocol. Bit 7:1 SMBus Address (SMB_ADDRESS)—R/W. ...
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SMBBLKDAT—SMBUS BLOCK DATA REGISTER (IO) I/O Address: Base + (07h) Default Value: 00h Attribute: Read/Write Reads and writes to this register are used to access the 32-byte block data storage array. An internal index pointer is used ...
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SMBSHDWCMD—SMBUS SHADOW COMMAND REGISTER (IO) I/O Address: Base + (09h) Default Value: 00h Attribute: Read Only This register is used to store command values for external SMBus master accesses to the host slave and slave shadow ports. Bit 7:0 ...
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PCI/ISA BRIDGE FUNCTIONAL DESCRIPTION This section describes each of the major functions on the PIIX4 PCI-to-ISA Bridge including the memory and I/O address map, DMA controller, interrupt controller, timer/counter and X-Bus interfaces. 8.1. Memory and IO Address ...
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Table 18. DMA and ISA Master Accesses to Main Memory Memory Space Top of main memory to 128 Mbytes 1 Mbyte to top of main memory 1 Mbyte minus 128 Kbytes to 1 Mbyte minus 64 Kbytes 640 Kbytes to ...
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ISA Access to BIOS Memory PIIX4 confines all ISA-initiated BIOS accesses to the top 64 Kbytes of the 128-Kbyte region (F0000–FFFFFh) to the ISA Bus, even if BIOS is shadowed in main memory. Accesses to the bottom 64 ...
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PCI Interface PIIX4 incorporates a fully PCI Bus compatible master and slave interface PCI master, PIIX4 runs cycles on behalf of DMA, ISA masters, bus master IDE, or USB PCI slave, PIIX4 accepts cycles initiated ...
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ISA/EIO Interface PIIX4 can incorporate a fully ISA Bus compatible master and slave interface or a subset interface called the Extended IO (EIO) Bus. PIIX4 can directly drive the equivalent of five ISA slots without external data ...
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Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. PIIX4 provides the timing control and data size ...
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Block Transfer Mode In Block Transfer mode, the DMA is activated by DREQ to continue making transfers during the service until a TC, caused by either a byte/word count going to FFFFh, is encountered. DREQ need only be ...
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Read Transfers Read transfers move data from ISA memory or the system DRAM ISA I/O device. PIIX4 activates the IOW# command and the appropriate DRAM and ISA Memory control signals to indicate a memory read. Data steering is ...
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CHANNEL PRIORITY For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA Command Register. DMA I/O ...
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SUMMARY OF DMA TRANSFER SIZES Table 20 lists each of the DMA device transfer sizes. The column labeled “Current Byte/Word Count Register” indicates that the register contents represents either the number of bytes to transfer or the number of ...
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SOFTWARE COMMANDS There are three additional special software commands which can be executed by the DMA controller. The three software commands are: 1. Clear Byte Pointer Flip-Flop 2. Master Clear 3. Clear Mask Register They do not ...
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ISA Bus refresh cycles are completely decoupled from DRAM Refresh. Transactions driven by PCI masters that target ISA or IDE resources while refresh is active are held off with wait states until the refresh is complete. ISA Master Initiated Refresh ...
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PCI DMA Expansion Protocol The PCI expansion agent must support the PCI expansion Channel Passing Protocol defined in Figure 4 for both the REQ# and GNT# pins. PCICLK REQ# Start CH0 CH1 CH2 GNT# Figure 4. DMA Serial ...
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The three cases above require the following functionality in the PCI DMA expansion device: 1. Drive REQ# inactive for one clock to signal new request information. 2. Drive REQ# inactive for two clocks to signal that a request that had ...
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Table 23. PCI Data Bus vs. DMA I/O port size PCI DMA I/O Port Size Word Table 24. DMA I/O Cycle Width vs. BE[3:0]# BE[3:0]# 1110b 1100b NOTES: For verify cycles the value of the Byte Enables (BEs) ...
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Read/Write Cycles Protocol For read cycles on the PCI bus that correspond to distributed DMA channels, PIIX4 performs the following: PIIX4 issues a PCI retry to terminate this cycle. PIIX4 requests the PCI bus. Upon being granted access to the ...
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Table 25. 8237 Register Map to Distributed DMA Peripheral I/O Address 8237 F/F R/W Status 6h Base Address Register A[0:7] C4, C8, or CCh 6h Current ...
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Single Channel Mask Register To make the peripherals easier to implement, the Distributed DMA specification does not have the peripherals implement the Single-Channel Mask Registers. Instead, a write to the Single Channel Mask register (which encodes the channel number in ...
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IRQ8# 82C59 IRQ9 Core IRQ10 IRQ11 Controller 2 IRQ12/Mouse FERR# (Slave) IRQ14 IRQ15 Figure 5. Interrupt Controller Block Diagram 8.6.1. PROGRAMMING THE INTERRUPT CONTROLLER The Interrupt Controller accepts two types of command words generated by the CPU or ...
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These are the command words which dynamically reprogram the Interrupt Controller to operate in various interrupt modes. Any interrupt lines can be masked by writing an OCW1 written in any bit of this command word will mask incoming ...
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After the initialization sequence, IRQ0 has the highest priority and IRQ7 the lowest. Priorities can be changed, as will be explained, in the rotating priority mode. The Special Fully Nested Mode This mode will be used in the ...
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The Poll command is issued by setting P=1 in OCW3. The Interrupt Controller treats the next I/O read pulse to the Interrupt Controller as an interrupt acknowledge, sets the appropriate IS bit if there is a request, and reads the ...
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INTERRUPT MASKS Masking on an Individual Interrupt Request Basis Each interrupt request input can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt ...
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The IRR can be read when, prior to the I/O read cycle, a Read Register Command is issued with OCW3 (RR=1, RIS=0). The ISR can be read when, prior to the I/O read cycle, a Read Register Command is issued ...
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Serial Interrupts PIIX4 supports a serial IRQ scheme. This allows a single signal to be used to report ISA-style interrupt requests. Typically, it will be used in a mobile environment by docking bridges or Cardbus controllers. Because ...
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Data Frame Number 32:22 Stop Frame After all of the data frames, a Stop frame is performed done by ...
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Timer/Counters PIIX4 contains three counters that are equivalent to those found in the 82C54 programmable interval timer. The three counters are contained in one PIIX4 timer unit, referred to as Timer-1. Each counter output provides a key ...
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The Control Word Register is write only. Counter status information is available with the read back Command. Because the timer counters wake unknown state after power up, multiple refresh requests may be queued. To avoid possible multiple ...
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Counter I/O Port Read The first method is to perform a simple read operation. To read the counter, which is selected with the A1, A0 inputs (port 040h, 041h, or 042h), the CLK input of the selected counter ...
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The Read Back Command may be used to latch multiple counter output latches (OL) by setting the COUNT# bit D5=0 and selecting the desired counter(s). This single command is functionally equivalent to several counter latch commands, one for each counter ...
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SRAM, and will be accessible even when the RTC module is disabled (via the RTC configuration register). All data movement between the host CPU and RTC is done through registers mapped to the ...
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Control Register A Address Offset: 0Ah Default Value: NA (This register is not affected by any system reset signal.) Attribute: Read/Write This register is used for general configuration of the RTC functions. Bits 7 Update in Progress (UIP). This ...
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Control Register B Address Offset: 0Bh Default Value: X0000XXXb Attribute: Read/Write This register is used for general configuration of the RTC functions. Bits 7 SET. Enables the update cycles. 1=A current time update cycle will be aborted, ...
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Control Register C Address Offset: 0Ch Default Value: 00h Attribute: Read/Write This register is used for various flags. All flag bits are cleared upon active RSMRST read of Register C. Bits 7 Interrupt Request Flag (IRQF). Interrupt ...
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RTC UPDATE CYCLE An update cycle occurs once a second, if the SET bit of register B is not set to 1 and the divide chain is properly configured. During this procedure, the stored time and date ...
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SA(16:0) and LA(23:17) address lines (Note that it is assumed that ISA masters drive SA(19:16) and LA(23:17) low when accessing I/O devices). PIIX4 also provides PS/2 mouse support via the IRQ12/M signal and coprocessor functions (FERR# and IGNNE#). The chip ...
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Stand-Alone I/O APIC Support PIIX4 supports a stand-alone I/O APIC device on the ISA X-Bus. PIIX4 provides a chip select signal (APICCS#) for the I/O APIC. It also provides handshake signals to maintain buffer coherency in the ...
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IDE CONTROLLER FUNCTIONAL DESCRIPTION PIIX4 integrates a high performance interface from PCI to IDE. This interface is capable of accelerated PIO data transfers as well as acting as a PCI Bus master on behalf of an IDE DMA slave ...
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PIIX4 Primary Drive 0 IDE Data and Control Figure 7. PIIX4 IDE Configurations 9.2. ATA Register Block Decode The IDE ATA I/O ports are decoded by PIIX4 when enabled in the PCICMD and IDETIM Registers for function 1. ...
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Table 28. IDE Legacy I/O port definition: COMMAND BLOCK (CS1x# chip select) IO Offset Register Function (Read/Write) 00h Data 01h Error/Features 02h Sector Count 03h Sector Number 04h Cylinder Low 05h Cylinder High 06h Drive/Head 07h Status/Command The Data Register ...
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DMA timings. The PIO transfers are executed using compatible timings or fast timings if also enabled. PIO IDE Timing Modes IDE data port transaction latency consists of startup latency, cycle latency, and ...
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PIIX4 can be programmed via the IDETIM registers to allow data to be posted to and prefetched from the IDE data ports. Data prefetching is initiated when a data port read occurs. The read prefetch eliminates latency to the IDE ...
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Byte 3 Byte 2 Memory Region Physical Base Address [31:1] EOT Reserved Figure 8. Physical Region Descriptor Table Entry Operation To initiate a bus master transfer between memory and an IDE DMA slave device, the following steps are ...
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Line Buffer A single line buffer exists for the PIIX4 Bus master IDE interface. This buffer is not shared with any other function. The buffer is maintained in either the read state or the write state. Memory writes are typically ...
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The DIOR# signal is redefined as DMARDY# for transferring data from the IDE device to PIIX4 (read used by PIIX4 to signal when it is ready to transfer data and to add wait states to the ...
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Synchronous DMA Timings The timings for Ultra DMA/33 are programmed into the Ultra DMA/33 Timing Register. The programmable timings include Cycle Time (CT) and Ready to Pause (RP) time. The Cycle Time represents the minimum pulse width of active data ...
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Software Universal Host Controller (HC) Hardware USB Device Figure 9. USB System Conceptual View 200 INTEL CONFIDENTIAL (until publication date) Client Software Universal Serial Bus Driver (USBD) Universal Host Controller Driver (HCD) Universal Host Controller Interface (UHCI) PIIX4 ...