82915GV Intel Corporation, 82915GV Datasheet
82915GV
Related parts for 82915GV
82915GV Summary of contents
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... R ® Intel 915G/915GV/915GL/915P/ 915PL/910GL Express Chipset Datasheet ® For the Intel 82915G/82915GV/82915GL/82910GL Graphics and Memory Controller Hub (GMCH) and the Intel Memory Controller Hub (MCH) February 2005 ® 82915P/82915PL Document Number: 301467-005 ...
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... The Intel 82915G,82915GV,82915GL,82910GL GMCH and 82915P/82915PL MCH may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ...
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... Only) ............................................................................... 28 ® Integrated Graphics (Intel 82915G/82915GV/82910GL/82915GL GMCH Only) ......................................................................................... 29 ® Analog and Intel SDVO Displays (Intel 82915G/82915GV/82910GL/82915GL GMCH Only) ........................... 31 System Interrupts.................................................................................. 31 (G)MCH Clocking.................................................................................. 31 Power Management.............................................................................. 32 ® 82915G/82915GV/82915GL/82910GL Standard PCI Bus Configuration Mechanism ....................................... 58 Logical PCI Bus 0 Configuration Mechanism ....................................... 58 Primary PCI and Downstream Configuration Mechanism .................... 59 PCI Express* Enhanced Configuration Mechanism ............................. 60 ® ...
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... Only)................................................ 76 DMIBAR—Root Complex Register Range Base Address (D0:F0) ...... 77 GGC—GMCH Graphics Control Register (D0:F0) (82915G/82915GV/82915GL/82910GL GMCH only)........................... 78 DEVEN—Device Enable (D0:F0) ......................................................... 79 PAM0—Programmable Attribute Map 0 (D0:F0) .................................. 81 PAM1—Programmable Attribute Map 1 (D0:F0) .................................. 82 PAM2—Programmable Attribute Map 2 (D0:F0) .................................. 83 PAM3—Programmable Attribute Map 3 (D0:F0) .................................. 84 PAM4— ...
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R 5.1.12 5.1.13 5.1.14 5.1.15 5.1.16 5.1.17 5.1.18 5.1.19 5.1.20 5.1.21 5.1.22 6 EPBAR Registers—Egress Port Register Summary ...................................................... 109 6.1 EP RCRB Configuration Register Details .......................................................... 109 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 7 DMIBAR Registers—Direct Media Interface (DMI) RCRB ...
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... Header (D1:F0) ................................................................................... 168 ESD—Element Self Description (D1:F0) ............................................ 169 LE1D—Link Entry 1 Description (D1:F0)............................................ 170 LE1A—Link Entry 1 Address (D1:F0)................................................. 171 PEGSSTS—PCI Express*-G Sequence Status (D1:F0).................... 171 VID2—Vendor Identification (D2:F0) .................................................. 175 DID2—Device Identification (D2:F0) .................................................. 175 PCICMD2—PCI Command (D2:F0) ................................................... 176 PCISTS2—PCI Status (D2:F0)........................................................... 177 ® 82915G/82915GV/82915GL/ Datasheet R ...
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... Device 2 Function 1 (D2:F1) Configuration Registers (Intel 82915G/82915GV/82915GL/ 82910GL Only)................................................................. 193 10.1 Device 2 Function 1 Configuration Register Details (D2:F1) ............................. 194 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.7 10.1.8 10.1.9 10.1.10 MMADR—Memory Mapped Range Address (D2:F1) ........................ 198 10.1.11 SVID2—Subsystem Vendor Identification (D2:F1)............................. 199 10.1.12 SID2—Subsystem Identification (D2:F1)............................................ 199 10.1.13 ROMADR—Video BIOS ROM Base Address (D2:F1) ....................... 199 10.1.14 CAPPOINT—Capabilities Pointer (D2:F1) ......................................... 199 10.1.15 MINGNT— ...
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... PCI Express* Configuration Address Space (Intel Only) ................................................................................................... 215 PCI Express* Graphics Attach (Intel AGP DRAM Graphics Aperture .......................................................... 215 Graphics Memory Address Ranges (Intel 82915G/82915GV/82915GL/82910GL GMCH Only) ......................... 216 SMM Space Definition ........................................................................ 217 SMM Space Restrictions .................................................................... 217 SMM Space Combinations ................................................................. 218 SMM Control Combinations................................................................ 218 SMM Space Decode and Transaction Handling ...
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... System Memory Configuration Registers Overview .......................................... 226 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.4 PCI Express* (Intel 12.4.1 12.4.2 12.4.3 ® 12.5 Intel Serial Digital Video Output (SDVO) (Intel 82915G/82915GV/82915GL/82910GL GMCH Only)......................................... 233 12.5.1 12.5.2 12.6 Integrated Graphics Device (Intel GMCH Only) ....................................................................................................... 235 12.6.1 12.6.2 12.6.3 12.6.4 Datasheet Only) ................................................................................................... 220 FSB GTL+ Termination....................................................................... 223 FSB Dynamic Bus Inversion ............................................................... 223 APIC Cluster Mode Support ............................................................... 224 Memory Organization Modes ...
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... VESA/VGA Mode .............................................................. 249 12.7.1.4 DDC (Display Data Channel) ............................................ 250 Digital Display Interface ...................................................................... 250 12.7.2.1 Digital Display Channels – SDVOB and SDVOC.............. 250 12.7.2.2 ADD2 Card ........................................................................ 250 Multiple Display Configurations .......................................................... 252 General DC Characteristics ................................................................ 262 RGB/CRT DAC Display DC Characteristics (Intel 82915G/82915GV/82915GL/82910GL GMCH Only) ......................... 265 R ® Datasheet ...
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R 15.2 XOR Test Mode Initialization for DDR................................................................ 400 15.3 XOR Test Mode Initialization for DDR2.............................................................. 400 15.4 XOR Chain Definition ......................................................................................... 401 15.5 DDR XOR Chains............................................................................................... 401 15.6 DDR2 XOR Chains............................................................................................. 414 15.7 PADs Excluded from XOR Mode(s) ................................................................... ...
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... Table 15-2. XOR Chain Outputs for both DDR and DDR2............................................. 401 Table 15-3. DDR XOR Chain #0..................................................................................... 402 Table 15-4. DDR XOR Chain #1..................................................................................... 404 Table 15-5. DDR XOR Chain #2..................................................................................... 406 Table 15-6. DDR XOR Chain #3..................................................................................... 407 Table 15-7. DDR XOR Chain #4..................................................................................... 408 Table 15-8. DDR XOR Chain #5..................................................................................... 409 Table 15-9. DDR XOR Chain #6..................................................................................... 410 12 ® 82915G/82915GV/82915GL/82910GL 3 ..................................................................................... 262 R Datasheet ...
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R Table 15-10. DDR XOR Chain #7................................................................................... 411 Table 15-11. DDR XOR Chain #8................................................................................... 412 Table 15-12. DDR XOR Chain #9................................................................................... 413 Table 15-13. DDR2 XOR Chain #0................................................................................. 414 Table 15-14. DDR2 XOR Chain #1................................................................................. 416 Table 15-15. DDR2 XOR ...
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... Minor edits throughout for clarity • Added Intel -003 • Added Intel -004 • Added Intel • Minor edits throughout for clarity -005 14 ® 82915GV GMCH ® 82910GL GMCH ® 82915GL GMCH ® 82915PL GMCH R Date June 2004 September 2004 ...
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... Pentium 4 processor or Intel D processor including 775-Land package. ⎯ Supports Pentium 4 processor FSB interrupt delivery ⎯ 533 MT/s (133 MHz) FSB (82915G/82915GV/ 82915GL/82910GL/82915P/82915PL) and 800 MT/s (200 MHz) FSB (82915G/82915GV/ 82915GL/82915P/82915PL only) ⎯ FSB Dynamic Bus Inversion (DBI) ⎯ 32-bit host bus addressing for access memory space ⎯ ...
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R Datasheet ...
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... GMCH (or MCH) for the host bridge and I/O Controller Hub 6 (ICH6) for the I/O subsystem. The 82915G GMCH is part of the 915G Express chipset, the 82915GV is part of the 915GV Express chipset, the 82915GL is part of the 915GL Express Chipset, the 82910GL is part of the 910GL Express chipset, the 82915P MCH is part of the 915P Express chipset, and the 82915PL is part of the 915PL Express chipset ...
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... Introduction Note: References in this document to DDR2 memory are for the 82915G, 82915GV, and 82915P only. Note: Unless otherwise specified, ICH6 refers to the Intel ICH6W, and 82801FRW ICH6RW I/O Controller Hub 6 components. ® Figure 1-1. Intel 915G Express Chipset System Block Diagram Example VGA ...
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R ® Figure 1-2. Intel 915P Express Chipset System Block Diagram Example Display ® Intel PCI Express Gigabit Ethernet Datasheet ® Intel Pentium Processor or Intel ® Celeron D Processor 533/800 MHz FSB Intel PCI Express ® Intel 82915P MCH ...
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... Processor or Intel ® Celeron D Processor 533/800 MHz System Bus ® Intel 915GV Express Chipset Analog Display Add2 Card ® Intel 82915GV GMCH SDVO DMI Interface ® Intel ICH6 Flash BIOS LPC Interface System Memory DDR or DDR2 Channel A DDR or DDR2 DDR or DDR2 ...
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R ® Figure 1-4. Intel 910GL Express Chipset System Block Diagram Example VGA Display Display USB 2.0 8 ports, 480 Mb/s GPIO 4 Serial ATA Ports 150 MB/s 2 ATA 100 Ports AC '97 3 CODEC support Datasheet ® ® ...
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Introduction ® Figure 1-5. Intel 915PL Express Chipset System Block Diagram Example Display ® Intel PCI Express Gigabit Ethernet 22 ® Intel Pentium Processor or Intel ® Celeron D Processor 533/800 MHz FSB Intel PCI Express* ® 82915PL Intel x16 ...
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R ® Figure 1-6. Intel 915GL Express Chipset System Block Diagram Example VGA Display Display USB 2.0 8 ports, 480 Mb/s GPIO 4 Serial ATA Ports 150 MB/s 2 ATA 100 Ports AC '97 3 CODEC support Datasheet ® ® ...
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... Low Voltage Differential Signaling. A high speed, low power data transmission standard LVDS used for display connections to LCD panels. 24 Description nd Generation. Provides digital display options for an ® 82915G GMCH, 82915GV GMCH, 82915GL, and 82910GL, unless ® I/O Controller Hub component contains the R ® ICH6. Datasheet ...
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R Term The Memory Controller Hub (MCH) component contains the processor interface and MCH DRAM controller; however, it does not contain an internal graphics device like the GMCH. It may also contain an x16 PCI Express port (typically the external ...
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... Figure 1-5, and Figure 1-6. A major role of the (G)MCH in a system is to manage the flow of information between its interfaces: the processor interface (FSB), the System Memory interface (DRAM controller), the Integrated Graphics interface (82915G/82915GV/82915GL/82910GL GMCH only), the External Graphics interface via PCI Express (82915G/82915P/82915PL MCH only), and the I/O Controller Hub through the DMI interface ...
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R configuration space. Host-initiated memory cycles are decoded to PCI Express, DMI, or system memory. PCI Express device accesses to non-cacheable system memory are not snooped on the host bus. Memory accesses initiated from PCI Express using PCI semantics and ...
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Introduction By using 256-Mb technology, the smallest memory capacity possible is 128 MB, assuming single- channel mode. (16M rows * 16b/(row*device devices/DIMM-side * 1 DIMM-side/channel * 1 channel *1B/8b = 128 MB). By using 1-Gb technology in dual-channel ...
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... Integrated Graphics (Intel 82915G/82915GV/82910GL/82915GL GMCH Only) The 82915G/82915GV/82910GL/915GL GMCH provides an integrated graphics device (IGD) delivering cost competitive 3D, 2D and video capabilities. The GMCH contains an extensive set of instructions for 3D operations, BLT and Stretch BLT operations, motion compensation, overlay, and display control. The GMCH’s video engines support video conferencing and other video applications ...
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Introduction GMCH graphics support includes: • Core Frequency of 333 MHz • High Quality 3D Setup and Render Engine ⎯ Setup matching processor geometry delivery rates ⎯ Triangle lists, strips and fans ⎯ Indexed vertex and flexible vertex formats ⎯ ...
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... PCI Express PLL. This clock uses the fixed 100 MHz Serial Reference Clock (GCLKP/GCLKN) for reference. For the 82915G/82915GV/82915GL/82910GL GMCH, display timings are generated from display PLLs that use a 96 MHz differential non-spread spectrum clock as a reference. Display PLLs can also use the SDVO_TVCLKIN[+/-] from an SDVO device as a reference. ...
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Introduction All of the above mentioned clocks are capable of tolerating Spread Spectrum clocking as defined in the Clock Generator specification. Host, Memory, and PCI Express* x16 Graphics PLLs, and all associated internal clocks are disabled until PWROK is asserted. ...
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R 2 Signal Description This chapter provides a detailed description of (G)MCH signals. The signals are arranged in functional groups according to their associated interface. The states of all of the signals during reset are provided in Section 2.11. The ...
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... EXP_COMPI Only EXP_SLR HCLKP, HCLKN GCLKP, GCLKN DREFCLKN, DREFCLKP RSTIN# PWROK EXTTS# BSEL[2:0] MTYPE ICH_SYNC# DMI_RXP[3:0], DMI_RXN[3:0] DMI_TXP[3:0], DMI_TXN[3:0] VCC VTT VCC_EXP VCCSM VCC2 VCCA_EXPPLL VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_SMPLL ® Intel VSS VCCA_DAC 82915G/ VSSA_DAC 82915GV/ 82910GL Only Signal_Info Datasheet ...
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R 2.1 Host Interface Signals Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination voltage of the Host Bus (VTT). Signal Name HADS# HBNR# HBPRI# HBREQ0# HCPURST# HDBSY# HDEFER# HDINV[3:0]# Datasheet ...
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Signal Description Signal Name HDRDY# HEDRDY# HA[31:3]# HADSTB[1:0]# HD[63:0] HDSTBP[3:0]# HDSTBN[3:0]# HHIT# HHITM# HLOCK# HPCREQ# 36 Type I/O Data Ready: This signal is asserted for each cycle that data is transferred. GTL+ O Early Data Ready: This signal indicates that ...
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R Signal Name HREQ[4:0]# HTRDY# HRS[2:0]# BSEL[2:0] HRCOMP HSCOMP HSWING HVREF Datasheet Type I/O Host Request Command: These signals define the attributes of the request. HREQ[4:0]# are transferred at 2x rate. They are asserted by the GTL+ requesting agent during ...
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Signal Description 2.2 DDR/DDR2 DRAM Channel A Interface Note that the 82910GL, 82915GL, and 82915PL (G)MCH only supports DDR DRAM. Signal Name SCLK_A[5:0] SCLK_A[5:0]# SCS_A[3:0]# SMA_A[13:0] SBS_A[2:0] SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0] SDQS_A[7:0] SDQS_A[7:0]# 38 Type O SDRAM Differential Clock: ...
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R Signal Name SCKE_A[3:0] SODT_A[3:0] 2.3 DDR/DDR2 DRAM Channel B Interface Note that the 82910GL, 82915GL, and 82915PL (G)MCH only supports DDR DRAM. Signal Name SCLK_B[5:0] SCLK_B[5:0]# SCS_B[3:0]# SMA_B[13:0] SBS_B[2:0] SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] SDM_B[7:0] Datasheet Type O Clock Enable: ...
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Signal Description Signal Name SDQS_B[7:0] SDQS_B[7:0]# SCKE_B[3:0] SODT_B[3:0] 2.4 DDR/DDR2 DRAM Reference and Compensation Note that the 82910GL, 82915GL, and 82915PL (G)MCH only supports DDR DRAM. Signal Name SRCOMP[1:0] SOCOMP[1:0] SM_SLEWIN[1:0] SM_SLEWOUT[1:0] SMVREF[1:0] 40 Type I/O Data Strobes: For DDR ...
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R 2.5 PCI Express* x16 Graphics Port Signals (Intel 82915G, 82915P, 82915PL Only) Unless otherwise specified, PCI Express Graphics signals are AC coupled, so the only voltage specified is a maximum 1.2 V differential swing. Signal Name EXP_RXN[15:0] EXP_RXP[15:0] EXP_TXN[15:0] ...
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... Signal Description 2.6 Analog Display Signals (Intel 82915G/82915GV/82915GL/82910GL GMCH Only) Signal Name RED RED# GREEN GREEN# BLUE BLUE# REFSET HSYNC VSYNC DDC_CLK DDC_DATA 42 ® Type O RED Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5 Ω ...
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R 2.7 Clocks, Reset, and Miscellaneous Signal Name HCLKP HCLKN GCLKP GCLKN DREFCLKN DREFCLKP RSTIN# PWROK EXTTS# MTYPE ICH_SYNC# 2.8 Direct Media Interface (DMI) Signal Name DMI_RXP[3:0] DMI_RXN[3:0] DMI_TXP[3:0] DMI_TXN[3:0] Datasheet Type I Differential Host Clock In: These pins receive ...
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... Serial DVO (SDVO) Interface (82915G/82915GV/82915GL/82910GL GMCH Only) For the 82915G/82915GV/82915GL/82910GL GMCH, all but two of the pins in this section are multiplexed with the lower 8 lanes of the PCI Express interface. Note: The SDVO interface does not support static lane reversal (e.g., SDVOB_CLK# will originate from the same ball whether the PCI Express interface is lane-reversed mode or not ...
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... Display PLL A Analog Power. 1.5 V Display PLL B Analog Power. 1.5 V Host PLL Analog Power. 1.5 V System Memory PLL Analog Power. 2.5 V Display DAC Analog Power. This signal is on the 82915G/82915GV/82915GL/82910GL GMCH only Ground Ground. This signal is on the 82915G/82915GV/82915GL/82910GL GMCH only. Signal Description Description Description 45 ...
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Signal Description 2.11 Reset States and Pull-up/Pull-downs This section describes the expected states of the (G)MCH I/O buffers during and immediately after the assertion of RSTIN#. This table only refers to the contributions on the interface from the (G)MCH and ...
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R Interface Signal Name Host I/F HHIT# HHITM# HLOCK# HREQ[4:0]# HTRDY# HRS[2:0]# HBREQ0# HPCREQ# HVREF HRCOMP HSWING HSCOMP Table 2-2. System Memory (DDR2) Reset and S3 States Interface Signal Name System Channel A Memory SCLK_A[5:0] (DDR2) SCLK_A[5:0]# SCS_A[3:0]# SMA_A[13:0] SBS_A[2:0] ...
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Signal Description Interface Signal Name System Channel B Memory SCLK_B[5:0] (DDR2) SCLK_B[5:0]# SCS_B[3:0]# SMA_B[13] SMA_B[12:11] SMA_B[10:8] SMA_B[7] SMA_B[6:0] SBS_B[2] SBS_B[1:0] SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] SDM_B[7:0] SDQS_B[7:0] SDQS_B[7:0]# SCKE_B[3:0] SODT_B[3:0] SRCOMP0 SRCOMP1 SM_SLEWIN[1:0] SM_SLEWOU{1:0] SMVREF[1:0] SOCOMP[1:0] 48 State During State After ...
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R Table 2-3. System Memory (DDR) Reset and S3 States Interface Signal Name System Channel A Memory SCLK_A[5:0] (DDR) SCLK_A[5:0]# SMA_A[13:9] SMA_A[8] SMA_A[7:6] SMA_A[5] SMA_A[4:0] SBS_A[2:0] SCS_A[3]# SCS_A[2:1]# SCS_A[0]# SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0] SDQS_A[7:0] SDQS_A[7:0]# SCKE_A[3:0] System Channel B ...
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Signal Description Interface Signal Name System SWE_B# Memory SDQ_B[63:0] (DDR) SDM_B[7:0] SDQS_B[7:0] SDQS_B[7:0]# SCKE_B[3:0] SRCOMP0 SRCOMP1 SM_SLEWIN[1:0] SM_SLEWOU[1:0] SMVREF[1:0] SOCOMP[1:0] Table 2-4. PCI Express* Graphics x16 Port Reset and S3 States Interface Signal Name PCI EXP_RXN[15:0] Express*- EXP_RXP[15:0] Graphics EXP_TXN[15:0] ...
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... TRI TRI I TERM HV TERM HV I TERM HV TERM TRI TRI I/O TERM PD TRI ® 82915G/82915GV/82915GL/82910GL GMCH only) State During State After RSTIN# I/O RSTIN# Deassertion Assertion TRI TRI O TRI TRI O TRI TRI O TRI TRI O TRI TRI ...
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Signal Description 52 R Datasheet ...
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... Host-PCI Express Bridge functions (controls PCI Express interface configurations and operating parameters). The third register block is for the 82915G/82915GV/82915GL/82910GL GMCH internal graphics functions. The (G)MCH internal registers (I/O Mapped, Configuration and PCI Express Extended Configuration registers) are accessible by the processor. The registers that reside within the lower 256 bytes of each device can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of CONFIG_ADDRESS that can only be accessed as a DWord ...
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Register Description Item R/WSC Read / Write Self Clear bit(s). These bits can be read and written. When the bit is ‘1’, hardware may clear the bit to ‘0’ based upon internal events, possibly sooner than any subsequent read could ...
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... Intel ICH6 logically constitute PCI Bus 0 to configuration software. This is shown in Figure 3-1. Figure 3-1. Conceptual Chipset PCI Configuration Diagram Device 1 (82915G/82915P/ 82915PL GMCH only Internal Graphics Bus 0, (82915G/82915GV/82915G L82910GL Device Datasheet Processor Intel 82915G/ 82915GV/ 82915GL/ ® 82915P/82915PL/82919GL (G)MCH PCI Configuration in I/O DRAM Interface Bus 0, Device 0 DMI Register Description PCI_Config_Dia 55 ...
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... Express memory address mapping). It also contains Isochronous and Virtual Channel controls in the PCI Express extended configuration space. • Device 2 – Internal Graphics Control (82915G/82915GV/82915GL/82910GL GMCH only). Logically, this appears as a PCI device residing on PCI bus 0. Physically, device 2 contains the configuration registers for 3D, 2D, and display functions. ...
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... Hex numbers represent address range size and not actual locations. Table 3-1. Device Number Assignment for Internal (G)MCH Devices Host Bridge / DRAM Controller Host-to-PCI Express* Bridge (virtual P2P) (Intel (G)MCH only) Internal Graphics Control (82915G/82915GV/82915GL/82910GL GMCH only) Datasheet Unused Unused EPBAR (G)MCH Function ® ...
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... PCI Bus 0 device. The Host-DMI Bridge entity within the (G)MCH is hardwired as Device 0 on PCI Bus 0. The Host-PCI Express Bridge entity within the (G)MCH is hardwired as Device 1 on PCI Bus 0. The 82915G/82915GV/82915GL/82910GL GMCH’s Device 2 contains the control registers for the Integrated Graphics Controller. The Intel ICH6 decodes the Type 0 access and generates a configuration access to the selected internal device ...
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R 3.3.3 Primary PCI and Downstream Configuration Mechanism If the Bus Number in the CONFIG_ADDRESS is non-zero, and falls outside the range claimed by the Host-PCI Express bridge (not between upper bound in device’s Subordinate Bus Number register and lower ...
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Register Description 3.3.4 PCI Express* Enhanced Configuration Mechanism PCI Express extends the configuration space to 4096 bytes per device/function as compared to 256 bytes allowed by PCI Specification, Revision 2.3. PCI Express configuration space is divided into a PCI 2.3 ...
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R To access this space (steps are performed only once by BIOS) 1. Use the PCI compatible configuration mechanism to enable the PCI Express enhanced configuration mechanism by writing 1 to bit 31 of the DEVEN register. ...
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Register Description ® 3.3.5 Intel 915x GMCH Configuration Cycle Flowchart ® Figure 3-6. Intel 915x GMCH Configuration Cycle Flowchart GMCH Generates Type 1 Access to PCI Express Device MCH allows cycle DMI resulting in ...
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R 3.4 I/O Mapped Registers The (G)MCH contains two registers that reside in the processor I/O address space − the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines ...
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Register Description Bit Access & Default 15:11 R/W 00h 10:8 R/W 000b 7:2 R/W 00h 1:0 3.4.2 CONFIG_DATA—Configuration Data Register I/O Address: Default Value: Access: Size: CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of configuration space ...
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R 4 Host Bridge/DRAM Controller Registers (D0:F0) The DRAM Controller registers are in Device 0 (D0), Function 0 (F0). Warning: Address locations that are not listed are considered Reserved registers locations. Reads to Reserved registers may return non-zero values. Writes ...
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Host Bridge/DRAM Controller Registers (D0:F0) Address Register Offset Symbol 52–53h GGC 54–57h DEVEN 58–8Fh 90h PAM0 91h PAM1 92h PAM2 93h PAM3 94h PAM4 95h PAM5 96h PAM6 97h LAC 98–9Bh 9Ch TOLUD 9Dh SMRAM 9Eh ESMRAMC 9F–C7h C8–C9h ERRSTS ...
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R Address Register Offset Symbol 10E–10F C0BNKARC 110–113h 114–117h C0DRT1 118–11Fh 120–123h C0DRC0 124–17Fh 180h C1DRB0 181h C1DRB1 182h C1DRB2 183h C1DRB3 184–187h 188h C1DRA0 189h C1DRA2 18A–18Bh 18Ch C1DCLKDIS 18Dh 18E–18Fh C1BNKARC 190–193h 194h C1DRT1 195–19Fh 1A0–1A3h C1DRC0 1A4–F0Fh ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1 Host Bridge/DRAM Controller PCI Register Details (D0:F0) 4.1.1 VID—Vendor Identification (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register combined with the Device Identification register uniquely identifies any PCI device. Bit Access ...
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R 4.1.3 PCICMD—PCI Command (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: Since (G)MCH Device 0 does not physically reside on Primary PCI bus, many of the bits are not implemented. Bit Access & Default 15: ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.4 PCISTS—PCI Status (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This status register reports the occurrence of error events on Device 0’s PCI interface. Since the (G)MCH Device 0 does not physically reside ...
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... Description Revision Identification Number (RID): This field indicates the number of times that this device in this component has been “stepped” through the manufacturing ® process. Refer to the Intel 82915G/82915P/82915GV/82910GL Express Chipset Specification Update for the value of the Revision ID Register. 0 09h 060000h ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.7 MLT—Master Latency Timer (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: Device 0 in the (G)MCH is not a PCI master. Therefore, this register is not implemented. Bit Access & Default 7:0 4.1.8 ...
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R 4.1.10 SID—Subsystem Identification (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This value is used to identify a particular subsystem. Bit Access & Default 15:0 R/WO 0000h 4.1.11 CAPPTR—Capabilities Pointer (D0:F0) PCI Device: Address Offset: Default Value: Access: ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.12 EPBAR—Egress Port Base Address (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This is the base address for the Egress Port MMIO configuration space. There is no physical memory within this 4-KB window ...
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R 4.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base Address (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This is the base address for the (G)MCH memory-mapped configuration space. There is no physical memory within this 16-KB window that can ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.14 PCIEXBAR—PCI Express* Register Range Base Address (D0:F0) (Intel PCI Device: Address Offset: Default Value: Access: Size: This is the base address for the PCI Express configuration space. This window of addresses contains the 4 ...
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R 4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the ...
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... Host Bridge/DRAM Controller Registers (D0:F0) 4.1.16 GGC—GMCH Graphics Control Register (D0:F0) (82915G/82915GV/82915GL/82910GL GMCH only) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default 15:7 6:4 R/W/L 011b 3 52h 0030h R/W/L 16 bits Descriptions Reserved Graphics Mode Select (GMS): This field is used to select the amount of main memory that is pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes ...
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... The PCIEXBAR register is enabled. Memory read and write transactions whose address bits 31:28 match PCIEXBAR 31:28 will be translated to configuration reads and writes within the (G)MCH. These translated cycles are routed as shown in the table above. 82915GV/82915GL/82910GL GMCH: Reserved. Reserved DMIBAR Enable (DMIBAREN DMIBAR is disabled and does not claim any memory. ...
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... Bus 0 Device 1 Function 0 is enabled and visible. The SDVO Presence hardware strap determines default value. Device 1 is disabled on Reset when the SDVO Presence strap (SDVO_CTLRDATA signal) is sampled high, and is enabled otherwise. 82915GV/82915GL/82910GL GMCH: Reserved. Host Bridge: Bus 0 Device 0 Function 0 can not be disabled and is therefore hardwired to 1. ...
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R 4.1.18 PAM0—Programmable Attribute Map 0 (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS area from 0F0000h– 0FFFFFh The (G)MCH allows programmable memory attributes on 13 Legacy ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.19 PAM1—Programmable Attribute Map 1 (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h– 0C7FFFh. Bit Access & Default 7:6 ...
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R 4.1.20 PAM2—Programmable Attribute Map 2 (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h– 0CFFFFh. Bit Access & Default 7:6 5:4 R/W 00b 3:2 ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.21 PAM3—Programmable Attribute Map 3 (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h– 0D7FFFh. Bit Access & Default 7:6 ...
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R 4.1.22 PAM4—Programmable Attribute Map 4 (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h- 0DFFFFh. Bit Access & Default 7:6 5:4 R/W 00b 3:2 ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.23 PAM5—Programmable Attribute Map 5 (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h- 0E7FFFh. Bit Access & Default 7:6 ...
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R 4.1.24 PAM6—Programmable Attribute Map 6 (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h– 0EFFFFh. Bit Access & Default 7:6 5:4 R/W 00b 3:2 ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.25 LAC—Legacy Access Control (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This 8-bit register controls a fixed DRAM hole from 15–16 MB. Bit Access & Default 7 R/W 0b 6:1 0 R/W 0b ...
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... This 8-bit register defines the Top of Low Usable DRAM. TSEG and Graphics Stolen Memory (82915G only) are within the DRAM space defined. From the top, the (G)MCH optionally claims DRAM for internal graphics if enabled (82915G/82915GV/82915GL/82910GL GMCH only), and DRAM for TSEG if enabled. These bits are LT Lockable. ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.27 SMRAM—System Management RAM Control (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function ...
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... Once D_LCK has been set, these bits become read only. NOTE: References to Graphics Stolen Memory only apply to the 82915G/82915GV/82915GL/82910GL GMCH only. TSEG Enable (T_EN): This bit Enables SMRAM memory for Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.29 ERRSTS—Error Status (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register is used to report various error conditions via the SERR DMI messaging mechanism. A SERR DMI message is generated on a ...
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R 4.1.30 ERRCMD—Error Command (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the (G)MCH responses to various system errors. Since the (G)MCH does not have an SERR# signal, SERR messages are passed from the (G)MCH to ...
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Host Bridge/DRAM Controller Registers (D0:F0) 4.1.31 SKPD—Scratchpad Data (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: This register holds 32 writable bits with no functionality behind them for the convenience of BIOS and graphics drivers. Bit Access ...
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R 5 MCHBAR Registers These registers are offset from the MCHBAR base address. Address Register Offset Symbol 100h C0DRB0 101h C0DRB1 102h C0DRB2 103h C0DRB3 104–107h 108h C0DRA0 109h C0DRA2 10A–10Bh 10Ch C0DCLKDIS 10Dh 10E–10F C0BNKARC 110–113h 114–117h C0DRT1 118–11Fh ...
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MCHBAR Registers Address Register Offset Symbol 195–19Fh 1A0–1A3h C1DRC0 1A4–F0Fh F10–F13h PMCFG F14h PMSTS 5.1 MCHBAR Register Details 5.1.1 C0DRB0—Channel A DRAM Rank Boundary Address 0 MMIO Range: Address Offset: Default Value: Access: Size: The DRAM Rank Boundary Register defines ...
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R Programming guide If Channel A is empty, all of the C0DRBs are programmed with 00h. C0DRB0 = Total memory in chA rank0 (in 32-MB increments) C0DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB increments) ______ ...
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MCHBAR Registers 5.1.2 C0DRB1—Channel A DRAM Rank Boundary Address 1 MMIO Range: Address Offset: Default Value: Access: Size: The operation of this register is detailed in the description for register C0DRB0. 5.1.3 C0DRB2—Channel A DRAM Rank Boundary Address 2 MMIO ...
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R 5.1.5 C0DRA0—Channel A DRAM Rank 0,1 Attribute MMIO Range: Address Offset: Default Value: Access: Size: The DRAM Rank Attribute Registers define the page sizes to be used when accessing different ranks. These registers should be left with their default ...
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MCHBAR Registers 5.1.7 C0DCLKDIS—Channel A DRAM Clock Disable MMIO Range: Address Offset: Default Value: Access: Size: This register can be used to disable the system memory clock signals to each DIMM slot. This can significantly reduce EMI and Power concerns ...
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R 5.1.8 C0BNKARC—Channel A DRAM Bank Architecture MMIO Range: Address Offset: Default Value: Access: Size: This register is used to program the bank architecture for each Rank. Bit Access & Default 15:8 7:6 R/W 00b 5:4 R/W 00b 3:2 R/W ...
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MCHBAR Registers 5.1.9 C0DRT1—Channel A DRAM Timing Register MMIO Range: Address Offset: Default Value: Access: Size: Bit Access & Default 31:24 23:20 R 18:10 9:8 R/W 01b 7 102 MCHBAR 114h 900122hh R/ bits ...
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R Bit Access & Default 6:4 R/W 010b 3 2:0 R/W 010b Datasheet Description DRAM RAS to CAS Delay (t ). This bit controls the number of clocks inserted RCD between a row activate command and a read or write ...
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MCHBAR Registers 5.1.10 C0DRC0—Channel A DRAM Controller Mode 0 MMIO Range: Address Offset: Default Value: Access: Size: Access & Bit Default 31:30 29 R/W 0b 28:11 10:8 R/W 000b 104 MCHBAR 120h 00000000h R/W 32 bits Description ...
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R Access & Bit Default 6:4 R/W 000 b 3:2 1:0 RO Datasheet Description Mode Select (SMS). These bits select the special operational mode of the DRAM interface. The special modes are intended for initialization at power up. 000 = ...
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MCHBAR Registers 5.1.11 C1DRB0—Channel B DRAM Rank Boundary Address 0 MMIO Range: Address Offset: Default Value: Access: Size: The operation of this register is detailed in the description for register C0DRB0. 5.1.12 C1DRB1—Channel B DRAM Rank Boundary Address 1 MMIO ...
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R 5.1.16 C1DRA2—Channel B DRAM Rank 2,3 Attribute MMIO Range: Address Offset: Default Value: Access: Size: The operation of this register is detailed in the description for register C0DRA0. 5.1.17 C1DCLKDIS—Channel B DRAM Clock Disable MMIO Range: Address Offset: Default ...
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MCHBAR Registers 5.1.21 PMCFG—Power Management Configuration MMIO Range: Address Offset: Default Value: Access: Size: Bit Access & Default 31:5 4 R/W 0b 3:0 5.1.22 PMSTS—Power Management Status MMIO Range: Address Offset: Default Value: Access: Size: This register is Reset by ...
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R 6 EPBAR Registers—Egress Port Register Summary These registers are offset from the EPBAR base address. Table 6-1. Egress Port Register Address Map Address Register Offset Symbol 044h–047h EPESD 050h–053h EPLE1D 058h– EPLE1A 05Fh 060h–063h EPLE2D 068h– EPLE2A 06Fh 6.1 ...
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EPBAR Registers—Egress Port Register Summary 6.1.1 EPESD—EP Element Self Description MMIO Range: Address Offset: Default Value: Access: Size: This register provides information about the root complex element containing this Link Declaration capability. Bit Access & Default 31:24 RO 00h 23:16 ...
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R 6.1.2 EPLE1D—EP Link Entry 1 Description MMIO Range: Address Offset: Default Value: Access: Size: This register provides the First part of a Link Entry that declares an internal link to another Root Complex Element. Bit Access & Default 31:24 ...
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EPBAR Registers—Egress Port Register Summary 6.1.4 EPLE2D—EP Link Entry 2 Description MMIO Range: Address Offset: Default Value: Access: Size: This register provides the First part of a Link Entry that declares an internal link to another Root Complex Element. Bit ...
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R 6.1.5 EPLE2A—EP Link Entry 2 Address MMIO Range: Address Offset: Default Value: Access: Size: This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element. Bit Access & Default 63:28 ...
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EPBAR Registers—Egress Port Register Summary 114 R Datasheet ...
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R 7 DMIBAR Registers—Direct Media Interface (DMI) RCRB This Root Complex Register Block (RCRB) controls the (G)MCH-Intel ICH6 serial interconnect. The base address of this space is programmed in DMIBAR in device 0 configuration space. These registers are offset from ...
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DMIBAR Registers—Direct Media Interface (DMI) RCRB 7.1 Direct Media Interface (DMI) RCRB Register Details 7.1.1 DMIVCECH—DMI Virtual Channel Enhanced Capability Header MMIO Range: Address Offset: Default Value: Access: Size: This register indicates DMI Virtual Channel capabilities. Bit Access & Default ...
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R 7.1.3 DMIPVCCAP2—DMI Port VC Capability Register 2 MMIO Range: Address Offset: Default Value: Access: Size: This register describes the configuration of Virtual Channels associated with this port. Bit Access & Default 31:24 RO 00h 23:8 7:0 RO 01h 7.1.4 ...
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DMIBAR Registers—Direct Media Interface (DMI) RCRB 7.1.5 DMIVC0RCAP—DMI VC0 Resource Capability MMIO Range: Address Offset: Default Value: Access: Size: Bit Access & Default 31:24 RO 00h 23 22:16 RO 00h 13:8 7:0 RO 01h ...
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R 7.1.6 DMIVC0RCTL0—DMI VC0 Resource Control MMIO Range: Address Offset: Default Value: Access: Size: This register controls the resources associated with PCI Express Virtual Channel 0. Bit Access & Default 30:27 26:24 RO 000b 23:20 19:17 R/W ...
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DMIBAR Registers—Direct Media Interface (DMI) RCRB 7.1.7 DMIVC0RSTS—DMI VC0 Resource Status MMIO Range: Address Offset: Default Value: Access: Size: This register reports the Virtual Channel specific status. Bit Access & Default 15 7.1.8 DMIVC1RCAP—DMI ...
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R 7.1.9 DMIVC1RCTL1—DMI VC1 Resource Control MMIO Range: Address Offset: Default Value: Access: Size: This register controls the resources associated with Virtual Channel 1. Bit Access & Default 31 R/W 0b 30: 26:24 R/W 001b 23:20 19:17 R/W ...
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DMIBAR Registers—Direct Media Interface (DMI) RCRB 7.1.11 DMILCAP—DMI Link Capabilities MMIO Range: Address Offset: Default Value: Access: Size: This register indicates DMI specific capabilities. Bit Access & Default 31:18 17:15 R/WO 010b 14:12 R/WO 010b 11:10 RO 11b 9:4 RO ...
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R 7.1.13 DMILSTS—DMI Link Status MMIO Range: Address Offset: Default Value: Access: Size: This register indicates DMI status. Bit Access & Default 15:10 9:4 RO 00h 3 Datasheet DMIBAR Registers—Direct Media Interface (DMI) RCRB DMIBAR 08Ah 0001h RO ...
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DMIBAR Registers—Direct Media Interface (DMI) RCRB 124 R Datasheet ...
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R 8 Host-PCI Express* Bridge Registers (D1:F0) ® (Intel 82915G/82915P/82915PL Only) Device 1contains the controls associated with the PCI Express x16 root port that is the intended to attach as the point for external graphics typically referred to ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) Address Register Offset Symbol 0F–17h 18h PBUSN1 19h SBUSN1 1Ah SUBUSN1 1Bh 1Ch IOBASE1 1Dh IOLIMIT1 1Eh–1Fh SSTS1 20–21h MBASE1 22–23h MLIMIT1 24–25h PMBASE1 26–27h PMLIMIT1 28–33h 34h CAPPTR1 35–3Bh 3Ch INTRLINE1 ...
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R Address Register Offset Symbol B2–B3h LSTS B4–B7h SLOTCAP B8–B9h SLOTCTL BA–BBh SLOTSTS BC–BDh RCTL BE–BFh C0–C3h RSTS C4–EBh EC–EFh PEGLC F0–FFh 100–103h VCECH 104–107h PVCCAP1 108–10Bh PVCCAP2 10C–10Dh PVCCTL 10E–10Fh 110–113h VC0RCAP 114–117h VC0RCTL 118–119h 11A–11Bh VC0RSTS 11C–11Fh VC1RCAP ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1 Host-PCI Express* Bridge PCI Register Details (D1:F0) 8.1.1 VID1—Vendor Identification (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register combined with the Device Identification register uniquely identifies any PCI ...
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R 8.1.3 PCICMD1—PCI Command (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default 15: ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) Bit Access & Default R/W 0b 8.1.4 PCISTS1—PCI Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register reports the occurrence of error ...
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R Bit Access & Default 10:9 RO 00b 2:0 Datasheet Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) ...
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... Description Revision Identification Number (RID1): This field indicates the number of times that this device in this component has been “stepped” through the manufacturing ® process. Refer to the Intel 82915G/82915P/82915PL/82915GV/82915GL/82910GL Express Chipset Specification Update for the value of the Revision ID Register. 1 09h 060400h ...
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R 8.1.7 CL1—Cache Line Size (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default 7:0 R/W 00h 8.1.8 HDR1—Header Type (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register identifies the header layout of ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.10 SBUSN1—Secondary Bus Number (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register identifies the bus number assigned to the second bus side of the “virtual” bridge i.e. to PCI ...
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R 8.1.12 IOBASE1—I/O Base Address (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the processor-to-PCI Express Graphics I/O access routing based on the following formula: IO_BASE ≤ address ≤ IO_LIMIT Only the upper 4 bits are ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.14 SSTS1—Secondary Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., PCI Express ...
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R 8.1.15 MBASE1—Memory Base Address (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the processor to PCI Express Graphics non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.16 MLIMIT1—Memory Limit Address (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the processor-to-PCI Express Graphics non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ...
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R 8.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register, in conjunction with the corresponding Upper Base Address register, controls the processor-to-PCI Express Graphics prefetchable memory access routing based on the following formula: ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register, in conjunction with the corresponding Upper Limit Address register, controls the processor-to-PCI Express Graphics prefetchable memory ...
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R 8.1.20 INTRLINE1—Interrupt Line (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register contains interrupt line routing information. The device itself does not use this value; rather device drivers and operating systems use it to determine priority and ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.22 BCTRL1—Bridge Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The BCTRL provides additional control for ...
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R Bit Access & Default Datasheet Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) Description ISA Enable (ISAEN): This bit is needed to exclude legacy resource decode to route ISA resources ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.23 PM_CAPID1—Power Management Capabilities (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default 31:27 RO 19h 24:22 RO 000b ...
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R 8.1.24 PM_CS1—Power Management Control/Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default 31: 14:13 RO 00b 12 R/W/S 0b 7:2 1:0 R/W 00b Datasheet Host-PCI Express* Bridge Registers ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.25 SS_CAPID—Subsystem ID and Vendor ID Capabilities (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This capability is used to uniquely identify the subsystem where the PCI device resides. Because this ...
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R 8.1.27 MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: When a device supports MSI, it can generate an interrupt request to the processor by writing a predefined data item (a message ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.28 MC—Message Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: System software can modify bits in this register, but the device is prohibited from doing so. If the device writes ...
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R 8.1.29 MA—Message Address (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default 31:2 R/W 00000000 h 1:0 RO 00b 8.1.30 MD—Message Data (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.31 PEG_CAPL—PCI Express* Capability List (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register enumerates the PCI Express capability structure. Bit Access & Default 15:8 RO 00h 7:0 RO 10h ...
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R 8.1.33 DCAP—Device Capabilities (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register indicates PCI Express link capabilities. Bit Access & Default 31 4:3 RO 00b 2:0 RO 000b Datasheet Host-PCI Express* Bridge Registers (D1:F0) ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.34 DCTL—Device Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors ...
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R 8.1.35 DSTS—Device Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register reflects status corresponding to controls in the Device Control register. Note: The error reporting bits are in reference to errors detected by this device, not ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.36 LCAP—Link Capabilities (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register indicates PCI Express device specific capabilities. Bit Access & Default 31:24 RO 02h 23:18 17:15 R/WO 010b 14:12 ...
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R 8.1.37 LCTL—Link Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register allows control of PCI Express link. Bit Access & Default 15 ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.38 LSTS—Link Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register indicates PCI Express link status. Bit Access & Default 15: ...
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R 8.1.39 SLOTCAP—Slot Capabilities (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: PCI Express slot-related registers allow for the support of Hot-Plug. Bit Access & Default 31:19 R/WO 0000h 18:17 16:15 R/WO 00b 14:7 R/WO 00h 6 R/WO 0b ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.40 SLOTCTL—Slot Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: PCI Express slot related registers allow for the support of Hot-Plug. Bit Access & Default 15:10 9:8 R/W 01b 7:6 ...
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R 8.1.41 SLOTSTS—Slot Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: PCI Express slot-related registers allow for the support of Hot-Plug. Bit Access & Default 15 R/ R/WC 0b 2:1 0 ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.42 RCTL—Root Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine ...
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R 8.1.43 RSTS—Root Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register provides information about PCI Express Root Complex specific parameters. Bit Access & Default 31: R/W/C 0b 15:0 RO 0000h Datasheet Host-PCI ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.44 PEGLC—PCI Express*-G Legacy Control PCI Device: Address Offset: Default Value: Access: Size: This register controls functionality that is needed by Legacy (non-PCI Express aware) OS’s during run time. Bit Access & ...
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R 8.1.45 VCECH—Virtual Channel Enhanced Capability Header (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register indicates PCI Express device Virtual Channel capabilities. Note: Extended capability structures for PCI Express devices are located in PCI Express extended configuration ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.47 PVCCAP2—Port VC Capability Register 2 (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit Access & ...
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R 8.1.49 VC0RCAP—VC0 Resource Capability (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default 31: 14:0 8.1.50 VC0RCTL—VC0 Resource Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register controls the ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.51 VC0RSTS—VC0 Resource Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register reports the Virtual Channel specific status. Bit Access & Default 15 8.1.52 VC1RCAP—VC1 ...
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R 8.1.53 VC1RCTL—VC1 Resource Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: Controls the resources associated with PCI Express Virtual Channel 1. Bit Access & Default 31 R/W 0b 30:27 26:24 R/W 001b 23:8 7:1 R/W 00h 0 ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.54 VC1RSTS—VC1 Resource Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register reports the Virtual Channel specific status. Bit Access & Default 15 8.1.55 RCLDECH—Root ...
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R 8.1.56 ESD—Element Self Description (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register provides information about the root complex element containing this Link Declaration Capability. Bit Access & Default 31:24 RO 02h 23:16 R/WO 00h 15:8 RO ...
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 8.1.57 LE1D—Link Entry 1 Description (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register provides the First part of a Link Entry that declares an internal link to another Root ...
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R 8.1.58 LE1A—Link Entry 1 Address (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element. Bit Access & Default 63:32 ...
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...
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... SID2 30–33h ROMADR 34h CAPPOINT 35–3Bh — Datasheet Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Cache Line Size Master Latency Timer Header Type ...
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... Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) Address Register Offset Symbol 3Ch INTRLINE 3Dh INTRPIN 3Eh MINGNT 3Fh MAXLAT 40–43h — 44h MCAPPTR 45–47h — 48–50h MCAPID 51h — 52–53h MGGC 54–57h MDEVENde v0F0 58–5Bh — 5C–5Fh BSM 60– ...
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... This register, combined with the Vendor Identification register, uniquely identifies any PCI device. Bit Access & Default 15:0 RO 2582h Datasheet Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 2 00h 8086h RO 16 bits Description Vendor Identification Number (VID): PCI standard identification for Intel. 2 02h ...
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... Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 9.1.3 PCICMD2—PCI Command (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory. ...
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... 2:0 Datasheet Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 2 06h 0090h RO 16 bits Description Detected Parity Error (DPE): Since the IGD does not detect parity; this bit is always hardwired to 0. Signaled System Error (SSE): The IGD never asserts SERR#, therefore this bit is hardwired to 0 ...
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... Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 9.1.5 RID2—Revision Identification (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: This register contains the revision number for Device 2 Functions 0 and 1 Bit Access & Default 7:0 RO 00h 9.1.6 CC—Class Code (D2:F0) PCI Device: Address Offset: ...
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... Bit Access & Default 7:0 RO 00h Datasheet Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 2 0Ch 00h RO 8 bits Description Cache Line Size (CLS): This field is hardwired to 0s. The IGD PCI compliant master, does not use the Memory Write and Invalidate command and, in general, does not perform operations based on cache line size ...
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... Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 9.1.9 HDR2—Header Type (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: This register contains the Header Type of the IGD. Bit Access & Default 6:0 RO 00h 9.1.10 MMADR—Memory Mapped Range Address (D2:F0) ...
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... R/W 0000h 2:1 RO 00b Datasheet Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 2 14h 00000001h RO, R/W 32 bits Description Reserved IO Base Address: Set by the OS, these bits correspond to address signals [15:3]. Memory Type: Hardwired indicate 32-bit address. Memory / I/O Space: Hardwired indicate I/O space. ...
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... Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 9.1.12 GMADR—Graphics Memory Range Address (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: IGD graphics memory base address is specified in this register. Bit Access & Default 31:28 R R/W/L 0b 26:4 RO 000000h 2:1 RO 00b ...
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... Access: Size: Bit Access & Default 15:0 R/WO 0000h Datasheet Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 2 1Ch 00000000h RO, R/W 32 bits Description Memory Base Address: Set by the OS, these bits correspond to address signals [31:18]. Address Mask: Hardwired indicate 256-KB address range. ...
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... Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 9.1.15 SID2—Subsystem Identification (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default 15:0 R/WO 0000h 9.1.16 ROMADR—Video BIOS ROM Base Address (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: The IGD does not use a separate BIOS ROM; therefore, this register is hardwired to 0s. ...
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... Bit Access & Default 7:0 RO 01h Datasheet Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 2 34h D0h RO 8 bits Description Capabilities Pointer Value: This field contains an offset into the function’s PCI configuration space for the first item in the New Capabilities Linked List; the Power Management Capabilities ID registers at address D0h ...
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... Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 9.1.20 MINGNT—Minimum Grant (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default 7:0 RO 00h 9.1.21 MAXLAT—Maximum Latency (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default ...
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... Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From the top of low used DRAM, GMCH claims MBs of DRAM for internal graphics, if enabled. Bit Access & Default 31:20 RO 078h 19:0 Datasheet Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only 52h 16 bits 2 0 54h 32 bits 2 5Ch ...
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... Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 9.1.27 MSAC—Multi Size Aperture Control (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: This register determines the size of the graphics memory aperture in function 0 and in the trusted space. By default, the aperture size is 256 MB (bit 27 read only). If bit 1 is set then the aperture size is limited to 128 MB ...
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... RO 0b 2:0 RO 010b Datasheet Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 2 D2h 0022h RO 16 bits Description PME Support: This field indicates the power states in which the IGD may assert PME#. Hardwired indicate that the IGD does not assert the PME# signal. ...
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... Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 9.1.30 PMCS—Power Management Control/Status (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: Bit Access & Default 14 7:2 1:0 R/W 00b 190 2 D4h 0000h RO, R/W 16 bits Description PME_Status: This bit indicate that IGD does not support PME# generation from D3 (cold) ...
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... R/W 00h 15:8 R/W 00h 7:0 R/W 00h Datasheet Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 2 E0h 0000h R/W 16 bits Description SW scratch bits Software Flag: This field is used to indicate caller and SMI function desired, as well as return result. GMCH Software SMI Event: When Set, this bit will trigger an SMI. Software ...
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... Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) 9.1.33 ASLS—ASL Storage (D2:F0) PCI Device: Address Offset: Default Value: Access: Size: This SW scratch register only needs to be read/write accessible. The exact bit register usage must be worked out in common between System BIOS and driver software, but storage for switching/indicating devices is possible with this amount. For each device, the ASL control method requires two bits for _DOD (BIOS detectable yes or no, VGA/Non VGA) ...
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... MINGNT 3Fh MAXLAT 40–43h 44h MCAPPTR 45–47h Datasheet Device 2 Function 1 (D2:F1) Configuration Registers (Intel® 82915G/82915GV/82915GL/ 82910GL Only) Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Register Cache Line Size Master Latency Timer Header Type Register — ...
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... Device 2 Function 1 (D2:F1) Configuration Registers (Intel® 82915G/82915GV/82915GL/ 82910GL Only) Address Register Offset Symbol 48–50h MCAPID 51h 52–53h MGGC 54–57h MDEVENdev0f0 58–5Bh 5C–5Fh BSM 60–CFh D0–D1h PMCAPID D2–D3h PMCAP D4–D5h PMCS D6–DFh E0–E1h SWSMI E2–FBh FC–FFh ASLS 10.1 Device 2 Function 1 Configuration Register Details (D2:F1) 10 ...
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... R R R/W 0b Datasheet Device 2 Function 1 (D2:F1) Configuration Registers (Intel® 82915G/82915GV/82915GL/ 82910GL Only) 2 04h 0000h RO, R/W 16 bits Description Reserved Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0. SERR Enable (SERRE): Not Implemented. Hardwired to 0. Address/Data Stepping Enable (ADSTEP): Not Implemented. Hardwired to 0. ...
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... Device 2 Function 1 (D2:F1) Configuration Registers (Intel® 82915G/82915GV/82915GL/ 82910GL Only) 10.1.4 PCISTS2—PCI Status (D2:F1) PCI Device: Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD ...
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... Default Value: Access: Size: This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0 implemented as common hardware with two access addresses. Datasheet Device 2 Function 1 (D2:F1) Configuration Registers (Intel® 82915G/82915GV/82915GL/ 82910GL Only) 2 08h See description below RO 8 bits 2 ...
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... Device 2 Function 1 (D2:F1) Configuration Registers (Intel® 82915G/82915GV/82915GL/ 82910GL Only) 10.1.8 MLT2—Master Latency Timer (D2:F1) PCI Device: Address Offset: Default Value: Access: Size: This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0 implemented as common hardware with two access addresses. ...
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... Address Offset: Default Value: Access: Size: This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0 implemented as common hardware with two access addresses. Datasheet Device 2 Function 1 (D2:F1) Configuration Registers (Intel® 82915G/82915GV/82915GL/ 82910GL Only) 2 2Ch 0000h R/WO 16 bits 2 2Eh ...
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... Device 2 Function 1 (D2:F1) Configuration Registers (Intel® 82915G/82915GV/82915GL/ 82910GL Only) 10.1.15 MINGNT—Minimum Grant Register (D2:F1) PCI Device: Address Offset: Default Value: Access: Size: This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0 implemented as common hardware with two access addresses. ...