LXT6251AQE Intel Corporation, LXT6251AQE Datasheet
LXT6251AQE
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LXT6251AQE Summary of contents
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LXT6251A 21 E1 SDH Mapper The LXT6251A 21E1 Mapper performs asynchronous mapping and demapping PDH signals into SDH. The PDH side interfaces with E1 LIUs and framers via NRZ Clock & Data, while the SDH side uses ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ® ...
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Contents 1.0 Block Diagram 2.0 Pin Assignments and Signal Descriptions 3.0 Functional Description 3.1 Introduction..........................................................................................................16 3.2 Receive Section, Terminal Mode ........................................................................16 3.2.1 Receive Alarms ......................................................................................17 3.2.1.1 Parity Alarm ...............................................................................17 3.2.1.2 Loss of Multiframe .....................................................................17 3.3 High Order Path Adaptation ................................................................................18 ...
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LXT6251A — SDH Mapper 4.2.2 J2 Processing......................................................................................... 27 4.2.2.1 J2 Memory Access .................................................................... 28 4.2.3 K4 Processing ........................................................................................ 28 4.2.4 N2 Processing........................................................................................ 28 4.3 High Order Path Adaptation ................................................................................ 29 5.0 Add/Drop Configuration 5.1 ADM Receive ...................................................................................................... 30 ...
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GLOB_INTS—Global Interrupt Source (00CH)......................................60 8.5.2 TRIB_ISRC—Tributary Interrupt Source Identification (00F–00DH) ......60 8.5.3 TRIB_INT—Tributary Interrupt (x1–x0H)................................................61 8.5.4 TRIB_INTE—Tributary Interrupt Enable (x5–x4H) .................................62 8.6 Status and Control Registers ..............................................................................63 8.6.1 TRIB_STA—Tributary Status (x3–x2H)..................................................63 8.6.2 BIP2_ERRCNT—BIP2 Error Counter (x7–x6H) .....................................63 8.6.3 REI_CNT—Remote ...
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LXT6251A — SDH Mapper Tables 1 Signal Description Nomenclature.......................................................................... 9 2 Pin Descriptions .................................................................................................... 9 3 Power, Ground, and No Connects ...................................................................... 15 4 Enhanced RDI Interpretation............................................................................... 23 5 Enhanced RDI Generation .................................................................................. 28 6 Multiplex Telecom Bus ...
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Block Diagram Figure 1. LXT6251A Block Diagram 21 E1 Clock 21 E1 Data E1 Line Interface units E1 Clock E1 Data Datasheet LXT6251A 21 Channel Mapper VC-12 Fixed Path Pointer Terminatio Generator FIFO, n S/P Microcontroller Interface (Intel/Motorola selectable) ...
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... LXT6251A is the unique identifier for this product family. QE indicates the family member. Rev # Identifies the particular silicon “stepping” — refer to the specification update for additional stepping information. Lot # Identifies the batch. FPO # Identifies the Finish Process Order. 8 LXT6251AQE XX XXXXXXXXXXXXXX XXXXXXXXX Definition 156 GND_5 155 VCC_3 ...
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Table 1. Signal Description Nomenclature Type I O I/O 1 TTLin 1 HiZ 1. Some signals indicate buffer strength. For example, HiZ-4ma indicates a high-impedance buffer capable of sourcing 4 ma. Table 2. Pin Descriptions (Sheet Pin ...
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LXT6251A — SDH Mapper Table 2. Pin Descriptions (Continued) (Sheet Pin # Name I 126 MTD17 TTL in I 130 MTD18 TTL in I 137 MTD19 TTL in I 141 MTD20 TTL in I 146 ...
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Table 2. Pin Descriptions (Continued) (Sheet Pin # Name I 138 MTC19 TTL in I 140 MTC20 TTL in I 147 MTC21 TTL DTD1 HiZ - 2mA O 48 DTD2 HiZ - 2mA O ...
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LXT6251A — SDH Mapper Table 2. Pin Descriptions (Continued) (Sheet Pin # Name O 145 DTD21 HiZ - 2mA O 42 DTC1 HiZ - 2mA O 49 DTC2 HiZ - 2mA O 56 DTC3 HiZ ...
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Table 2. Pin Descriptions (Continued) (Sheet Pin # Name O 204-197 MTBDATA <7:0> HiZ - 4mA O 196 MTBPAR HiZ - 4mA I 193 MTBYCK TTLin I/O 191 MTBJ0J1EN TTLin - 4mA I/O 188 MTBH4EN TTLin - ...
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LXT6251A — SDH Mapper Table 2. Pin Descriptions (Continued) (Sheet Pin # Name I 176 PTTUGA TTLin I 177 PTTUGB TTLin I 178 PTSOH TTLin O 40 DSAPDATA HiZ - 2mA O 39 DSAPCLK HiZ ...
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Table 2. Pin Descriptions (Continued) (Sheet Pin # Name 27 AS TTLin 148 SCANTEST TTLin-48PU 160 SCANEN ITTLin-48PU I 153 JTCK TTLin-48PU I 152 JTMS TTLin-48PU I 151 JTRS TTLin-35PD 150 JTDI ITTLin-48PU O 149 JTDO HiZ-2mA ...
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LXT6251A — SDH Mapper 3.0 Functional Description 3.1 Introduction The LXT6251A performs mapping and demapping of 21 channels of E1 PDH tributaries into and out of the SDH hierarchy. It supports two system configurations, terminal or Add/Drop multiplexing, ...
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Figure 3. LXT6251A Block Diagram Lower order Path Adaption MTD<1:21> FIFO S/P MTC<1:21> LPA MRAPDATA Remote MRAPCLK Alarm MRAPFRM Processing A<8:0> DATA<7:0> CS Synchronous Equipment Management Function (SEMF) Interface WR/RW RD/E DSAPDATA Serial DSAPCLK Alarm Processing DSPAFRM DTD<1:21> Desynchronizer P/S ...
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LXT6251A — SDH Mapper 3.3 High Order Path Adaptation Within each of the 21 TU-12 demapper blocks, the telecom bus data bytes first enter the higher order path adaptation (HPA) block for TU-12 pointer interpretation. The TU-12 pointer ...
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TU Loss of Pointer (LOP invalid pointer state is detected in the TU pointer, the TU-LOP status bit in Tributary Status (x3–x2H)” on page 63 normal or AIS pointer state after 8 consecutive invalid pointer values or ...
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LXT6251A — SDH Mapper To read the BIP counter registers, the microprocessor must first perform a write (any value) to either (x6H,x7H), then wait at least three cycles of DTBYCK (0.5uS in STM-0) before reading the two registers. ...
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Unequipped Detection (V5, bits 5-7) The Unequipped (UNEQP) status bit will be set in page ‘000’ is detected in the signal label for five consecutive multiframes cleared when the signal label equals a pattern ...
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LXT6251A — SDH Mapper 3.4.2.1 J2 Memory Access The J2 RAM for each tributary is indirectly accessible by the microprocessor. That is, there is a single data port to access the data, while the address is internally generated ...
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Trace Identifier Mismatch The chip compares the received J2 string with the one stored in memory. If the calculated CRC-7 matches that of the received value, but there are errors in the comparison of the remaining 15 bytes, the ...
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LXT6251A — SDH Mapper 3.4.5.1 TU-AIS Alarm V1/V2 = FFh for 8 consecutive multiframes 3.4.5.2 TU-LOP Alarm V1/V2 invalid for 8 consecutive multiframes 3.4.5.3 Signal Label Mismatch Signal Label invalid for 5 consecutive multiframes. A VC-AIS is also ...
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The external jitter attenuator must meet the following specifications or the final output jitter cannot be guaranteed to meet ITU G.783: • Loop Bandwidth lower • An elastic buffer of at least 32 bits • First ...
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LXT6251A — SDH Mapper 4.0 Transmit Section, Terminal Mode At the MTDx/MTCx input pins, the Mapper expects to receive asynchronous E1 signals in the form of NRZ data and clock. The mapper also requires the Telecom Bus timing ...
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Two bits in “ERRI_CONF—Error Insert Configuration (xDH)” on page 58 of the REI bit. First, the XmtLptReiEn bit can be set to ‘0’ to disable the automatic response to the RAP data. By default this bit is set to ‘1’. ...
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LXT6251A — SDH Mapper 4.2.2.1 J2 Memory Access The J2 RAM for each tributary is indirectly accessible by the microprocessor. That is, there is a single data port to access the data, while the address is internally generated ...
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High Order Path Adaptation After low order path termination, the completed 35 byte by 4 multiframe VC-12 data enters the HPA block. At this stage, the four pointer bytes V1-V4 are added to complete the 36 byte by 4 ...
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LXT6251A — SDH Mapper 5.0 Add/Drop Configuration The LXT6251A can be configured to operate as an Add/Drop multiplexer by setting the OpMode bit in “GLOB_CONF—Global Configuration (000H)” on page 55 internal configurations to change from the terminal mode: ...
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DTBDATA input, if set to ‘1’, the TU time slot data is added from an E1 input port; which port is determined by the Port Mapping registers. Finally, as with the receive section, the Port Mapping function is enabled. ...
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LXT6251A — SDH Mapper 5.2.1.2 PTTUGx The PTTUGA and PTTUGB pins are used only in STM-1 mode to control the pass through of the other TUG-3 payloads not being processed by the device. The need for this function ...
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Figure 7. ADM Multi-chip Configuration A VCC LXT6051 PTSOH DTBTUGEN1 PTTUGA DTBTUGEN2 PTTUGB DTBTUGEN3 DTBTUGEN A: STM-1 ADM with access to TUG3 #2 Pass-Thru of TUG3 # STM-1 ADM with access to TUG3 #2, #3 Pass-Thru of TUG3 ...
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LXT6251A — SDH Mapper 6.0 Application Information 6.1 Port Mapping Configuration To allow for the design of a cost-reduced ADM mapper module, the LXT6251A supports a programmable E1 port mapping feature that allows each E1 I/O port to ...
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Table 7. E1 Port Time Slot Assignment (Continued) Tributary Circuit (Port) Register Address 15 16Fh 16 170h 17 171h 18 172h 19 173h 20 174h 21 175h 6.2 Telecom Bus Interface The LXT6251A uses an industry standard Telecom Bus to ...
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LXT6251A — SDH Mapper MTBTUGEN Note: Note on Telecom Bus Timing Reference: All Telecom Bus timing signals (MTBH4EN, MTBPAYEN, MTBJ0EN and MTBTUGEN) are sampled on the falling edge of the MTBYCK clock, and the output data (MTBPAR and ...
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Demultiplexer Telecom Bus In both terminal and ADM configurations, the demultiplexer side Telecom Bus operates in a co- directional mode, meaning that both the timing signals and the data are inputs to the LXT6251A. The enable signals are coincident ...
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LXT6251A — SDH Mapper Figure 8. STM-0 Telecom Bus Timing STM-0 Receive Telecom Bus Timing (Terminal & Add/Drop) DTBYCK Input DTBJ0J1EN J0 Input DTBPAYEN Input DTBDATA A2 J0 Input Goes HI one clock cycle after H4 = 00, ...
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Figure 9. Terminal STM-1 Telecom Bus Timing ( STM-1 Receive Telecom Bus Timing DTBYCK Input DTBJ0J1EN J0 Input DTBPAYEN Input DTBTUGEN Input DTBTUGEN1 from OHT DTBDATA Input STM-1 Transmit Telecom Bus Timing MTBYCK Input MTBJ0J1EN J0 Input ...
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LXT6251A — SDH Mapper Figure 11. ADM STM-1 Telecom Bus Timing w/ PTSOH = 0 STM-1 Receive Telecom Bus Timing - ADM Slave MTBYCK, DTBYCK Inputs DTBJ0J1 J0 Input DTBPAYEN Input DTBTUGEN Input DTBTUGEN1 from OHT DTBDATA A2 ...
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Figure 12. SAP Bus Connections for Terminal & ADM MTD/MTC E1 Ports Terminal MTB Telecom Bus Mapper RAP TX REI, RDI Alarm Status Terminal Mapper SAP RX DTB Telecom Bus DTD/DTC E1 Ports Terminal Figure 13. SAP Bus Frame Format ...
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LXT6251A — SDH Mapper 7.0 Test Specifications Note: Minimum and maximum values in tables 9 though 11 represent the performance specifications of the LXT6251A and are guaranteed by test unless otherwise noted. Minimum and maximum values in tables ...
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Figure 14. Tributary Timing MTCx MTDx t DE1pwh DTCx DTDx Table 11. Tributary Timing Parameters Parameter MTCx Input E1 Clock pulse width low MTCx Input E1 Clock pulse width high MTCx Input E1 Clock cycle time MTDx setup time to ...
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LXT6251A — SDH Mapper Figure 15. Receive Telecom Bus Timing TERMINAL and ADD/DROP MODE DTBCLK DTBDATA<7:0> DTBJ0J1EN DTBPAYEN DTBH4EN DTBTUGEN ADD/DROP MODE ONLY MTBCLK DTBDATA<7:0> DTBJ0J1EN DTBPAYEN DTBH4EN DTBTUGEN DPTTUGA DPTTUGB Table 12. Receive Telecom Bus Timing Parameters ...
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Figure 16. Transmit Telecom Bus Timing - Terminal MTBCLK t MTBsu MTBJ0J1 MTBPAYEN MTBH4EN MTBTUGEN MTBDATA<7:0> MTBDOE Table 13. Transmit Telecom Bus Timing - Terminal Parameters Parameter MTBCLK Input clock cycle time Any telecom bus timing input setup time to ...
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LXT6251A — SDH Mapper Figure 17. Transmit Telecom Bus Timing - ADM Parameters MTBYCK MTBJ0J1 MTBPAYEN MTBH4EN MTBDATA<7:0> MTBDOE Table 14. Transmit Telecom Bus Timing - ADM Parameters Parameter MTBCLK Input clock cycle time Any telecom bus timing ...
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Figure 18. Microprocessor Data Read Timing MicroProcessor Read Timing (Intel Mode) t SAR A<8:0> t SALR t t HALR SCR SLR VRD RD INT t DDR D<7:0> t ADR t AAC t AAC Table ...
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LXT6251A — SDH Mapper Table 15. Microprocessor Data Read Timing Parameters Parameter D<7:0> bus driven from active read D<7:0> access time from active read D<7:0> hold from inactive read D<7:0> HIgh impedance from inactive read Valid read pulse ...
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Table 16. Microprocessor Data Write Timing Parameters Parameter A<8:0> setup time to active write A<8:0> hold time from inactive write A<8:0> setup time to latch A<8:0> hold time from latch Valid latch pulse width AS rising edge to active write ...
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LXT6251A — SDH Mapper 8.0 Microprocessor Interface & Register Definitions 8.1 Microprocessor Interface The LXT6251A incorporates an asynchronous microprocessor interface. A microprocessor can be connected to the LXT6251A for reading and writing data via the microprocessor interface pins. ...
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When a multiplexed data/address bus is used, the falling edge of the AS input latches the address provided on A<8:0>. If the address and data are not multiplexed the AS pin should be tied High. Timing diagrams for the Intel ...
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LXT6251A — SDH Mapper For example, when a tributary incurs a Signal Label Mismatch (SLM), if the interrupt is enabled, the SlmAlm bit in the interrupt register will be set causing the device interrupt pin to become active. ...
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Nine address bits are used to access the LXT6251A register (512 byte address space). Global registers occupy memory space from 000H to 00FH, and from 160H and above. Registers pertaining to the individual TU tributaries are accessed from memory locations ...
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LXT6251A — SDH Mapper When the LXT6251A is reset, it sets its registers to predetermined default states. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it Default does not ...
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Table 17. Register Address Map Address Mnemonic Global Configuration Registers 160H — 161–175H TU_TS_CONF 176–1FFH — 8.4 Configuration Registers The registers described in this section are related to global configuration. The global address space includes 000H through 00FH, as well ...
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LXT6251A — SDH Mapper Bit Name Sets the form of the unequipped signal generated by all transmit tributary LUG blocks, as defined in G707, section 6.2.4.2. 2 UNEQMode 0 = Unequipped 1 = Supervisory Unequipped Master configuration for ...
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Bit Name 2 Trib3 (3, Add Pass through. 1 Trib2 (2, Add Pass through. 0 Trib1 (1, Add Pass through. 8.4.3 TU_TS_CONF—TU Time Slot Configuration (161–175H) 21 Registers; ...
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LXT6251A — SDH Mapper Bit Name 7:0 J2MemReset No specific value. A write resets the memory pointer. 8.4.6 J2_ESDATA—J2 Expected String Data (xCH) x=1–15H This register is used to access the J2 memory for this receive channel. Successive ...
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Bit Name Enable/Disable automatic hardware updates of V5 RDI bit. Used when the microprocessor needs direct control of RDI. 4 XmtLptRdiEn 1 = Enable 0 = Disable Force active status of V5 RDI. Also causes K4 ERDI bits to be ...
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LXT6251A — SDH Mapper Bit Name 7:0 ChipID Chip Identification < 7:0> 8.5 Interrupt Registers 8.5.1 GLOB_INTS—Global Interrupt Source (00CH) The Tributary Alarm Group identifies the tributary group that is in alarm. The microprocessor will require two reads ...
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Bit Name 11 Trib12 1 = Tributary has alarm. 10 Trib11 1 = Tributary has alarm. 9 Trib10 1 = Tributary has alarm. 8 Trib9 1 = Tributary has alarm. 7 Trib8 1 = Tributary has alarm. 6 Trib7 1 ...
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LXT6251A — SDH Mapper Bit Name This alarm indicates the REI counter has overflowed. The counter will rollover to 4 ReiOvrFlw 0 and continue counting. This alarm indicates the V5 RDI bit was set to ‘1’ for five ...
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Bit Name 1 = Enable 3 RdiIntEn 0 = Disable 1 = Enable 2 RfiIntEn 0 = Disable 1 = Enable 1 SlmIntEn 0 = Disable 1 = Enable 0 UnEqIntEn 0 = Disable 8.6 Status and Control Registers 8.6.1 ...
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LXT6251A — SDH Mapper This counter increments each time a BIP error event in the Low Order Path section is detected. To access the count, the microprocessor must provide a Write command to the MSB address bit of ...
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Bit Name 7:6 BIP2 V5 BIP-2 bits 5 REI V5 REI bit 4 RFI V5 RFI bit 3:1 SigLabel V5 Signal Label bits 0 RDI V5 RDI bit Datasheet 21 E1 SDH Mapper — LXT6251A Description Type Default RO X ...
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LXT6251A — SDH Mapper 9.0 Testability Modes The LXT6251A 21E1 Mapper/Demapper provides a method for enhancing testability: IEEE1149.1 Boundary Scan (JTAG) is used for testing of the interconnect. 9.1 IEEE 1149.1 Boundary Scan Description The boundary scan circuitry ...
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Figure 20. Test Access Port JTDI JTMS JTCK JTRS 9.1.1 Instruction Register and Definitions The LXT6251A supports the following instructions IEEE1149.1: EXTEST, SAMPLE/PRELOAD, BYPASS and IDCODE. Instructions are shifted into the instruction register during the SHIFT-IR state, and become active ...
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LXT6251A — SDH Mapper 4. The results are shifted out and next test stimuli shifted into the BSR. 9.1.1.2 SAMPLE/PRELOAD (‘b01) This instruction allows a snapshot of the normal operation of the LXT6251A. The boundary scan register is ...
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Figure 22. Boundary Scan Cells Data in Scan in Shift dr Clock dr Data in Scan in Shift dr Clock dr Update dr Mode Datasheet 21 E1 SDH Mapper — LXT6251A Data out Scan out Type 1 Type 2 Scan ...
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LXT6251A — SDH Mapper Table 19. JTAG Scan Chain PIN Name Type OEN Data OEN_c Enable SCANEN Data DtbDATA<7> Data DtbDATA<6> Data DtbDATA<5> Data DtbDATA<4> Data DtbDATA<3> Data DtbDATA<2> Data DtbDATA<1> Data DtbDATA<0> Data DtbPAR Data DtbYck Clock ...
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Table 19. JTAG Scan Chain (Continued) PIN Name Type MtbDATA<6> Data MtbDATA<7> Data MtbDATA_c Enable MtbDOE Data DATA/I<7> Data DATA/O<7> Data DATA/I<6> Data DATA/O<6> Data DATA/I<5> Data DATA/O<5> Data DATA/I<4> Data DATA/O<4> Data DATA/I<3> Data DATA/O<3> Data DATA/I<2> Data DATA/O<2> ...
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LXT6251A — SDH Mapper Table 19. JTAG Scan Chain (Continued) PIN Name Type RST Data MRAPDATA Data MRAPCLK Data MRAPFRM Data DSAPFRM Data DSAPCLK Data DSAPDATA Data DTC0 Data DTD0 Data MTD0 Data MTC0 Data MTC1 Data MTD1 ...
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Table 19. JTAG Scan Chain (Continued) PIN Name Type DTD7 Data DTC7 Data DTC8 Data DTD8 Data MTD8 Data MTC8 Data MTC9 Data MTD9 Data DTD9 Data DTC9 Data DTC10 Data DTD10 Data MTD10 Data MTC10 Data MTC11 Data MTD11 ...
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LXT6251A — SDH Mapper Table 19. JTAG Scan Chain (Continued) PIN Name Type MTC16 Data MTC17 Data MTD17 Data DTD17 Data DTC17 Data DTC18 Data DTD18 Data MTD18 Data MTC18 Data MTC19 Data MTD19 Data DTD19 Data DTC19 ...
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Package Specification Datasheet 21 E1 SDH Mapper — LXT6251A • Part Number LXT6251A • 208-pin Plastic Quad Flat Pack • Extended Temperature Range 0 (-40, + ...
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LXT6251A — SDH Mapper 11.0 Glossary AIS Alarm Indication Signal AUG Administrative Unit Group RDI Remote Defect Indication REI Remote Error Indication RFI Remote Fail Indication FIFO First in/First Out Memory MSOH Multiplexer Section Overhead NRZ Non-Return to ...