S2002TB AMCC (Applied Micro Circuits Corp), S2002TB Datasheet
S2002TB
Related parts for S2002TB
S2002TB Summary of contents
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DEVICE SPECIFICATION DUAL SERIAL BACKPLANE DEVICE DUAL SERIAL BACKPLANE DEVICE FEATURES • Broad operating rate range (.98 - 1.3 GHz) - 1062 MHz (Fibre Channel) - 1250 MHz (Gigabit Ethernet) line rates - 1/2 Rate Operation • Dual Transmitter with ...
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S2002 Figure 2. Typical Backplane Application ATM MAC Fibre (ASIC) Channel S2002 Ethernet MAC Etc. (ASIC) ATM MAC Fibre (ASIC) Channel S2002 Ethernet MAC Etc. (ASIC) 2 DUAL SERIAL BACKPLANE DEVICE Crosspoint Switch S2016 S2025 BACKPLANE SIGNAL GROUP MAC ATM ...
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DUAL SERIAL BACKPLANE DEVICE Figure 3. S2002 Input/Output Diagram RESET RATE REFCLK CLKSEL TMODE TCLKO SYNC DINA[0:7] 10 DNA, KGENA TCLKA DINB[0:7] 10 DNB, KGENB TCLKB ERRA DOUTA[0:7] 10 EOFA, KFLAGA RCA P/N ERRB DOUTB[0:7] 10 EOFB, KFLAGB RCB P/N ...
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S2002 Figure 4. Transmitter Block Diagram RATE REFCLK CLKSEL TMODE 8 DINA[0:7] FIFO SYNC (input) DNA KGENA 0 1 TCLKA 8 DINB0:7] FIFO (input) DNB KGENB 0 1 TCLKB 4 DUAL SERIAL BACKPLANE DEVICE DIN PLL 10x/20x TMODE 8 10 ...
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DUAL SERIAL BACKPLANE DEVICE Figure 5. Receiver Block Diagram RATE CMODE REFCLK EOFA KFLAGA FIFO (output) ERRA 8 Q DOUTA[0:7] 2 RCAP/N EOFB KFLAGB FIFO (output) ERRB 8 DOUTB[0:7] 2 RCBP/N October 9, 2000 / Revision B TMODE 8B/10B Decode ...
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S2002 TRANSMITTER DESCRIPTION The transmitter section of the S2002 contains a single PLL which is used to generate the serial rate transmit clock for all transmitters. Two channels are provided with a variety of options regarding input clocking and loopback. ...
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DUAL SERIAL BACKPLANE DEVICE The S2002 also supports the traditional REFCLK (TBC) clocking found in many Fibre Channel and Gigabit Ethernet applications and is illustrated in Fig- ure 7. Half Rate Operation The S2002 supports full and 1/2 rate operation ...
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S2002 In order to provide interface compatibility to non- AMCC serial backplane transceivers, the S2002 can also generate a unique sync character consisting of 16 consecutive K28.5 characters. This event is initi- ated by the simultaneous assertion of SYNC and ...
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DUAL SERIAL BACKPLANE DEVICE Table 3. K Character Generation (DNx = 1 KGENx =1 SYNC = ...
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S2002 RECEIVER DESCRIPTION Each receiver channel is designed to implement a Serial Backplane receiver function through the physi- cal layer. A block diagram showing the basic func- tion is provided in Figure 5. Whenever a signal is present, the receiver ...
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DUAL SERIAL BACKPLANE DEVICE Table 7. Error and Status Reporting ...
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S2002 8B/10B Decoding After serial to parallel conversion, the S2002 pro- vides 8B/10B decoding of the data. The received 10- bit codeword is decoded to recover the original 8-bit data. The decoder also checks for errors and flags, either invalid ...
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DUAL SERIAL BACKPLANE DEVICE OTHER OPERATING MODES Operating Frequency Range The S2002 is designed to operate at serial baud rates of .98 GHz to 1.3 GHz (800 Mbps to 1040 Mbps user data rate). The part is specified at Fibre ...
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S2002 JTAG TESTING The JTAG implementation for the S2002 is compli- ant with the IEEE1149.1 requirements. JTAG is used to test the connectivity of the pins on the chip. The TAP, (Test Access Port), provides access to the test logic ...
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DUAL SERIAL BACKPLANE DEVICE Table 9. JTAG Pin Assignments ...
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S2002 Table 10. Transmitter Input Pin Assignment and Descriptions ...
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DUAL SERIAL BACKPLANE DEVICE Table 11. Transmitter Output Signals ...
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S2002 Table 13. Receiver Output Pin Assignment and Descriptions ...
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DUAL SERIAL BACKPLANE DEVICE Table 14. Receiver Input Pin Assignment and Descriptions ...
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S2002 Table 16. Power and Ground Signals (Continued ...
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DUAL SERIAL BACKPLANE DEVICE Table 17. JTAG Test Signals ...
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S2002 Figure 10. S2002 Pinout (Bottom View ...
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DUAL SERIAL BACKPLANE DEVICE Figure 11. S2002 Pinout (Top View ...
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S2002 Figure 12. Compact 21mm x 21mm 156 TBGA Package Thermal Management DUAL SERIAL BACKPLANE DEVICE ...
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DUAL SERIAL BACKPLANE DEVICE Figure 13. Transmitter Timing (REFCLK Mode, TMODE = 0) REFCLK DINx[0:7], DNx, KGENx, SYNC SERIAL DATA OUT Table 18. S2002 Transmitter Timing (REFCLK Mode, TMODE = ...
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S2002 Table 20. S2002 Receiver Timing (Full and Half Clock Mode ...
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DUAL SERIAL BACKPLANE DEVICE Figure 15. Receiver Timing (Full Clock Mode, CMODE = 1) SERIAL DATA IN RCxN RCxP DOUTx[0:7], EOFx, KFLAGx, ERRx Figure 16. Receiver Timing (Half Clock Mode, CMODE = 0, TMODE = 1) SERIAL DATA IN RCxN ...
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S2002 Figure 18. TCLKO Timing REFCLK TCLKO Table 22. S2002 Transmitter (TCLKO Timing ...
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DUAL SERIAL BACKPLANE DEVICE Table 23. Absolute Maximum Ratings ...
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S2002 Table 26. Serial Data Timing, Transmit Outputs ...
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DUAL SERIAL BACKPLANE DEVICE OUTPUT LOAD The S2002 serial outputs do not require output pulldown resistors. ACQUISITION TIME With the input eye diagram shown in Figure 24, the S2002 will recover data with a 1E-9 BER within the time specified ...
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S2002 Figure 25. Loop Filter Capacitor Connections 32 DUAL SERIAL BACKPLANE DEVICE 270 CAP1 22 nf CAP2 270 S2002 October 9, 2000 / Revision B ...
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DUAL SERIAL BACKPLANE DEVICE Ordering Information Applied Micro Circuits Corporation • 6290 Sequence Dr., San ...