LAN91C100FDQFP Standard Microsystems, LAN91C100FDQFP Datasheet
LAN91C100FDQFP
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LAN91C100FDQFP Summary of contents
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FEAST Fast Ethernet Controller with Full Duplex Capability !" Dual Speed CSMA/CD Engine (10 Mbps and 100 Mbps) !" Compliant with IEEE 802.3 100BASE-T Specification !" Supports 100BASE-TX, 100BASE-T4, and 10BASE-T Physical Interfaces !" 32 Bit Wide Data Path (into ...
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... When the LAN91C100FD is configured for SWFDUP, its transmit and receive paths will operate independently and some CSMA/CD functions will be disabled. When the controller is not configured for SWFDUP it will follow the CSMA/CD protocol. LAN91C100FDQFP (208 Pin QFP Package) LAN91C100FDTQFP (208 Pin TQFP Package) © STANDARD MICROSYSTEMS CORPORATION (SMSC) 2000 ...
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FEATURES ................................................................................................................................................................... 1 GENERAL DESCRIPTION............................................................................................................................................ 1 PIN CONFIGURATION ................................................................................................................................................. 4 DESCRIPTION OF PIN FUNCTIONS ........................................................................................................................... 5 FUNCTIONAL DESCRIPTION.................................................................................................................................... 12 DATA STRUCTURES AND REGISTERS................................................................................................................... 16 BOARD SETUP INFORMATION ................................................................................................................................ 46 APPLICATION CONSIDERATIONS ........................................................................................................................... 48 OPERATIONAL DESCRIPTION ................................................................................................................................. 56 MAXIMUM GUARANTEED RATINGS* ...
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LNK 1 TXEN 2 XTAL1 3 XTAL2 4 VDD 5 MIISEL 6 nCSOUT 7 nRXDISC 8 TX25 9 VDD 10 RX_ER 11 RX_DV 12 IOS0 13 GND 14 IOS1 15 IOS2 16 RX25 17 LAN91C100FD COL100 18 CRS100 19 RXD0 ...
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PQFP/TQFP PIN NO. NAME SYMBOL 148-159 Address A4-A15 145-147 Address A1-A3 193 Address AEN Enable 160-163 nByte nBE0- Enable nBE3 173-170, Data Bus D0-D31 168-166, 164, 144, 142-139, 137-135, 133, 131-129, 127, 126, 124, 123, 121, 118, 117, 115-112, 110 ...
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PQFP/TQFP PIN NO. NAME SYMBOL 106 nSynchron nSRDY - ous Ready 109 nReady nRDYRTN Return 176, Interrupt INTR0- 187-189 INTR3 108 nLocal nLDEV Device 177 nRead nRD Strobe 178 nWrite nWR Strobe 190 nData nDATACS Path Chip Select 54 EEPROM ...
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PQFP/TQFP PIN NO. NAME SYMBOL 59, 56, RAM Data RD8-RD31 49-47, Bus 45-43, 69-67, 65, 64, 62-60, 81-76, 71, 70 84, 87, 88, RAM RA2-RA16 90, 91, 96, Address 99, 101, 100, Bus 98, 89, 92, 103, 102, 104 97 ...
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PQFP/TQFP PIN NO. NAME SYMBOL 206 Receive RXD Data 197 Transmit TXC Clock 199 Receive RXC Clock 202 Loopback LBK 1 nLink nLNK Status 195 nFullstep nFSTEP 6 MII Select MIISEL 194 AUI Select AUISEL 30 Transmit TXEN100 Enable 100 ...
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PQFP/TQFP PIN NO. NAME SYMBOL 192 Manage- MCLK ment Clock 11 Receive RX_ER Error 7 nChip nCSOUT Select Output 8 nReceive nRXDISC Packet Discard 37 RDMAH O4 Output buffer with 2mA source and 4mA sink O12 Output buffer with 6mA ...
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Table 1 - LAN91C100FD Pin Requirements FUNCTION System Address Bus System Data Bus System Control Bus Serial EEPROM RAM Data Bus RAM Address Bus RAM Control Bus Crystal Oscillator Power Ground External ENDEC 10 Mbps Physical Interface 100 Mbps Clocks ...
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SYSTEM BUS ADDRESS ADDRESS CONTROL CONTROL LAN91C100FD DATA DATA RA FIGURE 2 - LAN91C100FD SYSTEM DIAGRAM SMSC DS – LAN91C100FD REV. B SERIAL EEPROM 1O Mbps FEAST MII OE,WE RD0-31 OR SRAM 3 4 32kx8 2 1 Page 11 LAN83C69 ...
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DESCRIPTION OF BLOCKS Clock Generator Block 1) The XTAL1 and XTAL2 pins are to be connected MHz crystal. 2) TXCLK and RXCLK are 10 MHz clock inputs. These clocks are generated by the external ENDEC in 10 ...
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MMU BlockMMU The Hardware Memory Management Unit allocates memory and transmit and receive packet queues. It also determines the value of the transmit and receive interrupts as a function of the queues. The page size is 2k, with a maximum ...
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In 100 Mbps mode, the LAN91C100FD provides the following interface signals to the PHY: !"For transmission: TXEN100 TXD0-3 TX25 !"For reception: RX_DV RX_ER RXD0-3 RX25 !"For CSMA/CD state machines: CRS100 COL100 A transmission begins by TXEN100 going active (high), and ...
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EEPROM EEPROM INTERFACE DATA BUS ADDRESS BUS BUS INTERFACE CONTROL WRITE READ DATA DATA REG REG FIGURE 3 - LAN91C100FD INTERNAL BLOCK DIAGRAM WITH DATA PATH SMSC DS – LAN91C100FD REV FIFO CSMA/CD DMA FIFO TX COMPL ...
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DATA STRUCTURES AND REGISTERS PACKET FORMAT IN BUFFER MEMORY The packet format in memory is similar for the Transmit and Receive areas. The first word is reserved for the status word. The next word is used to specify the total ...
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The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C100FD treated transparently as data both for transmit and receive operations. CONTROL BYTE - For transmit packets the CONTROL BYTE is written by the ...
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HASH VALUE - Provides the hash value used to index the Multicast Registers. Can be used by receive routines to speed up the group address search. The hash value consists of the six most significant bits of the CRC calculated ...
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BANK SELECT REGISTER OFFSET NAME E BANK SELECT REGISTER HIGH 0 0 BYTE 0 0 LOW BYTE X X BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to select the register ...
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STP_SQET - Stop transmission on SQET error. If set, stops and disables transmitter on SQE test error. Does not stop on SQET error and transmits next frame if clear. Defaults low. FDUPLX - When set it enables Full Duplex operation. ...
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CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15). Cleared by reading the ECR register. EXC_DEF - Excessive Deferral. When set last/ current transmit was deferred for more than 1518 * ...
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BANK 0 OFFSET 4 RECEIVE CONTROL REGISTER HIGH SOFT FILT BYTE RST CAR 0 0 LOW Reserved Reserved BYTE 0 0 SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. ...
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BANK 0 OFFSET 6 COUNTER REGISTER Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared when reading the register and do not wrap around beyond 15. HIGH NUMBER OF EXC. ...
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BANK 0 OFFSET A MEMORY CONFIGURATION HIGH BYTE 0 0 LOW MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M) BYTE 0 0 MEMORY RESERVED FOR TRANSMIT - Programming this value allows the host CPU to reserve memory to ...
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FULL STEP - This bit is a general purpose output port. Its inverse value drives pin nFSTEP and it is typically connected to SEL pin of the LAN83C694. It can be used to select the signaling mode for the AUI ...
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BANK 1 OFFSET 4 THROUGH 9 INDIVIDUAL ADDRESS REGISTERS These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload. The registers can be modified by the software driver, but a STORE operation ...
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BANK 1 OFFSET C CONTROL REGISTER HIGH RCV_ 0 BYTE BAD 0 0 LOW LE CR BYTE ENABLE ENABLE 0 0 RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate interrupts and ...
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BANK2 OFFSET 0 MMU COMMAND REGISTER This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three command bits determine the command issued as described below: HIGH BYTE LOW COMMAND ...
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Note 2: When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO ports register before issuing ...
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BANK 2 OFFSET 4 FIFO PORTS REGISTER This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from this register. ...
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Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than the last pre- fetched). This allows any interrupt routine that uses the pointer, to save it and restore it without affecting the ...
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OFFSET C INTERRUPT ACKNOWLEDGE RX_DISC ERCV INT INT OFFSET D INTERRUPT MASK REGISTER RX_DISC ERCV INT EPH INT INT 0 0 This register can be read and written as a word or as two individual bytes. The Interrupt Mask Register ...
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The TX EMPTY INT ENABLE should only be set after the following steps packet is enqueued for transmission b) the previous empty condition is cleared (acknowledged) TX INT - Set when at least one packet transmission was completed. ...
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BANK3 OFFSET 0 THROUGH 7 MULTICAST TABLE LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 The ...
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BANK 3 OFFSET 8 MANAGEMENT INTERFACE HIGH MSK_ FLTST BYTE CRS100 0 0 LOW BYTE 0 0 FLTST - Facilitates the inclusion of packet forwarding information on the receive packet memory structure. When 0, RD0-RD7 is always driven. When 1, ...
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PIN COUNTER - 8-bit counter increments when a packet is discarded due to the nRXDISC pin being active. This counter will be reset to 00 when read. A count of FF will set the RX_DISC INT. The count will ...
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TYPICAL FLOW OF EVENTS FOR TRANSMIT S/W DRIVER 1 ISSUE ALLOCATE MEMORY FOR BYTES - the MMU attempts to allocate N bytes of RAM. 2 WAIT FOR SUCCESSFUL CODE - Poll until the ALLOC INT bit is ...
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TYPICAL FLOW OF EVENTS FOR RECEIVE S/W DRIVER 1 ENABLE RECEPTION - By setting the RXEN bit SERVICE INTERRUPT - Read the Interrupt Status Register and determine if RCV INT is set. The next receive packet ...
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Call TX INTR or TXEMPTY INTR Get Next TX Packet Available for Transmission? Yes Call ALLOCATE Yes Call EPH INTR FIGURE 6 - INTERRUPT SERVICE ROUTINE SMSC DS – LAN91C100FD REV. B ISR Save Bank Select & Address Ptr Registers ...
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SMSC DS – LAN91C100FD REV INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM No Yes Destination Multicast? Read Words from RAM for Address Filtering Address No Yes Filtering Pass? No Yes Status ...
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SMSC DS – LAN91C100FD REV INTR Save Pkt Number Register Read TXDONE Pkt # from FIFO Ports Reg. Write Into Packet Number Register Write Address Pointer Register Read Status Word from RAM Yes No TX Status OK? Immediately ...
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TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) FIGURE 9 - TXEMPTY INTR (ASSUMES AUTO RELEASE OPTION SELECTED) SMSC DS – LAN91C100FD REV. B TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR ...
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DRIVER SEND Choose Bank Select Register 2 Call ALLOCATE Exit Driver Send Write Allocated Packet into Write Address Pointer Register Copy Part of TX Data Packet Set "Ready for Packet" Flag Return Buffers to Upper Layer FIGURE 10 - DRIVE ...
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MEMORY PARTITIONING Unlike other controllers, the LAN91C100FD does not require a fixed memory partitioning between transmit and receive resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the CPU to prevent the receive process from ...
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One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1. TX EMPTY INT is generated only after transmitting the last packet in the FIFO. TX INT will be set on a fatal transmit ...
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The following parameters are obtained from the EEPROM as board setup information: !" ETHERNET INDIVIDUAL ADDRESS !" I/O BASE ADDRESS !" 10BASET or AUI INTERFACE !" MII or ENDEC INTERFACE !" INTERRUPT LINE SELECTION All the above mentioned values are ...
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RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the value until read low is used to determine completion. When an EEPROM access is in progress the STORE and RELOAD bits of CTR ...
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The LAN91C100FD is envisioned to fit a few different bus types. This section describes the basic guidelines, system level implications and sample configurations for the most relevant bus types. All applications are based on buffered architectures with a private SRAM ...
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Table Local Bus Signal Connections VL BUS LAN91C100 SIGNAL SIGNAL nADS nADS, nCYCLE IRQn INTR0-INTR3 D0-D31 D0-D31 nLDEV nLDEV VCC nRD nWR GND A1 nVLBUS OPEN nDATACS SMSC DS – LAN91C100FD REV. B NOTES Address Strobe is ...
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VL BUS W/nR A2-A15 LCLK M/nIO nRESET IRQn D0-D31 nRDYRTN nBE0-nBE3 nADS delay 1 LCLK nLRDY nLDEV SMSC DS – LAN91C100FD REV. B W/nR A2-A15 LCLK AEN RESET LAN91C100FD INTR0-INTR3 D0-D31 nRDYRTN nBE0-nBE3 nADS nCYCLE nSRDY O.C. simulated O.C. FIGURE ...
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HIGH-END ISA OR NON-BURST EISA MACHINES On ISA machines, the LAN91C100FD is accessed bit peripheral. No support for XT (8 bit peripheral) is provided. The signal connections are listed in the following table: Table 4 - High-End ...
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ISA BUS A1-A15, AEN RESET VCC D0-D15 nIRQ nIORD nIOWR A0 nSBHE nIOCS16 SMSC DS – LAN91C100FD REV. B A1-A15, AEN RESET nBE2, nBE3 D0-D15 LAN91C100FD INTR0-INTR3 nRD nWR nBE0 nBE1 nLDEV O.C. FIGURE 14 - LAN91C100FD ON ISA BUS ...
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EISA 32 BIT SLAVEEISA 32 bit slave On EISA the LAN91C100FD is accessed bit I/O slave, along with a Slave DMA type "C" data path option I/O slave, the LAN91C100FD uses asynchronous accesses. In creating ...
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Table 5 - EISA 32 Bit Slave Signal Connections EISA BUS LAN91C100FD SIGNAL SIGNAL nEX32 nLDEV nNOWS (optional additional logic) THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES BCLK LCLK nDAK<n> nDATACS nIORC W/nR nIOWC nCYCLE nEXRDY nRDYRTN ...
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EISA BUS LA2-LA15 RESDRV AEN M/nIO D0-D31 IRQn nBE0-nBE3 nCMD LATCH + gates nWR BCLK nSTART nEX32 O.C. FIGURE 15 - LAN91C100FD ON EISA BUS SMSC DS – LAN91C100FD REV. B A2-A15 RESET AEN D0-D31 INTR0-INTR3 LAN91C100FD nBE0-nBE3 nRD nWR ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ................................................................................................................ +70EC Storage Temperature Range ............................................................................................................. -55EC"to + 150EC Lead Temperature Range (soldering, 10 seconds) ............................................................................................+325EC Positive Voltage on any pin, with respect to Ground ..................................................................................... V Negative Voltage ...
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PARAMETER SYMBOL O4 Type Buffer Low Output Level High Output Level Output Leakage I/O4 Type Buffer Low Output Level High Output Level Output Leakage O12 Type Buffer Low Output Level High Output Level Output Leakage O16 Type Buffer Low Output ...
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CAPACITANCE T = 25EC 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance CAPACITIVE LOAD ON OUTPUTS nARDY, D0-D31 (non VLBUS) D0-D31 in VLBUS All other outputs SMSC DS – LAN91C100FD REV ...
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ADDRESS nADS READ DATA t1 nRD,nWR WRITE DATA FIGURE 16 - ASYNCHRONOUS CYCLE - nADS=0 PARAMETER t1 A1-A15, AEN, nBE0-nBE3 Valid and nADS Low Setup to nRD, nWR Active t2 A1-A15, AEN, nBE0-nBE3 Hold After nRD, nWR Inactive (Assuming nADS ...
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READ DATA t1 nRD, nWR WRITE DATA FIGURE 18 - ASYNCHRONOUS CYCLE - nADS=0 (nDATACS Used to Select Data Register; Must Be 32 Bit Access) PARAMETER t1 A1-A15, AEN, nBE0-nBE3 Valid and nADS Low Setup to nRD, nWR ...
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LCLK nDATACS W/nR nCYCLE WRITE DATA nRDYRTN FIGURE 19 - BURST WRITE CYCLES - nVLBUS=1 t12 nDATACS Setup to Either nCYCLE or W/nR Falling t13 nDATACS Hold after Either nCYCLE or W/nR Rising t14 nRDYRTN Setup to LCLK Falling t15 ...
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ADDRESS nLDEV FIGURE 21 - ADDRESS LATCHING FOR ALL MODES PARAMETER t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE3 Hold After nADS Rising t25 A4-A15, AEN to nLDEV Delay LCLK W/nR ADDRESS nADS nCYCLE WRITE ...
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LCLK W/nR ADDRES nADS nCYCL READ nSRD RDYRT nDATAC FIGURE 23 - SYNCHRONOUS READ CYCLE - nVLBUS=0 PARAMETER t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE3 Hold After nADS Rising t10 nCYCLE Setup to LCLK Rising ...
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RA2-RA16 nRWE0-nRWE3 nROE RD0-RD31 WRITE CYCLE t38 RA2-RA16 nRWE0-nRWE3 nROE RD0-RD31 t38 RA2-RA16 nRWE0-nRWE3 nROE RD0-RD31 PARAMETER t34 Write – RA2-RA16 Setup to nRWE0-nRWE3 Falling t35 Write – RA2-RA16 Hold after nRWE0-nRWE3 Rising t36 Write – RD0-RD31 Setup to ...
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TXC t30 TXEN t30 TXD RXD RXC CRS FIGURE 25 - ENDEC INTERFACE - 10 MBPS PARAMETER t30 TXD, TXEN Delay from TXC Rising t31 RXD Setup to RXC Rising t32 RXD Hold After RXC Rising Notes: 1. CRS input ...
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DETAIL ' 0. Notes: 1 Coplanarity is 0.100mm maximum. 2 Tolerance on the position of the leads is 0.08mm maximum. 3 Package body dimensions D1 and E1 do not ...
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DIM MIN A A1 0.05 A2 1.35 D 29.80 D/2 14.90 D1 27.90 E 29.80 E/2 14.90 E1 27.90 H 0. 0.50 BSC 0.17 R1 0.08 R2 0.08 ccc ccc Notes: 1 Controlling ...
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LAN91C100FD REV. B REVISIONS SECTION/FIGURE/ENTRY PAGE(S) 5 Description of Pin Functions 20 Table under Bank Electrical and Timing Section SMSC DS – LAN91C100FD REV. B CORRECTION Pin 175 – Changed to active high signal. Changed RX_OVRN to ...