GCIXP1200FB Intel Corporation, GCIXP1200FB Datasheet
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Intel IXP1200 Network Processor Product Features ® The Intel IXP1200 Network Processor delivers high-performance processing power and flexibility to a wide variety of LAN and telecommunications products. Distinguishing features of the IXP1200 are the performance of ASIC hardware along ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2001 Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries *Other names and brands may be claimed as the property of others. ii ...
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Contents 1.0 Product Description ............................................................................................................ 9 2.0 Introduction.......................................................................................................................11 3.0 Related Documents..........................................................................................................11 4.0 Conventions .....................................................................................................................11 5.0 Functional Units................................................................................................................12 5.1 StrongARM* Core................................................................................................12 5.2 Microengines .......................................................................................................12 5.3 FBI Unit and the IX Bus.......................................................................................12 5.3.1 IX Bus Access Behavior .........................................................................13 5.3.1.1 Reset and Idle ...
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Intel IXP1200 Network Processor 6.6 IX Bus Pins Function Listed by Operating Mode................................................. 52 6.7 IX Bus Decode Table Listed by Operating Mode Type ....................................... 62 6.8 Pin State During Reset........................................................................................ 64 6.9 Pullup/Pulldown and Unused Pin Guidelines ...................................................... ...
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Reset Logic .........................................................................................................23 6 Pinout Diagram....................................................................................................25 7 64-Bit Bidirectional IX Bus, 1-2 MAC Mode.........................................................52 8 64-Bit Bidirectional IX Bus, 1-2 MAC Mode, FastPort Device .............................53 9 64-Bit Bidirectional IX Bus, 3+ MAC Mode..........................................................55 10 32-Bit Unidirectional IX Bus, 1-2 ...
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Intel IXP1200 Network Processor 41 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 14th Data Return with Status .................................................................................... 103 42 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 1st Through 13th Data Return with ...
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SRAM SlowPort Write .......................................................................................132 73 SRAM SlowPort RDY# ......................................................................................133 74 Pipelined SRAM Two Longword Burst Read Followed By SlowPort Write .......134 75 SDCLK AC Timing Diagram ..............................................................................135 76 SDRAM Bus Signal Timing ...............................................................................136 77 SDRAM Initialization Sequence ........................................................................139 78 ...
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Intel IXP1200 Network Processor 34 I1, I3, O1, O3, O4, and O5 Pin Types ................................................................. and O2 Pin Types ........................................................................................... 71 36 Overshoot/Undershoot Specifications................................................................. 71 37 PXTAL Clock Inputs ............................................................................................ MHz PCI Clock ...
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Product Description ® The Intel IXP1200 Network Processor is a highly integrated, hybrid data processor that delivers high-performance parallel processing power and flexibility to a wide variety of networking, communications, and other data-intensive products. The IXP1200 is designed specifically ...
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Intel IXP1200 Network Processor As shown in Figure • The IXP1200 interfaces to a maximum of 256 Mbytes of SDRAM over a 64-bit data bus. • A separate 32-bit SRAM bus supports Mbytes of SSRAM and ...
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Introduction Intel has created a new architecture, the IXP1200 Network Processor, to address the requirements of today’s network equipment designers. The network processor is a fully programmable device which has been specifically designed to handle the high speed data ...
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Intel IXP1200 Network Processor 5.0 Functional Units 5.1 StrongARM* Core The StrongARM* core is the same industry standard 32-bit RISC processor as used in the Intel * StrongARM SA-1100 compatible with the StrongARM* processor family currently used ...
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The IX Bus provides a 4.4 Gbps interface to peripheral devices. The IX Bus was specifically designed to provide a simple and efficient interface. The IX Bus can be configured as either a 64-bit bidirectional bus or as two 32-bit ...
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Intel IXP1200 Network Processor care” for these trailing bus cycles, except in the case of a status transfer where the IX Bus burst includes a possible status transfer if the device were programmed to support it. Slave devices must ...
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In both 32-bit and 64-bit modes, all of the associated FBE# signals (FBE#[7:4] in 32-bit mode and FBE#[7:0] for 64-bit mode) are driven low on a transmit. The last bus transfer, identified by the assertion of EOP/EOP_RX in 64-bit mode ...
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Intel IXP1200 Network Processor 5.4.1 SDRAM Unit The IXP1200 provides an SDRAM Unit to access low cost, high bandwidth memory for mass data storage. The StrongARM* core address space allows up to 256 Mbytes of SDRAM to be addressed. ...
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IXP1200 then updates only the bytes that were enabled and writes the entire quadword of data back to SDRAM memory. (Note that the bytes do not have to be consecutive.) These three steps are performed automatically. 5.4.2 SDRAM Bus Access ...
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Intel IXP1200 Network Processor 5.4.4 SRAM Unit The IXP1200 provides an SRAM Unit for very high bandwidth memory for storage of lookup tables and other data for the packet processing Microengines. The SRAM Unit controls the SRAM (up to ...
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DQ data signals will skew the SCLKIN slightly to track the return data trace propagation delay. When using Pipelined/DCD SRAMs, the SCLKIN input is not used and may be held inactive with a pulldown to GND ...
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Intel IXP1200 Network Processor 5.4.4.2 SRAM Configurations Table 6. SRAM Configurations Total Memory 1 Mbytes 2 Mbytes 2 Mbytes 4 Mbytes 4 Mbytes 8 Mbytes (maximum) 5.4.4.3 BootROM Configurations Table 7. BootROM x32 Sample Configurations Total Memory 512 Kbytes ...
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Accesses from the StrongARM* core: — Byte, word, and longword accesses generated from the StrongARM* core are supported. — Bit operations are supported via StrongARM* core accesses to the SRAM Alias Address Space to perform the same operations as ...
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Intel IXP1200 Network Processor 5.5.1 PCI Arbitration and Central Function Support The IXP1200 contains an optional arbiter to support up to three PCI Bus masters. This includes the IXP1200 plus two external PCI Bus master devices. The external masters ...
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Output Pin RESET_OUT# ext_rst Soft reset timer rst_in_sync start !zero 140 cycle counter Core clock [31] [30] [29] [28:19] [18] [17] cmd SA PCI sram sdram res arb Core reset reset reset reset reset reset Internal Reset Signals strongarm_rst pci_rst ...
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Intel IXP1200 Network Processor 5.6.1 Hardware Initiated Reset The IXP1200 provides the RESET_IN# pin so that an external device can reset the IXP1200. Asserting this pin resets the internal functions and generates an external reset via the RESET_OUT# pin. ...
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Signal Description 6.1 Pinout Diagram Figure 6. Pinout Diagram Processor Support Miscellaneous Test IEEE 1149.1 SRAM Interface LOW_EN#/DIRW# HIGH_EN#/RDY# SDRAM Interface Power Supply * StrongARM is a registered trademark of ARM Limited. Datasheet RESET_OUT# RESET_IN# PXTAL CINT# SCAN_EN TCK_BYP ...
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Intel IXP1200 Network Processor 6.2 Pin Type Legend The IXP1200 signals are categorized into one of several groups: Processor Support, Miscellaneous/Test, IEEE 1149.1, SRAM Interface, SDRAM Interface, IX Bus Interface, General Purpose, Serial Port, and PCI Interface. Table 10 ...
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Pin Description, Grouped by Function 6.3.1 Processor Support Pins Table 11. Processor Support Pins Processor Support Signal Names PXTAL CINT# RESET_OUT# RESET_IN# Totals: Datasheet Intel Pin # Type Total Input connection for system oscillator. Typically 3.6864 ...
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Intel IXP1200 Network Processor 6.3.2 SRAM Interface Pins Table 12. SRAM Interface Pins SRAM Interface Signal Names A[18:0] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] DQ[31:0] [31] ...
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Table 12. SRAM Interface Pins (Continued) SRAM Interface Signal Names CE#[3:0] [3] [2] [1] [0] SCLK SCLKIN SOE# SWE# SLOW_WE# LOW_EN#/DIRW# HIGH_EN#/RDY# SLOW_EN# SP_CE# SLOW_RD# Totals: Datasheet Pin # Type Total A26 SRAM Bus chip enable outputs. Internally decoded from ...
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Intel IXP1200 Network Processor 6.3.3 SDRAM Interface Pins Table 13. SDRAM Interface Pins SDRAM Interface Pin # Signal Names MADR[14:0] [14] AK5 [13] AD1 [12] AC3 [11] AC2 [10] AC1 [9] AB3 [8] AA4 [7] AB2 [6] AB1 [5] ...
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Table 13. SDRAM Interface Pins (Continued) SDRAM Interface Pin # Signal Names [25] L1 [24] L2 [23] M4 [22] L3 [21] K1 [20] K3 [19] J1 [18] J2 [17] J3 [16] H1 [15] H2 [14] J4 [13] H3 [12] G1 ...
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Intel IXP1200 Network Processor 6.3.4 IX Bus Interface Pins Table 14. IX Bus Interface Pins IX Bus Signal Pin # Names FCLK AB30 PORTCTL#[3:0] [3] AC30 [2] AC31 [1] AB29 [0] AA28 FPS[2:0] [2] AC29 [1] AD31 [0] AD30 ...
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Table 14. IX Bus Interface Pins (Continued) IX Bus Signal Pin # Names [30] AL23 [29] AJ22 [28] AH21 [27] AK22 [26] AL22 [25] AJ21 [24] AH20 [23] AK21 [22] AL21 [21] AJ20 [20] AH19 [19] AK20 [18] AL20 [17] ...
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Intel IXP1200 Network Processor Table 14. IX Bus Interface Pins (Continued) IX Bus Signal Pin # Names FAST_RX2 AJ10 RDYCTL#[4]/ FC_EN1#/ AK6 RXPEN# RDYCTL#[3:0] [3] AL6 [2] AJ7 [1] AH8 [0] AK7 RDYBUS[7:0] [7] AL9 [6] AK9 [5] AJ9 ...
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Table 14. IX Bus Interface Pins (Continued) IX Bus Signal Pin # Names EOP/EOP_RX AJ11 TK_REQ_OUT/ AJ6 SOP_TX TK_REQ_IN/ AL5 EOP_TX TK_OUT AA29 TK_IN AB31 Totals: Datasheet Intel Type Total End of Packet Indication. • Receive End of Packet Input ...
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Intel IXP1200 Network Processor 6.3.5 General Purpose I/Os Table 15. General Purpose I/Os General Purpose I/O Pin # Signal Names GPIO[3:1] [3] A25 [2] B25 [1] D24 GPIO[0]/ FC_EN0#/ C25 TXPEN Totals: 6.3.6 Serial Port (UART) Pins Table 16. ...
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PCI Interface Pins Table 17. PCI Interface Pins PCI Interface Pin # Signal Names AD[31:0] [31] B20 [30] A20 [29] C19 [28] C18 [27] B18 [26] D17 [25] C17 [24] A16 [23] D16 [22] A15 [21] B15 [20] C15 ...
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Intel IXP1200 Network Processor Table 17. PCI Interface Pins (Continued) PCI Interface Pin # Signal Names DEVSEL# D13 IDSEL C16 PERR# A11 SERR# B11 PCI_IRQ# A22 PCI_RST# C21 PCI_CLK D20 A24 PCI_CFN[1:0] C23 38 Type Total Device Select. Indicates ...
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Table 17. PCI Interface Pins (Continued) PCI Interface Pin # Signal Names GNT#[0] B21 REQ#[0] A21 GNT#[1] C20 REQ#[1] D19 Totals: Datasheet Intel Type Total PCI Bus Master Grant 1. Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): Pin is ...
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Intel IXP1200 Network Processor 6.3.8 Power Supply Pins Table 18. Power Supply Pins Supply Signal Pin # Names VDD A19, B19, B27, H31, J29, K2, L4, Y4, AA2, AA30, AA31, AC4, AD3, AD28, AE29, AG4, AG28 Total VDD pins ...
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IEEE 1149.1 Interface Pins Table 19. IEEE 1149.1 Interface Pins IEEE 1149.1 Interface Pin Pin # Name TCK A23 TMS C22 TDI B22 TDO D21 TRST# B23 Totals: 6.3.10 Miscellaneous Test Pins Table 20. Miscellaneous Test Pins Processor Support ...
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Intel IXP1200 Network Processor 6.3.11 Pin Usage Summary Table 21. Pin Usage Summary Type Inputs Outputs Bidirectional Total Signal Power Overall Totals: 42 Quantity 21 68 235 324 108 432 Datasheet ...
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Pin/Signal List Table 22. Pin Table in Pin Order Pin Signal Name Number A1 VDDX A2 VSS A3 VSS A4 VSSP1 A5 RESET_OUT# A6 AD[1] A7 AD[5] A8 AD[8] A9 AD[11] A10 AD[15] A11 PERR# A12 IRDY# A13 AD[16] ...
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Intel IXP1200 Network Processor Table 22. Pin Table in Pin Order (Continued) Pin Signal Name Number D10 VDDX D11 AD[13] D12 PAR D13 DEVSEL# D14 VDDX D15 AD[18] D16 AD[23] D17 AD[26] D18 VDDX D19 REQ#[1] D20 PCI_CLK D21 ...
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Table 22. Pin Table in Pin Order (Continued) Pin Signal Name Number T2 MDATA[38] T3 MDATA[39] T4 MDATA[40] T28 DQ[7] T29 DQ[6] T30 DQ[5] T31 DQ[4] U1 MDATA[41] U2 MDATA[42] U3 MDATA[43] U4 MDATA[45] U28 DQ[2] U29 DQ[3] U30 VSS ...
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Intel IXP1200 Network Processor Table 22. Pin Table in Pin Order (Continued) Pin Signal Name Number AH18 VDDX AH19 FDAT[20] AH20 FDAT[24] AH21 FDAT[28] AH22 VDDX AH23 FDAT[35] AH24 FDAT[39] AH25 VDDX AH26 FDAT[46] AH27 FDAT[50] AH28 VDDX AH29 ...
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Signals Listed in Alphabetical Order Table 23. Pin Table in Alphabetical Order Signal Name A[0] A[1] A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] AD[0] AD[1] AD[10] AD[11] AD[12] AD[13] ...
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Intel IXP1200 Network Processor Table 23. Pin Table in Alphabetical Order (Continued) Signal Name FBE#[4] FBE#[5] FBE#[6] FBE#[7] FCLK FDAT[0] FDAT[1] FDAT[10] FDAT[11] FDAT[12] FDAT[13] FDAT[14] FDAT[15] FDAT[16] FDAT[17] FDAT[18] FDAT[19] FDAT[2] FDAT[20] FDAT[21] FDAT[22] FDAT[23] FDAT[24] FDAT[25] FDAT[26] ...
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Table 23. Pin Table in Alphabetical Order (Continued) Signal Name MDATA[18] MDATA[19] MDATA[2] MDATA[20] MDATA[21] MDATA[22] MDATA[23] MDATA[24] MDATA[25] MDATA[26] MDATA[27] MDATA[28] MDATA[29] MDATA[3] MDATA[30] MDATA[31] MDATA[32] MDATA[33] MDATA[34] MDATA[35] MDATA[36] MDATA[37] MDATA[38] MDATA[39] MDATA[4] MDATA[40] MDATA[41] MDATA[42] MDATA[43] MDATA[44] ...
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Intel IXP1200 Network Processor Table 23. Pin Table in Alphabetical Order (Continued) Signal Name TRDY# TRST# TSTCLK TXASIS TXD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD_REF VDDP1 VDDX ...
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Table 23. Pin Table in Alphabetical Order (Continued) Signal Name VSS VSSP1 WE# Datasheet Intel Pin Pin Signal Name Number Number AL30 A4 W1 ® IXP1200 Network Processor Pin Signal Name Number 51 ...
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Intel IXP1200 Network Processor 6.6 IX Bus Pins Function Listed by Operating Mode Figure 7 through Figure 11 to one or more MAC devices and is accompanied by a pin description for the IX Bus in that mode. Figure ...
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Figure 8. 64-Bit Bidirectional IX Bus, 1-2 MAC Mode, FastPort Device ® Intel IXP1200 Processor GPIO[0]/FC_EN0#/TXPEN RDYCTL#[4]/FC_EN1#/RXPEN# TK_REQ_OUT#/SOP_TX TK_REQ_IN#/EOP_TX Datasheet 3.3V [7:2] CINT# GPIO[3:1] not used RDYBUS[7:0] [1] RDYCTL#[3:0] not used [0] FAST_RX1 [1] FAST_RX2 [0] PORTCTL#[3:0] [2] [0] FPS[2:0] ...
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Intel IXP1200 Network Processor Table 24. 64-Bit Bidirectional IX Bus, 1-2 MAC Mode Signal GPIO[3:1] GPIO[0]/FC_EN0#/ TXPEN RDYCTL#[3:0] RDYCTL#[4]/FC_EN1#/ RXPEN# RDYBUS[7:0] PORTCTL#[3:0] FPS[2:0] SOP/SOP_RX TK_REQ_OUT/ SOP_TX EOP/EOP_RX TK_REQ_IN/EOP_TX TK_IN TK_OUT RXFAIL TXASIS/TXERR FBE#[7:0] FDAT[63:0] FAST_RX1 FAST_RX2 54 Description Active ...
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Figure 9. 64-Bit Bidirectional IX Bus, 3+ MAC Mode ® Intel IXP1200 Processor GPIO[0]/FC_EN0#/TXPEN RDYCTL[4]/FC_EN1#/RXPEN# TK_REQ_OUT/SOP_TX TK_REQ_IN/EOP_TX Datasheet CINT# GPIO[3:1] not used not used RDYBUS[7:0] [31:0] RDYCTL#[3:0] 5 > 32 FCLK [15:0] 4 > 16 PORTCTL#[3:0] FCLK FPS[2:0] FDAT[63:0] FBE#[7:0] ...
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Intel IXP1200 Network Processor Table 25. 64-Bit Bidirectional IX Bus, 3+ MAC Mode (Shared IX Bus Operation Only in This Mode) Signal GPIO[3:1] GPIO[0]/FC_EN0#/ TXPEN RDYCTL#[4:0] RDYBUS[7:0] PORTCTL#[3:0] FPS[2:0] SOP/SOP_RX TK_REQ_OUT/ SOP_TX EOP/EOP_RX TK_REQ_IN/EOP_TX TK_IN TK_OUT RXFAIL TXASIS/TXERR 56 ...
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Table 25. 64-Bit Bidirectional IX Bus, 3+ MAC Mode (Shared IX Bus Operation Only in This Mode) (Continued) Signal FBE#[7:0] FDAT[63:0] FAST_RX1 FAST_RX2 Shared IX Bus Operation Signals These signals are driven by the IXP1200 IX Bus owner, and are ...
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Intel IXP1200 Network Processor Figure 10. 32-Bit Unidirectional IX Bus, 1-2 MAC Mode ® Intel IXP1200 Processor GPIO[0]/FC_EN0#/TXPEN RDYCTL[4]/FC_EN1#/RXPEN# Receive Transmit TK_REQ_OUT/SOP_TX TK_REQ_IN/EOP_TX 58 CINT# RDYBUS[7:0] [0] RDYCTL#[3:0] [1] [0] PORTCTL#[1:0] FDAT [31:0] FBE#[3:0] FPS[2:0] RxFAIL SOP/SOP_RX EOP/EOP_RX [2] ...
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Table 26. 32-Bit Unidirectional IX Bus, 1-2 MAC Mode Transmit Path Signals GPIO[3:1] PORTCTL#[3:2] TK_REQ_OUT/ SOP_TX TK_REQ_IN/EOP_TX TXASIS/TXERR FBE#[7:4] FDAT[63:31] Receive Path Signals FPS[2:0] PORTCTL#[1:0] SOP/SOP_RX EOP/EOP_RX RXFAIL FBE#[3:0] FDAT[31:0] Control Signals Common to both Transmit/Receive Paths GPIO[0]/FC_EN0#/ TXPEN RDYCTL#[4]/FC_EN1#/ ...
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Intel IXP1200 Network Processor Figure 11. 32-bit Unidirectional IX Bus, 3+ MAC Mode (3-4 MACs Supported) ® Intel IXP1200 Processor Receive RDYCTL#[4]/FC_EN1#/RXPEN# Transmit GPIO[0]/FC_EN0#/TXPEN TK_REQ_OUT/SOP_TX TK_REQ_IN/EOP_TX 60 CINT#[0] [15:0] 4 > 16 RDYCTL#[3:0] decoder FCLK RDYBUS[7:0] 2 > 4 ...
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Table 27. 32-bit Unidirectional IX Bus, 3+ MAC Mode Transmit Path Signals GPIO[3:1] PORTCTL#[3:2] GPIO[0]/FC_EN0#/TXPEN TK_REQ_OUT/SOP_TX TK_REQ_IN/EOP_TX TXASIS/TXERR FBE#[7:4] FDAT[63:31] Receive Path Signals FPS[2:0] PORTCTL#[1:0] RDYCTL#[4]/FC_EN1#/ RXPEN# SOP/SOP_RX EOP/EOP_RX RXFAIL FBE#[3:0] FDAT[31:0] Control Signals Common to both Transmit/Receive Paths RDYCTL#[3:0] ...
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Intel IXP1200 Network Processor 6.7 IX Bus Decode Table Listed by Operating Mode Type Table 28. IX Bus Decode Table Listed by Operating Mode Type PIN NAME Bidirectional 1-2 1110 MAC0 RxSEL 1101 MAC1 RxSEL PORTCTL#[3:0] 1011 MAC0 TxSEL ...
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Table 28. IX Bus Decode Table Listed by Operating Mode Type (Continued) PIN NAME Bidirectional 1-2 EOP/EOP_TX Not used RDYCTL#[4]/ MAC1 Flw Ctl FC_EN1#/ enable when low RXPEN# x1111 NOP x1110 MAC0 Rx RDYCTL#[4:0] x1101 MAC0 Tx x1011 MAC1 Rx ...
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Intel IXP1200 Network Processor 6.8 Pin State During Reset Table 29 summarizes IXP1200 pin states during reset. Table 29. Pin State During Reset Function SRAM SCLK SRAM A[17:0] SRAM DQ[31:0] SRAM CE#[3:0] SRAM SLOW_EN# SRAM SOE# SRAM SWE# SRAM ...
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Table 29. Pin State During Reset (Continued) Function PCI PCI_CFN[1] PCI PCI_IRQ# PCI PCI_RST# PCI PERR# PCI SERR# PCI STOP# PCI DEVSEL# PCI TRDY# PCI GNT#[1:0] PCI REQ#[1:0] IX Bus FCLK IX Bus FDAT[63:0] IX Bus FBE#[7:4] IX Bus FBE#[3:0] ...
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Intel IXP1200 Network Processor Table 29. Pin State During Reset (Continued) Function Misc Test TCK_BYP Misc Test TSTCLK Misc Test SCAN_EN Processor PXTAL Support Processor CINT# Support Processor RESET_IN# Support Processor RESET_OUT# Support Serial RXD Serial TXD IEEE 1149.1 ...
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Electrical Specifications This chapter specifies the following electrical behavior of the IXP1200: • Absolute maximum ratings. • DC specifications. • AC timing specifications for the following signal interfaces: — PXTAL Clock input. — PCI Bus Interface. — IX Bus ...
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Intel IXP1200 Network Processor The power specifications listed below are based on the following assumption: • PCI Bus Frequency (PCI_CLK MHz. Table 31. Functional Operating Range Parameter Operating temperature range Supply voltage (core and PLL), VDD, VDDP1 ...
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Figure 12. Typical IXP1200 Heatsink Application 12.5 10.0 7.5 5.0 2.5 0 Note: The heat sink comparison shown in package mounted inch-by-4 inch test board. Note: Refer to the IXP1200 Network Processor Family Heatsinks: ja and Airflow ...
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Intel IXP1200 Network Processor 7.2 DC Specifications The IXP1200 supports two fundamental I/O buffer Types: Type 1 and Type 2. The Pin Description section defines which pins use which I/O buffer type. The driver characteristics are described in the ...
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Type 2 Driver DC Specifications Table 35 refers to pin types: I2, O2. Table 35. I2 and O2 Pin Types Symbol Input leakage currents include high ...
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Intel IXP1200 Network Processor 7.3 AC Specifications 7.3.1 Clock Timing Specifications The ac specifications consist of input requirements and output responses. The input requirements consist of setup and hold times, pulse widths, and high and low times. Output responses ...
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PXTAL Clock Oscillator Specifications Frequency: Stability: Voltage signal level: Rise/fall time: Duty cycle: 7.3.4 PCI 7.3.4.1 PCI Electrical Specification Conformance The IXP1200 PCI pins support the basic set of PCI electrical specifications in the PCI Local Bus Specification, Revision ...
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Intel IXP1200 Network Processor Table 39. 33 MHz PCI Clock Signal AC Parameters Symbol T cyc T high T low 1. 0.2 VDDX to 0.6 VDDX. 2. Not tested. Guaranteed by design. Figure 15. PCI Bus Signals PCI_CLK Outputs ...
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PCI Bus Signals Timing Table 40. 33 MHz PCI Signal Timing Symbol CLK to signal valid delay, bused 1 T val signals 1 T CLK to signal valid delay, val (point-to-point) point-to-point signals 3 T Float to active delay ...
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Intel IXP1200 Network Processor 7.3.5 Reset 7.3.5.1 Reset Timings Specification Table 42 shows the reset timing specifications for RESET_IN# and RESET_OUT#. Table 42. Reset Timings Specification Symbol RESET_IN# asserted after power t RST stable. t GPIO[3] setup to reset ...
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IEEE 1149.1 The following pins are considered IEEE 1149.1 compliance pins: RESET_IN# PCI_CLK SCAN_EN TCK_BYP TSTCLK The following pins are not connected to the Boundary Scan ring: RESET_IN# PCI_CLK SCAN_EN TCK_BYP TSTCLK TCK TMS TDI TDO TRST# Caution: A ...
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Intel IXP1200 Network Processor 7.3.6.1 IEEE 1149.1 Timing Specifications Figure 17. IEEE 1149.1/Boundary-Scan General Timing 78 Tbscl tck tms, tdi Tbsis Tbsih tdo Tbsoh Tbsod Data In Tbsss Tbssh Data Out Tbsdh Tbsdd Tbsch A4772-01 Datasheet ...
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Figure 18. IEEE 1149.1/Boundary-Scan Tri-State Timing Data Out Table 43 shows the IEEE 1149.1/boundary-scan interface timing specifications. Table 43. IEEE 1149.1/Boundary-Scan Interface Timing Symbol Freq TCK frequency T TCK low period bscl T TCK high period bsch T TDI,TMS setup ...
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Intel IXP1200 Network Processor 7.3.7 IX Bus 7.3.7.1 FCLK Signal AC Parameter Measurements Figure 19. FCLK Signal AC Parameter Measurements V ptp Table 44. FCLK Signal AC Parameter Measurements Symbol F CLK high 2 T ...
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IX Bus Signals Timing Figure 20. IX Bus Signals Timing CLK Outputs Inputs Table 45. IX Bus Signals Timing Symbol Parameter T Clock to output delay val Data input setup time before T su clock Data input hold time ...
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Intel IXP1200 Network Processor Table 46. Signal Delay Derating Signal FDATA[63:0] 0.055 FBE#[7:0] 0.055 FPS[2:0] 0.065 TK_REQ_OUT 0.065 TK_REQ_IN 0.065 RDYCTL#[4:0] 0.065 RDYBUS[7:0] 0.065 TXAXIS 0.065 EOP 0.065 SOP 0.065 GPIO[3:0] 0.065 PORTCTL#[3:0] 0.095 TK_OUT 0.095 RXFAIL 0.095 82 ...
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FCLK MAC0/Rx A PORTCTL#[0] PORTCTL#[1] PORTCTL#[2] PORTCTL#[3] FPS[2:0] Port A FDAT[63:0] Ra0 Ra3 Ra4 Ra5 Ra6 Ra7 Tb0 Ra1 Ra2 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: int_1200_OE is not an IXP1200 signal shown to indicate when the IXP1200 drives ...
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FCLK PORTCTL#[3:0] No Select MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. ...
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FCLK PORTCTL#[3:0] MAC0/Rx A MAC1/ Select ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# ext_MAC3_Tx# FPS[2:0] Port A Port B FDAT[63:0] Ra1 Ra4 Ra5 Ra6 Ra7 Tb1 Tb2 Tb3 Tb6 Tb7 Ra0 Tb0 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] Int_1200_OE Notes: Signals using prefix "ext_" are ...
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FCLK PORTCTL#[3:0] MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE is ...
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FCLK PORTCTL#[3:0] MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE is not ...
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FCLK PORTCTL#[3:0] MAC0/ Select ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE is ...
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FCLK No Select PORTCTL#[3:0] No Select MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE ...
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FCLK PORTCTL#[3:0] MAC0/ Select ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE is not an ...
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FCLK No Select PORTCTL#[3:0] MAC0/ Sel ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE is not an IXP1200 ...
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FCLK No Select No Select PORTCTL#[3:0] MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ ...
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FCLK No PORTCTL#[3:0] MAC0/Rx A Sel ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. ...
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FCLK No Select PORTCTL#[3:0] MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. ...
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FCLK No Select PORTCTL#[3:0] MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE ...
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FCLK No PORTCTL#[3:0] MAC0/Rx A Sel ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# Port A FPS[2:0] FDAT[63: Ra0 Ra1 Ra2 Ra3 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ ...
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FCLK No Sel No Sel PORTCTL#[7 :0] MAC0/Rx A MAC1/Rx B ext_MAC0_Rx# ext_MAC1_Rx# FPS[2:0] Port A Fetch-9 FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 Ra8 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an ...
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FCLK No Sel No Sel PORTCTL#[3:0] MAC0/Tx A ext_MAC0_Tx# ext_MAC1_Tx# ext_MAC2_Tx# FPS[2:0] Port A FDAT[63:0] Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ ...
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FCLK No Sel No Sel PORTCTL#[3:0] MAC0/Tx A ext_MAC0_Tx# ext_MAC1_Tx# ext_MAC2_Tx# FPS[2:0] Port A FDAT[63:0] Ta3 TaP Ta0 Ta1 Ta2 Ta4 Ta5 Ta6 Ta7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in ...
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FCLK No Sel PORTCTL#[1 :0] MAC0/Rx A MAC1/ used with PORTCTL# RDYCTL#[4]/ 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# FPS[2:0] Port FDAT[31:0] Ra0 Ra1 Ra2 Ra3 Rb0 Rb1 Rb2 Rb3 14 ...
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FCLK No Sel No Sel PORTCTL#[1:0] MAC0/Rx A MAC1/ used with PORTCTL# RDYCTL#[4]/ 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# Port A Port B FPS[2: FDAT[31:0] Ra0 Ra1 Rb0 Rb1 14 13 ...
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FCLK No Sel No Sel PORTCTL#[1:0] MAC0/Rx A MAC1/ used with PORTCTL# RDYCTL#[4]/ 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# FPS[2:0] Port FDAT[31:0] Ra0 Ra1 Ra2 Ra3 RaS 14 13 SOP/SOP_RX EOP/EOP_RX ...
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FCLK No Sel No Sel PORTCTL#[1:0] MAC0/Rx A MAC1/ used with PORTCTL# RDYCTL#[4]/ 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# Port A FPS[2:0] Ra FDAT[31:0] Ra0 Ra1 Ra2 Ra3 RaS 13 SOP/SOP_RX EOP/EOP_RX FBE#[3:0] Notes: ...
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FCLK No Sel No Sel PORTCTL#[1:0] MAC0/Rx A MAC1/ used with PORTCTL# RDYCTL#[4]/ 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# FPS[2:0] Port A Ra FDAT[31:0] Ra0 Ra1 Ra2 RaS 12 SOP/SOP_RX EOP/EOP_RX FBE#[3:0] Notes: Signals ...
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FCLK No PORTCTL#[1:0] MAC0/Rx A MAC0/Rx B Sel ( used with PORTCTL# RDYCTL#[4] 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# Port A FPS[2: FDAT[31:0] Ra1 Ra0 SOP/SOP_RX EOP/EOP_RX FBE#[3:0] Notes: Signals ...
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FCLK No No PORTCTL#[1:0] MAC0/Rx A MAC1/Rx B Sel Sel ( used with PORTCTL# RDYCTL#[4] 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# FPS[2:0] Port A Port FDAT[31:0] Ra0 Ra1 Rb0 Rb1 29 30 ...
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FCLK No Sel No Sel PORTCTL#[3:2] MAC0/Tx A GPIO[0]/ ( used with PORTCTL# FC_EN0#/TXPEN 3+ MAC mode only ) ext_MAC0_Tx# ext_MAC1_Tx# ext_MAC2_Tx# Port A GPIO[3:1] FDAT[31:0] Ta0 Ta1 Ta2 Ta3 Ta15 TK_REQ_OUT/ SOP_TX TK_REQ_IN/ EOP_TX FBE#[7:4] Notes: Signals using prefix ...
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FCLK No Sel PORTCTL#[3:2] MAC0/Tx A GPIO[0]/ ( used with PORTCTL# FC_EN0#/TXPEN 3+ MAC mode only ) ext_MAC0_Tx# ext_MAC1_Tx# ext_MAC2_Tx# Port A GPIO[3:1] TaP TaP FDAT[31:0] Ta0 Ta1 Ta2 Ta14 Ta15 0 1 TK_REQ_OUT/ SOP_TX TK_REQ_IN/ EOP_TX FBE#[7:4] Notes: Signals ...
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FCLK No PORTCTL#[3:0] FastPort/Rx Port 0 req#1 No Select - See Footnote* Sel ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=0 FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs ...
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FCLK No PORTCTL#[3:0] FastPort/Rx Port 0 req#1 Sel ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=5 FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in ...
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FCLK No PORTCTL#[3:0] FastPort/Rx Port 0 req#1 No Select - 5 clks Sel ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=0 FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs ...
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FCLK PORTCTL#[3:0] FastPort/Rx Port 0 req#1 No Select-5 clks ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=5 FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder ...
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FastPort request #2 pending FCLK PORTCTL#[3:0] FastPort/Rx Port 0 req#1 No Sel ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=0 FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC ...
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FCLK No PORTCTL#[3:0] FastPort/Rx Port 0 req#1 Sel ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT = don't care FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs of an ...
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FCLK No Sel PORTCTL#[3:0] FastPort/Rx Port 0 req#1 FastPort/Rx Port 1 req#1 ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=0 FAST_RX1 FAST_RX for Port 1 req#1 sampled FAST_RX2 int_1200_OE Notes: ...
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FCLK PORTCTL#[3:0] FastPort/Rx Port 0 req#1 No Select ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] FAST_RX for Port 0 req#2 sampled register FP_READY_WAIT=0 FAST_RX1 FAST_RX for Port 1 req#1 sampled- pending ...
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RDYBus Figure 55. Consecutive Fetch Ready Flags, 1-2 MAC Mode (with No External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=1 FCLK RDYCTL#[0] RDYCTL#[1] RDYCTL#[2] RDYCTL#[3] RDYBUS[7:0] Figure 56. Consecutive Fetch Ready Flags, 3+ MAC Mode (with External Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 FCLK RDYCTL#[4:0] ...
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Intel IXP1200 Network Processor Figure 57. Fetch Ready Flags, Get/Send Commands, 3+ MAC Mode (with External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 FCLK MAC0/TxRdy RDYCTL#[3:0] NOP ext_MAC0_TxRdy# RDYBUS[7:0] Note: Signals using prefix "ext_" are outputs of an external decoder in 3+ ...
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Figure 59. Ready Bus Control Timing, Fetch Ready Flags - Flow Control - Fetch Ready Flags, 3+ MAC Mode (with External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 FCLK RDYCTL#[4:0] ext_MAC0_RxRdy# ext_MAC1_RxRdy# ext_MAC2_RxRdy# ext_MAC0_FC# RDYBUS[7:0] Notes: Configuration uses an external Flow Control latch, ...
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Intel IXP1200 Network Processor 7.3.7.5 TK_IN/TK_OUT The following timing diagrams show the transition from one IX Bus owner to another. Note that prior to giving up the bus, the PORTCTL[4:0] signals are driven high which will not select any ...
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Table 47. SRAM SCLK Signal AC Parameter Measurements Symbol Freq Clock frequency T Cycle time cyc T Clock high time high T Clock low time low SCLK rise/fall time r f Datasheet Minimum (IXP1200 Core Speed) Parameter ...
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Intel IXP1200 Network Processor 7.3.8.2 SRAM Bus Signal Timing Figure 62. SRAM Bus Signal Timing SCLK Outputs Inputs Table 48. SRAM Bus Signal Timing Symbol T Clock to data output valid delay val T Clock to control outputs valid ...
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Table 49. Signal Delay Deratings for T Signal 83 MHz SCLK 0.053 SLOW_EN# 0.065 SWE# 0.065 SLOW_RD# 0.065 SLOW_WE# 0.065 SP_CE# 0.065 SOE# 0.065 HIGH_EN# 0.065 LOW_EN# 0.065 CE#[3:0] 0.065 A[18:0] 0.065 DQ[31:0] 0.065 Datasheet and T val ctl Maximum ...
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Intel IXP1200 Network Processor 7.3.8.3 SRAM Bus - SRAM Signal Protocol and Timing Figure 63. Pipelined SRAM Read Burst of Eight Longwords SCLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] A[18:0] SWE# SOE# DQ[31:0] Figure 64. Pipelined SRAM Write Burst ...
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Figure 65. Pipelined SRAM Read Burst of Four From Bank 0 Followed by Write Burst of Four From Bank 8 SCLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] A[18:0] SWE# SOE# DQ[31:0] Note 1: There is always a 1 clock cycle ...
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Intel IXP1200 Network Processor Figure 66. Pipelined SRAM Longword Write Followed by 2 Longword Burst Read Followed by 4 Longword Burst Write SCLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] A[18:0] SWE# SOE# DQ[31:0] Note 1: There is always a ...
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Figure 67. Flowthrough SRAM Read Burst of Eight Longwords SACLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] A[18:0] SWE# SOE# DQ[31:0] Datasheet ® Intel IXP1200 Network Processor CE#[3:0] = 1110 D(A0) D(A1) D(A2) D(A3) ...
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Intel IXP1200 Network Processor 7.3.8.4 SRAM Bus - BootROM and SlowPort Timings Timing for the BootROM and SlowPort areas are programmable through the SRAM configuration registers described in the IXP1200 Network Processor Family Microcode Programmer’s Reference Manual. The designer ...
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Figure 69. BootROM Write A[18:0] DQ[31:0] SLOW_EN# SLOW_RD# SLOW_WE# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] Externally Generated Signal BootROM Chip select signal SLOW_EN# or CE#<3:0> Cycle Count = Example for the following setting in SRAM registers SRAM_SLOW_CONFIG 31:16 RES SRAM_BOOT_CONFIG 31:24 23:16 09 ...
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Intel IXP1200 Network Processor Figure 70. Pipelined SRAM Two Longword Burst Read Followed by BootROM Write SCLK A[18:0] DQ[31:0] Buffered DQ[31:0] SLOW_EN# SLOW_RD# SLOW_WE# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] SWE# SOE# BootROM_CE#[3:0] 130 A1 A2 D(A1) D(A1) D(A2) CE#<3:0> = 1110 ...
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SRAM Bus - Slow-Port Device Signal Protocol and Timing Figure 71. SRAM SlowPort Read DQ[31:0] SLOW_EN# SLOW_RD# SLOW_WE# HIGH_EN#/RDY# LOW_EN#/DIRW# SP_CE# Externally Generated Signal SRAM SlowPort Chip select signal - SP_CE# & address Cycle Count = Example for the ...
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Intel IXP1200 Network Processor Figure 72. SRAM SlowPort Write A[18:0] DQ[31:0] SLOW_EN# SLOW_RD# SLOW_WE# HIGH_EN#/RDY# LOW_EN#/DIRW# SP_CE# Externally Generated Signal SRAM SlowPort Chip select signal - SP_CE# & address Cycle Count = Example for the following setting in SRAM ...
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Figure 73. SRAM SlowPort RDY# SCLK A[18:0] DQ[31:0] SLOW_EN# SLOW_RD# SLOW_WE# HIGH_EN#/RDY# LOW_EN#/DIRW# SP_CE# ext_CE# (SP_CE#.AND.Ax) Cycle_count Register Settings used for these timings: SRAM_SLOW_CONFIG=000A:0B0Fh where RDY# Pause State=Ah, BCC=0Bh, and SCC=0Fh SRAM_SLOWPORT_CONFIG=0D0E:0501h where SRWA=0Dh, SCEA=0Eh, SRWD=05h, SCED=01 SRAM_CSR=0009:4810h where <19>=1, ...
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Intel IXP1200 Network Processor Figure 74. Pipelined SRAM Two Longword Burst Read Followed By SlowPort Write SCLK A[18:0] DQ[31:0] Buffered DQ[31:0] SP_CE# SLOW_EN# SLOW_RD# SLOW_WE# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] SWE# SOE# BootROM_CE#[3:0] 134 D(A1) D(A2) D(A3) CE#[3:0] ...
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SDRAM Interface 7.3.9.1 SDCLK AC Parameter Measurements Figure 75. SDCLK AC Timing Diagram Vt1 = 0.5*VDDX Vt2 = 0.4*VDDX Vt3 = 0.3*VDDX Table 50. SDCLK AC Parameter Measurements Symbol Freq Clock frequency T Cycle time cyc T Clock high ...
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Intel IXP1200 Network Processor 7.3.9.2 SDRAM Bus Signal Timing Figure 76. SDRAM Bus Signal Timing Control Outputs (RAS#, CAS#, WE#, DQM, MADR) Table 51. SDRAM Bus Signal Timing Parameters Symbol T Clock to data output valid delay val T ...
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Table 52. Signal Delay Deratings for T Signal 83 MHz SDCLK 0.053 DQM 0.065 WE# 0.065 RAS# 0.065 CAS# 0.065 MADR[14:0] 0.065 MDATA[63:0] 0.095 7.3.9.3 SDRAM Signal Protocol This section describes the SDRAM timing parameters referenced in the SDRAM timing ...
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Intel IXP1200 Network Processor altogether, and simply have this time be the sum of tRP and tRASmin, as discussed above. The IXP1200 Network Processor Family Microcode Programmer’s Reference Manual refers to this as the tRC Bank Cycle Time. Also ...
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Figure 77. SDRAM Initialization Sequence SDCLK RAS# CAS# WE# MADR MDAT DQM Notes: 1. Number of total initialization phase refresh cycles programmed as INIT_RFRSH value in register SDRAM_MEMINIT. 2. Burst length and CAS latency values programmed as BURSTL value in ...
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Intel IXP1200 Network Processor Figure 78. SDRAM Read Cycle SDCLK RAS# CAS# WE# MADR MDAT DQM Notes: 1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1 2. CAS Latency value (CASL ...
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Figure 80. SDRAM Read-Modify-Write Cycle SDCLK RAS# CAS# WE# MADR MDAT DQM Notes: 1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1 2. CAS Latency value (CASL programmed in SDRAM_MEMCTL0 7.4 Asynchronous ...
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Intel IXP1200 Network Processor 8.0 Mechanical Specifications 8.1 Package Dimensions The IXP1200 is contained in a 432-HL-PBGA package, as shown in the following illustrations. Figure 81. IXP1200 Part Marking Pin 1 142 i GCIXP1200XX FPO# INTEL(M)(C)2001 XXXXXXXXXXX xxxxxxxSz YYWW ...
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Figure 82. 432-Pin HL-BGA Package - Bottom View 0. Figure 83. IXP1200 Side View Figure 84. IXP1200 A-A Section View Datasheet ...
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Intel IXP1200 Network Processor 8.2 IXP1200 Package Dimensions (mm) Table 53. IXP1200 Package Dimensions (mm) Symbol A Overall thickness A Ball height 1 A Body thickness 2 D Body size D Ball footprint 1 E Body size E Ball ...