MT46V32M4TG-75Z Micron Semiconductor Products, MT46V32M4TG-75Z Datasheet
MT46V32M4TG-75Z
Related parts for MT46V32M4TG-75Z
MT46V32M4TG-75Z Summary of contents
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DOUBLE DATA RATE (DDR) SDRAM FEATURES • +2.5V ±0.2V +2.5V ±0. • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two – one per byte) • Internal, ...
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... DDR SDRAM PART NUMBERS (Note: xx= -75, -75Z, or -8) PART NUMBER CONFIGURATION MT46V32M4TG-xx MT46V32M4TG-xxL MT46V16M8TG-xx MT46V16M8TG-xxL MT46V8M16TG-xx MT46V8M16TG-xxL GENERAL DESCRIPTION The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits internally configured as a quad- bank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation ...
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TABLE OF CONTENTS Functional Block Diagram – 32 Meg x 4 ............... Functional Block Diagram – 16 Meg x 8 ............... Functional Block Diagram – 8 Meg x 16 ............. Pin Descriptions ...................................................... Functional Description ......................................... Initialization ...................................................... Register Definition ...
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CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH 12 MODE REGISTERS COUNTER 12 12 A0-A11, ADDRESS 14 BA0, BA1 REGISTER 2 11 128Mb: x4, x8, x16 DDR SDRAM 128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01 FUNCTIONAL BLOCK DIAGRAM 32 ...
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CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH 12 COUNTER MODE REGISTERS 12 12 A0-A11, ADDRESS 14 BA0, BA1 REGISTER 2 10 128Mb: x4, x8, x16 DDR SDRAM 128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01 FUNCTIONAL BLOCK DIAGRAM 16 ...
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CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER 12 MODE REGISTERS ROW- ADDRESS MUX A0-A11, ADDRESS 14 BA0, BA1 REGISTER 2 9 128Mb: x4, x8, x16 DDR SDRAM 128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01 ...
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PIN DESCRIPTIONS TSOP PIN NUMBERS SYMBOL 45, 46 CK, CK# 44 CKE 24 CS# 23, 22, 21 RAS#, CAS#, WE 20, 47 LDM, UDM 26, 27 BA0, BA1 29-32, 35-40, A0–A11 28 ...
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PIN DESCRIPTIONS (continued) TSOP PIN NUMBERS SYMBOL 51 DQS 16, 51 LDQS, UDQS 3, 9, 15, 55 12, 52 34, 48 ...
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FUNCTIONAL DESCRIPTION The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. The 128Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed ...
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Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that ...
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Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set 2.5 clocks, as shown ...
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EXTENDED MODE REGISTER The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, and QFC#. These functions are con- trolled via the bits shown in Figure 3. The ...
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Commands Truth Table 1 provides a quick reference of avail- able commands. This is followed by a verbal descrip- tion of each command. Two additional Truth Tables TRUTH TABLE 1 – COMMANDS (Note: 1) NAME (FUNCTION) DESELECT (NOP) NO OPERATION ...
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DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to ...
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AUTO REFRESH AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS#-BE- FORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs. This command is nonpersistent must be issued each time a refresh is required. The ...
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Operations BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and ...
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READS READ bursts are initiated with a READ command, as shown in Figure 6. The starting column and bank addresses are pro- vided with the READ command and auto precharge is either enabled or disabled for that burst access. If ...
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T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ NOTE data-out from column n. 2. Burst length = 4. 3. Three ...
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T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ NOTE ( data-out from column n (or column b). 2. Burst ...
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T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ NOTE ( data-out from column n (or column b). 2. Burst ...
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T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS DQ T0 CK# CK COMMAND COMMAND READ Bank, ADDRESS ADDRESS Col n DQS DQ NOTE ( data-out from column n (or ...
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READs (continued) Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 11. The BURST TERMINATE latency is equal to the READ (CAS) latency, i.e., the BURST TERMINATE command should be issued x ...
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T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ T0 CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ NOTE data-out from column n. 2. Burst length = 4. 3. Subsequent ...
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T0 CK# CK COMMAND READ Bank, ADDRESS Col n DQS CK# CK COMMAND READ Bank a, ADDRESS Col n DQS DQ DM NOTE data-out from column data-in from ...
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T0 CK COMMAND READ Bank a, ADDRESS Col n DQS COMMAND READ Bank a, ADDRESS Col n DQS DQ NOTE data-out from column n. 2. Burst length = 4, ...
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WRITES WRITE bursts are initiated with a WRITE com- mand, as shown in Figure 14. The starting column and bank addresses are pro- vided with the WRITE command, and auto precharge is either enabled or disabled for that access. If ...
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CK# CK COMMAND ADDRESS t DQSS (NOM) DQS DQSS (MIN) DQS DQSS (MAX) DQS DQ DM NOTE data-in for column b. 2. Three subsequent elements of data-in are applied in ...
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T0 CK# CK COMMAND WRITE Bank, ADDRESS Col DQSS (NOM) DQSS DQS DQ DM NOTE etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the programmed order ...
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T0 CK# CK COMMAND WRITE Bank, ADDRESS Col DQSS (NOM) DQSS DQS DQ DM NOTE etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the programmed order ...
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T0 CK# CK COMMAND WRITE Bank, ADDRESS Col b t DQSS (NOM) DQS DQ DM NOTE etc. = data-in for column b, etc. 2. b', etc. = the next data-in following DI b, etc., according to the ...
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T0 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM NOTE ...
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T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM NOTE ...
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T0 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM NOTE ...
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T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM NOTE ...
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T0 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM NOTE ...
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T0 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM NOTE ...
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PRECHARGE The PRECHARGE command (Figure 25) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( the PRECHARGE ...
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TRUTH TABLE 2 – CKE (Notes: 1-4) CKE CKE CURRENT STATE n Power-Down Self Refresh L H Power-Down Self Refresh H L All Banks Idle Bank(s) Active All Banks Idle NOTE: 1. CKE is the logic state ...
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TRUTH TABLE 3 – CURRENT STATE BANK n – COMMAND TO BANK n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle L ...
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NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ...
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TRUTH TABLE 4 – CURRENT STATE BANK n – COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle Row ...
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NOTE (continued): 3. Current state definitions: Idle: The bank has been precharged, and Row Active: A row in the bank has been activated, and and no register accesses are in progress. Read: A READ burst has been initiated, with auto ...
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ABSOLUTE MAXIMUM RATINGS* V Supply Voltage DD Relative to V ...................................... -1V to +3. Supply DD Voltage Relative to V ........................ -1V to +3. and Inputs Voltage REF Relative to V ....................................... -1V to +3.6V ...
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Transmitter 128Mb: x4, x8, x16 DDR SDRAM 128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/ (2.3V minimum (1.670V for SSTL2 termination) OH(MIN) System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation) 1.560V 1.400V 1.300V 1.275V 1.250V 1.225V 1.200V ...
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CLOCK INPUT OPERATING CONDITIONS (Notes: 1–5, 15, 16, 30; notes appear on pages 50–53) (0°C ≤ T PARAMETER/CONDITION Clock Input Mid-Point Voltage; CK and CK# Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock ...
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CAPACITANCE (x4, x8) (Note: 13; notes appear on pages 50–53) PARAMETER Delta Input/Output Capacitance: DQs, DQS, DM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command and Address Input Capacitance: ...
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CAPACITANCE (x16) (Note: 13; notes appear on pages 50–53) PARAMETER Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM ...
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 1–5, 14–17, 33; notes appear on pages 50–53) (0°C ≤ CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time DQ and DM ...
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SLEW RATE DERATING VALUES (Note: 14; notes appear on pages 50–53) (0°C ≤ T SPEED SLEW RATE -75/-75Z 0.500V / ns -75/-75Z 0.400V / ns -75/-75Z 0.300V / ns -75/-75Z 0.200V / ns -8 0.500V / ns -8 0.400V / ...
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NOTES 1. All voltages referenced Tests for AC timing and electrical AC and DD DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaran- teed ...
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NOTES (continued) 23. The refresh period 64ms. This equates to an average refresh rate of 15.625µs. However, an AUTO REFRESH command must be asserted at least once every 140.6µs; burst refreshing or posting by the DRAM controller greater than eight ...
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NOTES (continued) 32. V must not vary more than 4% if CKE is not DD active while any bank is active. 33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the ...
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NOTES (continued) 39. The voltage levels used are derived from a minimum V level and the referenced test load practice, the voltage levels obtained from a properly terminated bus will provide signifi- cantly different voltage values. 40. VIH ...
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NORMAL OUTPUT DRIVE CHARACTERISTICS PULL-DOWN CURRENT (mA) VOLTAGE NOMINAL NOMINAL (V) LOW HIGH 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 49.8 0.9 47.5 55.2 ...
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REDUCED OUTPUT DRIVE CHARACTERISTICS PULL-DOWN CURRENT (mA) VOLTAGE NOMINAL NOMINAL (V) LOW HIGH 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.9 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 26.9 31.3 ...
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CK DQS QFC# DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First data no longer valid) All DQs and ...
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CK LDQS DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First data no longer valid) DQ0 - DQ7 and LDQS, collectively 1 UDQS DQ (Last ...
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T0 CK (MIN) 2 DQS, or LDQS/UDQS DQ (Last data valid) DQ (First data valid) 3 All DQs collectively NOTE DQSCK is the DQS output window relative to CK and is the“long term” component ...
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INITIALIZE AND LOAD MODE REGISTERS ( ( ) ) VTD ( ( REF ) ) CK LVCMOS CKE ...
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T0 CK CKE VALID 1 COMMAND ADDR VALID DQS DQ DM Power-Down NOTE this command is a PRECHARGE (or if the device is ...
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CKE NOP 2 COMMAND PRE 1 A0-A9, A11 ALL BANKS 1 A10 ONE BANK Bank(s) 3 BA0, BA1 4 DQS ...
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T0 CK CKE COMMAND NOP ADDR DQS NOTE: 1. Clock must be stable before exiting self refresh mode. That is, the ...
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BANK READ – WITHOUT AUTO PRECHARGE CKE NOP 6 COMMAND ACT x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 x8: A11 ...
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CKE NOP 5 COMMAND ACT x4: A0-A9, A11 x8: A0-A9 RA x16: A0-A8 x8: A11 RA x16: A9, A11 A10 RA ...
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BANK WRITE – WITHOUT AUTO PRECHARGE CKE NOP 6 COMMAND ACT t IS x4: A0-A9, A11 RA x8: A0-A9 x16: A0-A8 x8: A11 RA x16: A9, A11 ...
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BANK WRITE – WITH AUTO PRECHARGE CKE NOP 5 COMMAND ACT x4: A0-A9, A11 RA x8: A0-A9 x16: A0-A8 x8: A11 RA ...
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CKE NOP 6 COMMAND ACT x4: A0-A9, A11 RA x8: A0-A9 x16: A0-A8 x8: A11 RA x16: A9, A11 A10 RA t ...
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TYP 0.32 ± .075 TYP PIN # All dimensions in millimeters MAX or typical here noted. NOTE: 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. ...