MT46V16M16TG-6T Micron Semiconductor Products, MT46V16M16TG-6T Datasheet

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MT46V16M16TG-6T

Manufacturer Part Number
MT46V16M16TG-6T
Description
4 Meg x 16 x 4banks, CL=2.5, 167MHz double data rate (DDR) SDRAM
Manufacturer
Micron Semiconductor Products
Datasheet

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DOUBLE DATA RATE
(DDR) SDRAM
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
FEATURES
• 167 MHz Clock, 333 Mb/s/p data rate
• V
• Bidirectional data strobe (DQS) transmitted/
• Internal, pipelined double-data-rate (DDR)
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
• 2.5V I/O (SSTL_2 compatible)
• Backwards compatible with DDR200 and DDR266
OPTIONS
• Configuration
• Plastic Package
• Timing - Cycle Time
• Self Refresh
NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION AND DATA SHEET SPECIFICATIONS.
received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)
architecture; two data accesses per clock cycle
aligned with data for WRITEs
two - one per byte)
t
64 Meg x 4 (16 Meg x 4 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
66-Pin TSOP (OCPL)
60-Ball FBGA (16x9mm)
Standard
RAS lockout (
DD
6ns @ CL = 2.5 (DDR333B–FBGA)
6ns @ CL = 2.5 (DDR333B–TSOP)
7.5ns @ CL = 2 (DDR266A)
= +2.5V ±0.2V, V
2. Supports PC2100 modules with 2-3-3 timing
t
RAP =
t
DD
RCD)
Q = +2.5V ±0.2V
2
PART NUMBER
1
1
16M16
64M4
32M8
none
-75Z
-6T
T G
FJ
-6
1
MT46V64M4 – 16 Meg x 4 x 4 banks
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
DDR333 COMPATIBILITY
quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
support concurrent auto-precharge and
for improved timing performance.
DDR333 device will support an (
odic refresh interval of 7.8us.
point-to-point applications where the FBGA package
is intended for the multi-drop systems.
cations and functionality unless specified herein.
CONFIGURATION
KEY TIMING PARAMETERS
NOTE: 1. CL = CAS (Read) Latency
GRADE
Architecture
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
SPEED
-75Z
DDR333 meets or surpasses all DDR266 timing re-
The Micron 256Mb data sheet provides full specifi-
-6T
-6
The standard 66-pin TSOP package is offered for
DDR333 SDRAM Addendum
2. With a 50/50 clock duty cycle and a minimum clock
3. -75, -8 are also available; see base data sheet.
www.micron.com/dramds
133 MHz
133 MHz
133 MHz
CL = 2
rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CLOCK RATE
16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
2K (A0–A9, A11)
1
64 Meg x 4
8K (A0–A12)
4 (BA0, BA1)
CL = 2.5
167 MHz
167 MHz
133 MHz
8K
256Mb: x4, x8, x16
1
WINDOW
DATA-OUT ACCESS DQS-DQ
32 Meg x 8
2.15ns
8K (A0–A12)
4 (BA0, BA1)
1K (A0–A9)
2.0ns
2.5ns
8K
t
3
REFI) average peri-
2
PRELIMINARY
WINDOW SKEW
±0.70ns
±0.75ns
±0.75ns
©2001, Micron Technology, Inc.
The 256Mb,
t
RAS lockout
16 Meg x 16
512 (A0– A8)
8K (A0–A12)
4 (BA0, BA1)
8K
+0.35ns
+0.45ns
+0.50ns

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MT46V16M16TG-6T Summary of contents

Page 1

DOUBLE DATA RATE (DDR) SDRAM FEATURES • 167 MHz Clock, 333 Mb/s/p data rate • +2.5V ±0.2V +2.5V ±0. • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 ...

Page 2

FBGA 60-BALL PACKAGE DIMENSION 0.850 ±0.075 SEATING PLANE C 0.10 C 6.40 1.80 CTR 61X 0.45 0.80 TYP SOLDER BALL DIAMETER REFERS TO POST REFLOW PIN A1 ID CONDITION. THE PRE- REFLOW DIAMETER IS Ø 0.40 BALL A9 BALL A1 ...

Page 3

TSOP PACKAGE DIMENSION 22.22 ± 0.08 0.65 TYP 0.32 ± .075 TYP PIN #1 ID 1.20 MAX GAGE PLANE 0.25 +0.10 0.10 -0.05 0.80 TYP 0.50 ±0.10 DETAIL A NOTE: 1. All dimensions in millimeters. 2. Package width and ...

Page 4

PIN DESCRIPTIONS BALL / PIN NUMBERS FBGA TSOP SYMBOL G2, G3 45, 46 CK, CK CKE H8 24 CS# H7, G8, G7 23, 22, 21 RAS#, CAS#, WE F7, 3F 20, 47 LDM, UDM J8,J7 ...

Page 5

PIN DESCRIPTIONS (continued) BALL / PIN NUMBERS FBGA TSOP SYMBOL A8, B9 DQ0-2 C9, C7 DQ3-5 D7, E9, E1 11, 13, 54 DQ6-8 D3, D1, C3 56, 57, 59 DQ9-11 C1, B3, ...

Page 6

GENERAL DESCRIPTION The DDR333 SDRAM is a high-speed CMOS, dy- namic random-access memory that operates at a fre- quency of 167 MHz ( t CK=6ns) with a peak data trans- fer rate of 333Mb/s/p. DDR333 continues to use the JEDEC ...

Page 7

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets) (0°C ≤ T ≤ 70° +2.5V ±0.2V CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK ...

Page 8

S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc. 256Mb: x4, ...

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