HY5DU56422BF-J Hynix Semiconductor, HY5DU56422BF-J Datasheet
HY5DU56422BF-J
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HY5DU56422BF-J Summary of contents
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... DDR SDRAM This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ July 2003 HY5DU56422B(L)F HY5DU56822B(L)F HY5DU56422B(L)F HY5DU56822B(L)F 1 ...
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Revision History 1. Revision 0.1 (July 2003) 1) Define Preliminary Specification Rev. 0.1 / July 2003 HY5DU56422B(L)F HY5DU56822B(L)F 2 ...
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DESCRIPTION The Hynix HY5DU56422 and HY5DU56822 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced ...
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PIN CONFIGURATION (X4 VSSQ NC VSS A NC VDDQ DQ3 B NC VSSQ VDDQ DQ2 D NC VSSQ DQS E VREF VSS A12 CKE H A11 ...
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PIN DESCRIPTION PIN TYPE CK, /CK Input CKE Input /CS Input BA0, BA1 Input A0 ~ A12 Input /RAS, /CAS, /WE Input DM Input (LDM, UDM) DQS I/O (LDQS, UDQS Supply Supply ...
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FUNCTIONAL BLOCK DIAGRAM (64Mx4) 4Banks x 16Mbit x 4 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE Command /CS Decoder /RAS /CAS /WE ADD Address Buffer BA Rev. 0.1 / July 2003 Write Data Register 2-bit Prefetch Unit 8 ...
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FUNCTIONAL BLOCK DIAGRAM (32Mx8) 4Banks x 8Mbit x 8 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE Command /CS Decoder /RAS /CAS /WE ADD Address Buffer BA Rev. 0.1 / July 2003 Write Data Register 2-bit Prefetch Unit 16 ...
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SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self ...
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WRITE MASK TRUTH TABLE Function CKEn-1 Data Write Data-In Mask Note : 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM ...
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OPERATION COMMAND TRUTH TABLE-I Current /CS /RAS State IDLE ROW L H ACTIVE L ...
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OPERATION COMMAND TRUTH TABLE-II Current /CS /RAS State WRITE READ WITH L H AUTOPRE CHARGE ...
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OPERATION COMMAND TRUTH TABLE-III Current /CS /RAS State ROW L H ACTIVATING WRITE L H RECOVERING ...
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OPERATION COMMAND TRUTH TABLE-IV Current /CS /RAS State WRITE MODE L H REGISTER ACCESSING ...
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CKE FUNCTION TRUTH TABLE Current CKEn- CKEn State SELF REFRESH POWER DOWN ...
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SIMPLIFIED STATE DIAGRAM MODE REGISTER SET POWER DOWN READ WRITE READAP WRITE WRITEAP PRE(PALL) Rev. 0.1 / July 2003 MRS SREF IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE ...
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF ...
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Issue 2 or more Auto Refresh commands. 8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low. Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK CKE CMD DM ADDR A10 BA0,BA1 ...
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MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is ...
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BURST DEFINITION Burst Length Starting Address (A2,A1,A0 BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column ...
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CAS LATENCY The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 1.5, 2, 2.5 or ...
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EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func- tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended ...
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ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative Voltage on V relative Voltage on V relative to V DDQ SS Output Short Circuit Current Power Dissipation Soldering Temperature ...
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DC CHARACTERISTICS II 64Mx4 Parameter Symbol One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and Operating Current DQS inputs changing twice per clock cycle; IDD0 address and control inputs changing once per clock cycle One bank; Active - Read - ...
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DC CHARACTERISTICS II 32Mx8 Parameter Symbol One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and Operating Current DQS inputs changing twice per clock cycle; IDD0 address and control inputs changing once per clock cycle One bank; Active - Read - ...
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DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7 IDD1 : Operating current: One bank operation 1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout ...
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AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note ...
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AC CHARACTERISTICS I Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay ...
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Parameter Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & ...
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AC CHARACTERISTICS II Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay ...
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Parameter Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width Write DQS High Level Width Write DQS Low Level Width Clock to ...
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Note : 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. 3. For command/address input slew ...
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DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 15. tDAL = (tDPL / tCK ) + (tRP ...
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CAPACITANCE o (T =25 C, f=100MHz ) A Parameter Input Clock Capacitance Delta Input Clock Capacitance Input Capacitance Delta Input Capacitance Input / Output Capacitance Delta Input / Output Capacitance Note : 1. VDD = min. to max., VDDQ = ...
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PACKAGE INFORMATION Rev. 0.1 / July 2003 8.0 ± 0.10 HY5DU56422B(L)F HY5DU56822B(L)F 34 ...