MT48LC2M8A1TG-8S Micron Semiconductor Products, MT48LC2M8A1TG-8S Datasheet
MT48LC2M8A1TG-8S
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MT48LC2M8A1TG-8S Summary of contents
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... AC = 6ns @ 10ns 9ns @ • Part Number Example: MT48LC2M8A1TG-10 S NOTE: The 16Mb SDRAM base number differentiates the offerings in two places: MT48LC2M8A1 S. The fourth field distinguishes the architecture offering: 4M4 designates 4 Meg x 4, and 2M8 designates 2 Meg x 8. The fifth field distinguishes the WRITE recovery offering: A1 designates one CLK and A2 designates two CLKs ...
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GENERAL DESCRIPTION (continued) and either 1,024 columns by 4 bits (4 Meg 512 columns by 8 bits (2 Meg x 8). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location ...
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TABLE OF CONTENTS Functional Block Diagram - 4 Meg x 4 ........................... Functional Block Diagram - 2 Meg x 8 ........................... Pin Descriptions ................................................................. Functional Description .................................................... Initialization ................................................................. Register Definitions ..................................................... Mode Register ........................................................ Burst Length ..................................................... Burst Type ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# MODE REGISTER 12 REFRESH ADDRESS CONTROLLER A0-A10 REGISTER REFRESH 11 COUNTER 11 16 Meg: x4, x8 SDRAM 16MSDRAMx4x8.p65 – Rev. 5/98 FUNCTIONAL BLOCK DIAGRAM 4 Meg x 4 SDRAM ROW- ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# MODE REGISTER 12 REFRESH ADDRESS CONTROLLER A0-A10 REGISTER REFRESH 11 COUNTER 11 16 Meg: x4, x8 SDRAM 16MSDRAMx4x8.p65 – Rev. 5/98 FUNCTIONAL BLOCK DIAGRAM 2 Meg x 8 SDRAM ROW- ...
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PIN DESCRIPTIONS PIN NUMBERS SYMBOL 32 CLK 31 CKE 15 CS# 14, 13, RAS#, CAS#, 12 WE# 33 DQM 16 BA 18-21, 24-29, 17 A0-A10 4, 8, 37, 41 x4: DQ0 x8: DQ1 ...
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FUNCTIONAL DESCRIPTION In general, the SDRAM is a dual memory array (the 4 Meg dual 2 Meg x 4, and the 2 Meg dual 1 Meg x 8) which operates at 3.3V ...
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BA A10 Reserved Mode CAS Latency BT *Should program M11, M10 = ensure compatibility with future devices ...
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CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set clocks. If ...
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COMMANDS Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Two additional Truth Tables appear following TRUTH TABLE 1 – Commands and DQM Operation (Notes: 1) NAME (FUNCTION) COMMAND ...
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COMMAND INHIBIT The COMMAND INHIBIT function prevents new com- mands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effec- tively deactivated, or deselected. NO OPERATION (NOP) The NO OPERATION (NOP) command ...
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AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analagous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is non- persistent must be issued each time a refresh is required. The addressing ...
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OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE com- mand, which selects both the bank and ...
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READs READ bursts are initiated with a READ command, as shown in Figure 5 ( “Don’t Care”on x8). The starting column and bank addresses are provided with the READ command, and AUTO PRECHARGE is either enabled or disabled ...
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CAS latency minus one. This is shown in Figure 7 for CAS latencies of one, two and three; data element either the last of a burst of four or the last desired of ...
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T0 CLK COMMAND ADDRESS DQ CAS Latency = 1 T0 CLK COMMAND ADDRESS DQ T0 CLK COMMAND ADDRESS DQ NOTE: Each READ command may be to either bank. DQM is LOW. 16 Meg: x4, x8 SDRAM 16MSDRAMx4x8.p65 – Rev. 5/98 ...
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A fixed-length READ burst may be followed by, or trun- cated with, a WRITE burst (provided that AUTO PRECHARGE was not activated), and a full-page READ burst may be truncated by a WRITE burst. The WRITE burst may be initiated ...
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A fixed-length READ burst may be followed by, or trun- cated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same ...
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AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the com- mand and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can ...
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WRITE s WRITE bursts are initiated with a WRITE command, as shown in Figure 13 ( “Don’t Care” on x8). The starting column and bank addresses are provided with the WRITE command and AUTO PRECHARGE is either enabled ...
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Full-speed random write accesses can be per- formed to the same bank, as shown in Figure 16, or each subsequent WRITE may be performed to a different bank. A fixed-length WRITE burst may be followed by, or truncated with, ...
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Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST ...
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CLOCK SUSPEND The clock suspend mode occurs when a column access/ burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on ...
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CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with AUTO PRECHARGE en- abled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO ...
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WRITE with AUTO PRECHARGE 3. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank t ...
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TRUTH TABLE 2 – CKE (Notes: 1-4) CKE CKE CURRENT STATE n Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L Both Banks Idle Both Banks Idle Reading or Writing H H ...
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TRUTH TABLE 3 – Current State Bank n - Command to Bank n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle L ...
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NOTE (continued): Write w/Auto- Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled, and ends when 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied ...
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TRUTH TABLE 4 – Current State Bank n - Command to Bank m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle Row ...
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NOTE (continued): Write w/Auto- Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled, and ends when 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. ...
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ABSOLUTE MAXIMUM RATINGS* Voltage Supply DD DD Relative to V ................................................ -1V to +4.6V SS Voltage on Inputs I/O Pins Relative to V ................................................ -1V to +4.6V SS Operating Temperature, T (ambient) .......... 0 ...
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CAPACITANCE PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes 11 + CHARACTERISTICS PARAMETER Access time from CLK ...
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AC FUNCTIONAL CHARACTERISTICS (Notes 11 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input ...
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NOTES 1. All voltages referenced This parameter is sampled MHz pin under test biased at 1.4V dependent on output loading and cycle ...
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INITIALIZE AND LOAD MODE REGISTER CLK ( ( CKH t CKS ( ( ( ( ) ) ) ) CKE ( ( ( ( ) ...
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CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP DQM ADDRESS BANK(S) High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks. power-down mode. TIMING ...
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CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM A0-A9 2 COLUMN ...
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T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP DQM ADDRESS BANK(S) High Precharge all active banks. TIMING PARAMETERS -8B SYMBOL* MIN MAX t AH ...
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T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM ADDRESS BANK(S) High Precharge all active banks. TIMING PARAMETERS -8B SYMBOL* MIN MAX ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM A0-A9 ROW ROW A10 DISABLE AUTO PRECHARGE ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 ...
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ALTERNATING BANK READ ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP READ t CMS DQM A0-A9 ROW COLUMN ROW A10 ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE ...
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WRITE – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM A0-A9 ROW ROW A10 DISABLE AUTO PRECHARGE ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP WRITE t CMS DQM COLUMN m 3 A0-A9 ROW ENABLE AUTO PRECHARGE ...
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ALTERNATING BANK WRITE ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM A0-A9 ROW ROW A10 BANK DQ t ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM A0-A9 ROW ROW A10 BANK DQ t RCD TIMING ...
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PIN #1 ID .0315 (0.80) TYP NOTE: 1. All dimensions in inches (millimeters) 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 16 Meg: x4, x8 ...