21285-AB Intel Corporation, 21285-AB Datasheet

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21285-AB

Manufacturer Part Number
21285-AB
Description
Microprocessor, 21285 Core Logic For SA-110 Microprocessor
Manufacturer
Intel Corporation
Datasheet

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21285 Core Logic for SA-110
Microprocessor
Datasheet
September 1998
Order Number:
278115-001

Related parts for 21285-AB

21285-AB Summary of contents

Page 1

... Core Logic for SA-110 Microprocessor Datasheet September 1998 Order Number: 278115-001 ...

Page 2

... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners. 21285 Core Logic for SA-110 Datasheet ...

Page 3

... PCI Configuration Write........................................................................3–5 3.1.14 PCI Configuration Read .......................................................................3–5 3.1.15 PCI Special Cycle.................................................................................3–5 3.1.16 PCI IACK Read ....................................................................................3–5 3.1.17 X-Bus Write ..........................................................................................3–5 3.1.18 X-Bus Read ..........................................................................................3–6 3.1.19 Outbound Write Flush ..........................................................................3–6 3.1.20 SA-110 Cache Flush ............................................................................3–6 3.1.21 Reserved Addresses ............................................................................3–6 3.2 PCI Target Transactions ...................................................................................3–6 21285 Core Logic for SA-110 Datasheet iii ...

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... Read Data Parity Error .......................................................... 3–22 3.4.2.5 Target Abort on Read............................................................ 3–22 4 SDRAM and ROM Operation ......................................................................................... 4–1 4.1 SDRAM Control................................................................................................. 4–1 4.1.1 SDRAM Addresses .............................................................................. 4–2 4.1.2 Commands ........................................................................................... 4–3 4.1.3 Parity .................................................................................................... 4–4 4.2 ROM Control ..................................................................................................... 4–5 4.2.1 Addressing ........................................................................................... 4– Address .......................................................................... 3– Address .......................................................................... 3–11 2 21285 Core Logic for SA-110 Datasheet ...

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... UARTDR—Offset 160h ......................................................................6–14 6.6.2 RXSTAT—Offset 164h .......................................................................6–15 6.6.3 H_UBRLCR—Offset 168h ..................................................................6–16 6.6.4 M_UBRLCR—Offset 16Ch .................................................................6–17 6.6.5 L_UBRLCR—Offset 170h ..................................................................6–17 6.6.6 UARTCON-Offset 174h ......................................................................6–18 6.6.7 UARTFLG—Offset 178h ....................................................................6–18 21285 Core Logic for SA-110 Datasheet O Inbound FIFO Operation ................................................................6–9 O Outbound FIFO Operation .............................................................6–9 v ...

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... CSR Base Address Mask Register—Offset F8h ................................ 7– Inbound FIFO Register—Offset 40h ............................................ 7–16 O Inbound FIFO .................................................. 7– Inbound FIFO...................................................... 7– Outbound FIFO Register—Offset 44h ......................................... 7–17 O Outbound FIFO................................................ 7– Outbound FIFO.................................................. 7–17 2 21285 Core Logic for SA-110 Datasheet ...

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... AC Timing Specifications ..................................................................................9–3 9.4.1 PCI Clock Timing Specifications ..........................................................9–3 21285 Core Logic for SA-110 Datasheet O Inbound Free_List Head Pointer Register—Offset 120h .............7–34 O Inbound Post_List Tail Pointer Register—Offset 124h ................7–34 O Outbound Post_List Head Pointer Register—Offset 128h ...........7–34 O Outbound Free_List Tail Pointer Register—Offset 12Ch .............7–35 O Inbound Free_List Count Register— ...

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... PCI Signal Timing Specifications ......................................................... 9–4 9.4.3 PCI Reset Timing Specifications .......................................................... 9–5 9.4.4 JTAG Timing Specifications ................................................................. 9–6 9.5 Memory and SA-110 Interface Timing .............................................................. 9–6 9.5.1 SA-110, 21285, and SDRAM Clock Signal Timing Specifications ....... 9–7 9.5.2 SA-110, 21285, and SDRAM Interface Timing Specifications ............. 9–8 10 Mechanical Specifications............................................................................................ 10–1 Support, Products, and Documentation ..............................................................................- Figures 1-1 21285 Host Bridge Application Diagram ........................................................... 1– ...

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... PCI Signal Timing AC Parameters ....................................................................9–5 9-7 PCI Reset Timing Specifications .......................................................................9–5 9-8 JTAG Timing Specifications ..............................................................................9–6 9-9 SA-110, 21285, and SDRAM Clock Signal AC Parameters..............................9–7 9-10 Memory and SA-110 AC Parameters................................................................9–9 10-1 256 Plastic Ball Grid Array (PBGA) Package Dimensions ..............................10–2 21285 Core Logic for SA-110 Datasheet ...

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...

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... Intelprocessor. It configures all PCI peripherals in the system. • Attached processor. In this configuration, the SA-110 processor system interfaces directly to the host system PCI bus. The 21285 is configured by the host processor in the system. • Intelligent add-in card. In this configuration, the SA-110 processor controls a PCI-based subsystem that is designed to be plugged into a host system PCI slot ...

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... Provides an IEEE standard 1149.1 JTAG interface 1.1.1 Power Management The 21285 REV_ID 4 or higher provides support to enable applications to be compliant with the PCI Bus Power Management Interface Specification. Specifically, the required configuration registers are provided in the 21285 along with an interrupt to the SA-110 processor, indicating that the registers have been written by the host processor ...

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... Host CPU configures all PCI devices. Subsystem appears as a PCI device. • PCI devices on add-in card are private to SA-110. Figure 1-3. Intelligent Add-In Card Application Diagram Add-In Card SDRAM/ ROM 21285 SA-110 21285 Core Logic for SA-110 Datasheet PCI PCI Device Device 21285 PCI Bus PCI PCI ...

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...

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... Signal Description The 21285 signals are categorized into one of several groups: PCI, SA-110, ROM, SDRAM, serial port, miscellaneous, X-Bus/Arbiter, and JTAG. Table 2-1 defines the PCI and SA-110 signal-type abbreviations used in the signal tables. These abbreviations use the same conventions and descriptions as found in the PCI Local Bus Specification, Revision 2 ...

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... I Grant. gnt_l from the PCI arbiter (either external or internal), indicates that the 21285 can take control of the PCI bus. If the 21285 does not have any transactions the PCI when gnt_l is asserted, it parks the PCI bus PCI interrupt ...

Page 17

... The timing of the SA-110 signals is referenced to the MCLK. signals that are connected to the 21285. connected to the 21285 and must be forced state. The SA-110 must be configured for little endian mode. The 21285 does not support big endian mode. Table 2-3. SA-110 Signals Connected to the 21285 ...

Page 18

... SA-110 bus cycles. Address bus enable. ABE is deasserted by the 21285 to tristate A[31: can access SDRAM and ROM. Data bus enable. DBE is deasserted by the 21285 to tristate D[31: can access SDRAM and ROM. Interrupt request. nIRQ is asserted when one or more of the interrupt sources is active, unmasked, and directed to normal interrupt ...

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... ROM write enable. This signal allows data to be stored in a flash ROM. ROM output enable. This signal allows the ROM to output data. Two low address bits of ROM. Table 4-4 ROM chip enable. Chip enable is asserted by the 21285 during ROM accesses. Description Memory addresses. ma[12:0] provides multiplexed row and column addresses to the SDRAMs ...

Page 20

... This occurs because buffers such as 74LVT16244A contain internal bus hold circuitry on their input pins that will force an input high or low if it attempts to float. The pull-up resistor internal to the 21285 is unable to supply enough current to overcome the hysterisis in the bus hold circuitry. In this case, a 4.7 K pull-up or pull-down resistor should be fitted externally on each of the ma[8:2] pins ...

Page 21

... Transmit data from the UART Type Description IC Reference input clock. Supplied by an oscillator and buffered to create MCLK, sdclk, and fclk. OCZ Clock output for 21285. fclk is an internally buffered version of osc and must be connected on the circuit board to fclk_in Signal Description (Figure 2-1). 2-7 ...

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... The configuration is determined by the value latched on ma[7] at reset. 2-8 Type Description IC Clock input for 21285. fclk_in must be connected on the circuit board to fclk (Figure 2-1). The etch length of the connection should be matched to the etch length of MCLK to the SA-110 and sdclk to the SDRAMs to minimize skew. ...

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... X-Bus read strobe. Asserted by the 21285 to enable the X-Bus peripheral to drive read data. X-Bus write strobe. Asserted by the 21285 to enable the X-Bus peripheral to accept write data. X-Bus chip selects. As outputs, xcs_l[2:0] are used as chip selects asserted by the 21285 during writes or reads to X-Bus devices. For information on address ranges, see Table 5-1. ...

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... See of the PCI arbiter operation. Table 2-11 describes the PCI arbiter signals. Note: When the internal arbiter is selected, the req_l pin is the arbiter grant to the 21285 and must be connected to gnt_l external to the 21285. Table 2-11. PCI Arbiter Signals Signal Name ...

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... O dqm O cs_l O d_wren_l O parity O sdclk fclk O rom_ce_l O pci_gnt_l[3] TS xd_wren_l TS 21285 Core Logic for SA-110 Datasheet Signal Description (Sheet Value (if O) 00000000h 0h 0 — — — — — — — — — — Undefined — Asserted (h) Deasserted (l) Undefined Undefined — ...

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... TS tdo O 2.10 Pin Assignment This section describes the 21285 pin assignment and lists the pins according to location (numeric) and in alphabetic order. Figure 2-2 shows the 21285 256-point ball grid array, representing the pins in vertical rows labeled alphabetically, and horizontal rows labeled numerically. Table 2-14 ...

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... Pins Listed in Numeric Order Table 2-14 lists the 21285 pins in order of location (numeric), showing the location code, name, and signal type of each pin. Figure 2-2 provides the map for identifying the pin location codes, listed in alphabetic order in the PBGA Location column in Table 2-1 defines the signal-type abbreviations used in the Type column in Table 2-14 ...

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... Signal Description Table 2-14. 21285 PBGA Location Pin List PBGA Pin Name Location C19 MCLK D1 Vss D3 ma[12] D5 D[2] D7 Vss D9 parity[1] D11 Vdd D13 Vss D15 Vdd D17 Vss D19 osc E1 ma[7] E3 ma[9] E17 Vdd E19 nRW F1 ma[4] F3 ma[6] F17 Vdd F19 A[0] G1 ma[2] G3 ma[3] G17 MAS[0] G19 ...

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... Table 2-14. 21285 PBGA Location Pin List PBGA Pin Name Location L17 Vdd L19 A[14] M1 d_wren_l M3 cmd[1] M17 A[18] M19 A[16] N1 rom_ce_l N3 tdi N17 Vss N19 Vss P1 tdo P3 tck P17 A[26] P19 A[22] R1 trst_l R3 xcs_l[2] R17 Vdd R19 A[25] T1 xior_l T3 tx T17 nRESET T19 A[29] U1 xcs_l[0] U3 pci_rst_l U5 ad[27] U7 idsel ...

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... Signal Description Table 2-14. 21285 PBGA Location Pin List PBGA Pin Name Location V11 Vdd V13 ad[14] V15 ad[8] V17 ad[3] V19 Vio W1 gnt_l W3 ad[31] W5 ad[24] W7 Vss W9 cbe_l[2] W11 Vss W13 ad[15] W15 ad[10] W17 ad[6] W19 Vss Y1 Vdd Y3 ad[26] Y5 cbe_l[3] Y7 ad[20] Y9 frame_l Y11 Vdd Y13 cbe_l[1] Y15 Vss ...

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... Pins Listed in Alphabetic Order Table 2-15 lists the 21285 pins in alphabetic order, showing the name, location code, and signal type of each pin. Figure 2-2 provides the map for identifying the pin location codes. Table 2-1 defines the signal-type abbreviations used in the Type column in Table 2-15. 21285 Pin Name Pin List ...

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... Signal Description Table 2-15. 21285 Pin Name Pin List Pin Name ad[27] ad[28] ad[29] ad[30] ad[31] ba[0] ba[1] cbe_l[0] cbe_l[1] cbe_l[2] cbe_l[3] CLF cmd[0] cmd[1] cmd[2] cs_l[0] cs_l[1] cs_l[2] cs_l[3] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] D[16] D[17] 2-18 PBGA Type Pin Name Location U5 TS D[18 D[19 D[20 D[21 D[22] D2 ICOCZ D[23] B1 ICOCZ D[24] Y17 TS D[25] Y13 TS D[26 D[27 D[28] E18 IC D[29] M4 OCZ ...

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... Table 2-15. 21285 Pin Name Pin List Pin Name ma[5] ma[6] ma[7] ma[8] ma[9] ma[10] ma[11] ma[12] MAS[0] MAS[1] MCLK nFIQ nIRQ nMREQ nRESET nRW osc par parity[0] parity[1] parity[2] parity[3] pci_cfn pci_clk pci_gnt_l[0] pci_irq_l pci_req_l[3] pci_rst_l perr_l req_l rom_ce_l rx scan_en sdclk[0] sdclk[1] sdclk[2] sdclk[3] 21285 Core Logic for SA-110 Datasheet ...

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... Signal Description Table 2-15. 21285 Pin Name Pin List Pin Name Vdd Vdd Vdd Vdd Vio Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss 2-20 PBGA Type Pin Name Location Y1 P Vss ...

Page 35

... The 21285 controls the SA-110 clock, MCLK, by stretching the high time to stall the SA-110 during bus cycles (indicated by assertion of nMREQ by SA-110). The number of cycles that MCLK stays high may be different for each address space and depends upon other 21285 activity at the time nMREQ asserts. ...

Page 36

... SDRAM vendors recommend that the dqm signals into the SDRAMs be forced high at reset, and held high until an all-banks precharge command is issued to the array. The 21285 complies with this recommendation by forcing the dqm signals high at reset, and holding them high until four all-bank precharge commands have been issued (the internal logic that counts these commands increments on all-banks precharge, mode register set, and refresh commands) ...

Page 37

... The SA-110 is stalled while the ROM is written. The ROM write data must be placed on the proper byte lanes by software running on the SA-110, that is, the data is not aligned in hardware by the 21285. Only one write is done regardless of the ROM width. When the ROM write completes, the 21285 unstalls the SA-110. ...

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... If there is no room in the FIFO, the SA-110 stalls until room is created by the unloading of some data to PCI. Data with ascending addresses is placed in the Outbound FIFO in such a way written to PCI in a burst. In order to maximize the burst size, the 21285 does not attempt to unload the Outbound FIFO until one or more of the following conditions occur: • ...

Page 39

... No prefetching on PCI occurs during a PCI IACK read. 3.1.17 X-Bus Write The SA-110 is stalled while the 21285 performs the write to the X-Bus device. The SA-110 address and write data are driven to the X-Bus through transceivers. The SA-110 becomes unstalled when the write is complete. ...

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... SDRAM base address mask, prior to the host configuration code being able to read them. The command register memory space enable bit ([1]) must be set for the 21285 to respond to any memory transaction. The command register I/O space enable bit ([0]) must be set for the 21285 to respond to any I/O transaction. 3-6 ...

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... PCI command is either a memory write or a memory write and invalidate. The PCI memory write data is collected in the Inbound FIFO and written to SDRAM at a later time. The 21285 requests the SDRAM at the end of each eight Dword boundary of the PCI burst (or at the end of the burst). ...

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... PCI. If the byte enable is not asserted, then the corresponding dqm signal is not asserted. If fewer than five Dwords are available in the Inbound FIFO at the start of the write, the 21285 signals retry to the PCI master. If the Inbound FIFO fills during the write, the 21285 signals target disconnect to the PCI master ...

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... FFFh), and the command is either a memory read, memory read line, or memory read multiple. The read is completed as a PCI delayed read. On the first occurrence of the read, the 21285 signals a retry to the PCI master. If the delayed read latch is not full, the 21285 latches the address and command, and places it into the Inbound FIFO. ...

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... PCI address bits [7:2]. The PCI byte enables determine which bytes are written nonexistent CSR is selected within the CSR address range, the data is discarded and no error action is taken. If the PCI master attempts burst longer than one data phase, the 21285 target disconnects. 3.2.5 Type 0 Configuration Read PCI configuration read to the CSR occurs when idsel is asserted, the PCI command is a configuration read, and the PCI address bits [1:0] are 00 ...

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... If the PCI master attempts burst longer than one data phase, the 21285 target disconnects. Write data is discarded if the PCI address matches the CSR I/O base address register (see Section 7 ...

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... In other words, the new read does not displace the in-progress read. If the PCI address matches the CSR I/O base address register (see command is an I/O read, and the register offset is either 40h or 44h. The 21285 returns 0 for read data. For more information about CSR and I 3 ...

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... When the address reaches the head of the FIFO, the 21285 reads the ROM. The ROM is read from one to four times, depending on the ROM width setting in the SA-110 control register, and the data is collected and packed. See which the ROM read address is derived from the PCI address. ...

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... Dword. • If the 21285 receives a master abort, it discards all of the write data from that transaction and sets the status register received master abort bit [29], which, if enabled, interrupts the SA-110. • ...

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... If the 21285 receives a master abort, it substitutes FFFFFFFFh for the read data and sets the status register received master abort bit [29], which, if enabled, interrupts the SA-110. • If the 21285 receives a target abort, it sets the status register received target abort bit [28], which, if enabled, interrupts the SA-110. 21285 Core Logic for SA-110 Datasheet ...

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... Dwords beyond the first Dword are optional. If the target disconnects after delivering the first Dword, the 21285 does not resume the read at that time (for a DMA originated read, it resumes at the address of the next unread Dword after the normal channel interburst delay). For an SA-110 read, all Dwords that have been read are eligible to be delivered to the SA-110 as prefetched read data ...

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... If the 21285 receives a target retry response, it repeats the I/O read command at the first opportunity. • If the 21285 receives a master abort, it substitutes FFFFFFFFh for the read data and sets the status register received master abort bit [29], which, if enabled, interrupts the SA-110. • If the 21285 receives a target abort, it substitutes FFFFFFFFh for the read data and sets the status register received target abort bit [28], which, if enabled, interrupts the SA-110 ...

Page 52

... If the 21285 receives a master abort, it discards the write data and sets the status register received master abort bit [29], which, if enabled, interrupts the SA-110. • If the 21285 receives a target abort, it discards the write data and sets the status register received target abort bit [28], which, if enabled, interrupts the SA-110. 3-18 ...

Page 53

... PCI Request Operation The 21285 asserts req_l to act as bus master on the PCI for SA-110 and DMA originated transactions. It deasserts req_l for two cycles when it receives a retry or disconnect response from the target. However, if gnt_l is asserted, the 21285 can start a PCI transaction regardless of the state of req_l ...

Page 54

... Master Latency Timer When the 21285 begins a PCI transaction as master, asserting frame_l, it begins decrementing its master latency timer. When the timer value reaches zero, the 21285 checks the value of gnt_l. If gnt_l is deasserted, the 21285 deasserts frame_l ( still asserted) at the earliest opportunity. ...

Page 55

... Write Data Parity Error A write data parity error is detected when the par that is received by the 21285 does not match the expected parity for data and byte enables. This causes the following actions to occur: • The status register detected parity error bit [31] is set. ...

Page 56

... Read Data Parity Error A read data parity error is detected when the par that is received by the 21285 does not match the expected parity for data and byte enables. This causes the following actions to occur: • The status register detected parity error bit [31] is set. ...

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... This chapter describes the operation of the SDRAM and ROM. 4.1 SDRAM Control The SDRAM controller on the 21285 controls from one to four arrays of synchronous DRAMs (SDRAMs). SDRAM supported parts include: 8Mb, 16Mb, and 64Mb. All SDRAMs share command and address bits, but have separate clock and chip select bits (see Figure 4-1) ...

Page 58

... Memory reads and writes are done in bursts of four Dwords. For a read that requires less than four Dwords (for example, a memory read from PCI), the 21285 discards the unused data. For a write that requires less than four Dwords, the 21285 uses the dqm pins to inhibit writing to some Dwords ...

Page 59

... Note: “—” in Table 4-2 indicates that the address is not used by the SDRAM in this configuration. The pin is driven by the 21285 and its value can be either Note: “ap” in Table 4-2 indicates the autoprecharge bit that is used by the SDRAM during column address time. A low (deasserted), indicates no autoprecharge, which occurs during read and write commands when there is another burst pending to the same page ...

Page 60

... During a write from the SA-110, the operation depends on bit [13] of the SDRAM timing register. • data is received by the 21285 and flows through an internal parity generator onto parity. Therefore necessary to run a parity-enabled memory subsystem slower than a comparable parity-disabled memory to allow for the parity computation. ...

Page 61

... Figure 4-2 shows the ROM configuration. The ROM output enable and write enable are connected to address bits [30:31] respectively. The ROM address is connected to address bits [24:2]. Figure 4-2. ROM Configuration SA-110 This section describes the following aspects of the 21285 ROM interface: • Addressing • Reads • ...

Page 62

... ROM Width Byte Word (2 bytes) Dword (4 bytes) During ROM accesses from the SA-110, the 21285 latches the address and drives it back onto A. Table 4-5 shows how the ROM address is derived from the SA-110 address. Table 4-5. ROM Address Generation for SA-110 Accesses Bits ...

Page 63

... Latches and packs the ROM data read from D[15:0] internally For reads from a Dword-wide ROM, the 21285 latches the data from D[31:0]. If the read is from the SA-110, the 21285 drives the packed data back onto D[31:0]. If the read is from the PCI, the data is sent back to the PCI. ...

Page 64

... Blank ROM Programming The 21285 has a mode that allows programming of blank Flash ROMs in place on a circuit board. This mode is enabled if both ma[6] and pci_cfn are 0 when the 21285 is reset. When this mode is enabled: • nRESET is asserted by the 21285 to keep the SA-110 in reset state. (This is necessary since there may be no code in the ROM yet.) • ...

Page 65

... CSR. Bits [19:12] are ignored. Reserved space should not be used by SA-110 software. Accidental accesses to reserved space will not cause the 21285 bus interface to hang, however, because the reserved address can alias to another valid address, a write can change the state of a SDRAM, a CSR, and so on. ...

Page 66

... FFFFh 16MB 7900 0000h 79FF FFFFh 16MB 7A00 0000h 7AFF FFFFh 16MB 7B00 0000h 7BFF FFFFh 16MB 7C00 0000h 7C00 FFFFh 64KB 7C01 0000h 7FFF FFFFh — 8000 0000h FFFF FFFFh 2GB 21285 Core Logic for SA-110 Datasheet ...

Page 67

... When a DMA and Inbound FIFO operation are both outstanding, priority alternates between DMA and the Inbound FIFO. 5.2 X-Bus Interface The X-Bus interface allows low-performance 8-, 16-, and 32-bit peripherals with ISA-bus-like interfaces to be attached to the SA-110 side of the 21285. Typical devices that can be attached include: • Super I/O controller • ...

Page 68

... A standard 74LVT24S part can be used for the data transceiver. The behavior of xd_wren_l has been designed so that during a 21285 write, the transceiver’s T/nR pin will be low. Therefore, the transceiver B port should connect to the SA-110/21285 and the A port should connect to the X-Bus devices ...

Page 69

... The strobe will be asserted after four cycles and will remain asserted for seven cycles. The access will continue for an additional seven cycles. 21285 Core Logic for SA-110 Datasheet SA-110 Operation Figure 5-2 5-5 ...

Page 70

... D (write) X-Bus Device Data (Read) On reads, the X-Bus device drives read data to the SA-110, and the 21285 unstalls the SA-110 after the cycle count has expired. On writes, the SA-110 drives write data to the X-Bus device, and the 21285 unstalls the SA-110 after the cycle count has expired ...

Page 71

... An SA-110 write to PCI if the Outbound FIFO is full To break the deadlock, the 21285 must be able to write data to SDRAM and/or ROM while the SA- 110 is stalled so, the 21285 deasserts both the address and data bus enables (ABE and DBE) to the SA-110. Any PCI writes that get posted after the SA-110 access has started, as well as those that had been posted prior to it, may need to be done ...

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...

Page 73

... Serial port 6.1 PCI Bus Arbiter The 21285 contains a PCI bus arbiter that supports four external masters in addition to the 21285. In order to enable the arbiter, ma[7] must reset. The arbiter and X-Bus cannot both be used at the same time since they share I/O pins. ...

Page 74

... Low-Priority Group Arbiter Control Register = 0011b Each bus master, including the 21285, can be configured either the low-priority group or the high-priority group as determined by the value of the corresponding priority bit in the arbiter control register. Each master has a corresponding bit. If the bit the master is assigned to the high-priority group ...

Page 75

... The fourth Dword of the descriptor is the value of the upper 32 bits of the PCI address for the current transfer (that is, pertaining to the descriptor currently being fetched from memory) and is loaded into the Channel n DAC register. Note that this is the case 21285 Core Logic for SA-110 Datasheet Byte Count, Direction, End of Chain PCI Bus Address ...

Page 76

... After each write, the destination address is incremented by the number of bytes written. On the initial write, some low-order bytes can be masked based on the low two bits of the destination address as described in that it is Dword aligned. 6-4 Table 6-1. After the first write, the destination address is incremented so 21285 Core Logic for SA-110 Datasheet ...

Page 77

... Destination is SDRAM for PCI-to-SDRAM transfers, and PCI for SDRAM-to-PCI transfers. The 21285 may need to realign the data depending on the initial source and destination addresses. The data in each byte lane is rotated right or left byte lanes as described in Table 6-3 ...

Page 78

... For a PCI-to-SDRAM transfer, the channel enqueues a read request to the PCI (in the Outbound FIFO) when the PCI interburst delay for the channel has elapsed. The 21285 attempts to read the number of Dwords specified by the read length bit [15] of the channel control register (or the number of Dwords remaining in the transfer, if that is smaller). If the target disconnects before that number of Dwords has been read, the 21285 waits for the PCI interburst delay before starting another read ...

Page 79

... I O Message Unit 2 This section describes the operation of the 21285 I of this specification describe the I The message unit provides a standardized message-passing mechanism between a host and a local processor (the SA-110 is the local processor). It provides a means for the host to read and write lists over the PCI bus at offsets of 40h and 44h from the first base address. ...

Page 80

... The FIFOs are used to hold message frame addresses (MFAs). The MFAs are offsets (pointers) to the message frames. The 21285 does not interpret the MFA values other than to recognize the special indicator for an invalid MFA (which is FFFFFFFFh), nor does it access the message frames. ...

Page 81

... When it needs to send a request message, the host processor removes an MFA from the head of the inbound free_list (via a read over the PCI bus to the 21285 register offset 40h). 2. The host processor writes the request message to the MFA in SA-110 memory (via writes over the PCI to SA-110 SDRAM) ...

Page 82

... The SA-110 places the MFA onto the tail of the outbound post_list. The SA-110 must also do a write to the outbound post_list count register to increment the number of entries. The 21285 asserts pci_irq_l when the value in the outbound post_list count register is not zero (if not masked by outbound interrupt mask register) ...

Page 83

... SA-110 software clearing bit [9] in the SA-110 control register). When pci_cfn is asserted, nRESET is normally an input driven by the power-on reset circuitry on the board, but in this case, it must be driven by the 21285. So, to use the watchdog timer, the power-on circuitry must drive nRESET with an open-drain driver on the board ...

Page 84

... A periodic process (based on one of the other timers) would write to Timer4Load. If that process ever fails to write to Timer4Load within the countdown time, then both the SA-110 and the 21285 reset. Once the watchdog enable bit is set, it can only be cleared by a chip reset. ...

Page 85

... Baud Rate Generation The baud rate is derived by dividing down the 21285 clock (fclk_in). The signal fclk_in is divided by four and used as the reference clock. That clock is first divided by a programmable number between 1 and 1024, and then by a fixed value of 16. The receive/transmit baud clock is synchronized with the data stream each time a transition is detected on the receive data line ...

Page 86

... FIFO is accessed. Write data is placed in the FIFO. After a write, the data is automatically transferred down to the next location of the transmit FIFO. For data sizes other than eight bits, the upper bits of this field are zero extended. R Read only as 0. 21285 Core Logic for SA-110 Datasheet ...

Page 87

... Overrun error 31:3 — Note: The received data must be read first (UARTDR) followed by the status error associated with the data (RXSTAT). This read sequence cannot be reversed. 21285 Core Logic for SA-110 Datasheet R/W Description R This bit is set if a framing error (FE) occurred. R This bit is set if a parity error (PER) occurred. ...

Page 88

... Specifies the UART data length as follows bits bits bits bits When this field is programmed to be less than eight bits, the data is right justified in the FIFO, and the unused bits are zero filled. R Read only as 0. 21285 Core Logic for SA-110 Datasheet ...

Page 89

... In order to internally update the contents of M_UBRLCR or L_UBRLCR, an H_UBRLCR write must always be performed at the end. The three registers must be updated with the following sequence: • L_UBRLCR write, M_UBRLCR write, and H_UBRLCR write UARTCON—Offset 174h 21285 Core Logic for SA-110 Datasheet Section 6.5.4 R/W Description ...

Page 90

... The transmitter busy flag (TBY read-only bit that is set when the transmitter is actively processing data for transmission, and is cleared when the transmitter is idle or the UART is disabled (UE=0). R When 1: No characters available. When 0: One or more characters available. R When 1: Busy. When 0: Ready to accept a character. R Read only as 0. 21285 Core Logic for SA-110 Datasheet ...

Page 91

... They are also accessible from the SA-110 (offset is from address 4200 0000h). shows the allowable access to each register. Table 7-1. Register Access Abbreviation R R/W W1C W0C W1S WO 21285 Core Logic for SA-110 Datasheet Definition Read only. Writes have no effect. Read/write. Read. Write 1 to clear. Write zero to clear. Read. Write 1 to set. Write only. 7 Table 7-1 ...

Page 92

... Internally hardwired to be 1011h. R/W Description R Identifies this device as the 21285. Internally hardwired to be 1065h. 0 Offset 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 4Ch – 69h 70h 74h 21285 Core Logic for SA-110 Datasheet ...

Page 93

... Parity error response 21285 Core Logic for SA-110 Datasheet R/W Description R/W When 0: The 21285 does not respond to PCI I/O transactions as a target. When 1: The 21285 response to I/O transactions for CSR accesses when the address matches the CSR I/O base address register. Reset value: 0. R/W When 0: The 21285 does not respond to PCI memory transactions as a target ...

Page 94

... Reserved 7-4 R/W Description R Reads indicate that the 21285 does not perform address or data stepping. R/W Controls the enable for serr_l. When 0: Signal serr_l cannot be driven by the 21285. When 1: Signal serr_l can be driven low by the 21285 under the conditions described in Section Reset value: 0 ...

Page 95

... R Reads indicate that the 21285 never signals target abort as a target. W1C This bit is set to 1 when the 21285 is the master of a transaction that terminates with a target abort. Reset value: 0. W1C This bit is set to 1 when the 21285 is the master of a transaction (except for special cycles) that terminates with a master abort ...

Page 96

... Reset value: 0. R/W Description R/W Indicates the value of the latency timer, which limits the length of a burst that the 21285 performs as master when its bus grant is removed. Reset value: 0. R/W Description R Reads as 0 indicating a header type of zero. ...

Page 97

... R/W Description R/W The SA-110 can write to this field to indicate to a host that it provides BIST. The 21285 does not interpret or set this field, however, bit [30] (bit [6] of the BIST field that the host processor uses to invoke BIST) can be enabled to interrupt the SA-110. Reset value: 0. ...

Page 98

... CSR I/O Base Address Register—Offset 14h Dword Bit Name 6:0 CSR address space 31:7 CSR base address 7-8 R/W Description R Reads indicate that the CSRs require 128 bytes of I/O address space. R/W Contains the base address of the CSRs. Reset value: 0. 21285 Core Logic for SA-110 Datasheet ...

Page 99

... Lower 31:28 SDRAM base address, Upper 7.1.14 CardBus CIS Pointer Register—Offset 28h The CardBus CIS pointer register is not used read as 0. 21285 Core Logic for SA-110 Datasheet Section 7.3.9. R/W Description R If bit [31] of the SDRAM base address mask register is 0, this field is read as 8, indicating that the SDRAM must be mapped to PCI memory space, may be located anywhere in 32-bit PCI address space, and is prefetchable ...

Page 100

... Reset value: 0. R/W Read/write or read-only 0 as determined by bit [31] in the expansion ROM base address mask register. Reset value: 0. R/W Description R Indicates the offset in configuration space of the first new capability; in this case, Power Management. Value: 70h. R Reset value: 0. 21285 Core Logic for SA-110 Datasheet ...

Page 101

... R/W Description R/W from SA- The SA-110 sets this field according to the routing of 110, pci_irq_l. Usually, pci_irq_l is routed to INTA# and R from PCI this field is programmed with a value of 1. The 21285 does not interpret or set this field. Reset value Read only as 0. R/W Description R/W from SA- The 21285 does not interpret or set this field ...

Page 102

... The PMC register is used to indicate to system software which power management features are supported. In the 21285, this register is Read/Write from the SA-110 and Read-Only from the PCI. This enables the SA-110 firmware to determine exactly what features of the PCI Power Management Interface Specification are supported. The field names from this specification are listed here for reference ...

Page 103

... SA-110. A write by the SA-110 to this register clears this status bit. The field names from the PCI Power Management Interface Specification are listed here for reference; however, only the Power State field, PME_Status, and PME_En are used by the 21285 (other than for register reads and writes). ...

Page 104

... Registers 2. The 21285 asserts Pre_PME due to the SA-110 setting the PME_Status bit (assuming that PME_En is set). 3. System software, in response to PME#, writes Power State from D3 to D0. This causes the 21285 to assert nRESET, which clears all registers, including PMCSR, and resets the SA-110. ...

Page 105

... Table 7-3 lists the PCI control and status registers. Table 7-3. PCI Control and Status Registers 31 7.2.1 Outbound Interrupt Status Register—Offset 30h The outbound interrupt status register indicates the reasons why the 21285 is asserting pci_irq_l. Dword Bit Name 1:0 — 2 Doorbell interrupt 3 Outbound post list ...

Page 106

... Registers 7.2.2 Outbound Interrupt Mask Register—Offset 34h The outbound interrupt mask register is used to allow the host processor to disable the 21285 from asserting pci_irq_l. Dword Bit Name 1:0 — 2 Doorbell interrupt mask 3 Outbound post list interrupt mask 31:4 — 7.2 Inbound FIFO Register—Offset 40h ...

Page 107

... When the I O Outbound FIFO is read from PCI (from CSR memory base address—offset 44h), the 2 21285 reads the SDRAM using the value in the outbound post_list head pointer register as the address. • If the outbound post_list count register is not equal to 0, then it: a ...

Page 108

... ROMs, since neither the SA-110 or PCI can put the data on the low-byte lane(s) and simultaneously place the correct byte (word) address on the two low-order address bits. Reset value: Undefined. R Read only as 0. 21285 Core Logic for SA-110 Datasheet SA-110 to host ...

Page 109

... Inbound free_list head pointer (I Inbound post_list tail pointer (I Outbound post_list head pointer (I Outbound free_list tail pointer (I Inbound free_list count (I Outbound post_list count (I Inbound post_list count (I SA-110 control 21285 Core Logic for SA-110 Datasheet Offset 80h 84h 88h 8Ch 90h 94h 98h to 9Ch ...

Page 110

... Core Logic for SA-110 Datasheet ...

Page 111

... The DMA channel n byte count register ( contains the following fields. Dword Bit Name 23:0 Byte count 29:24 Channel interburst delay 30 Channel transfer direction 31 End of chain 21285 Core Logic for SA-110 Datasheet (Sheet Offset 32Ch 330h to 33Ch 340h 344h 348h 34Ch 350h to 35Ch 360h 364h 368h ...

Page 112

... DAC address, which can Next descriptor 1 = DAC address When the channel initial descriptor in register bit [4] of the Channel Control Register is set, the software writes 0 to this bit. Reset value: 0 Reserved. 21285 Core Logic for SA-110 Datasheet ...

Page 113

... Table 7-5 lists the format of the descriptor block in memory. Table 7-5. Descriptor Block Format Offset from Descriptor Pointer 21285 Core Logic for SA-110 Datasheet Descriptor Pointer Register—Offset n R/W Description R Read only as 0. R/W Contains the address of the next descriptor in SDRAM. Reset value: Undefined. ...

Page 114

... SDRAM, that is, reads are from the PCI bus. It defines the command type that should be used during the PCI reads. • 00=Memory read • 01=Memory read line • 10=Memory read multiple • 11=Memory read multiple Reset value: Undefined. 21285 Core Logic for SA-110 Datasheet (Sheet ...

Page 115

... Reset value: Undefined. R Read only as 0. R/W This field defines the number of Dwords that the 21285 attempts to read per burst from the PCI during PCI-to- SDRAM transfers (during the beginning or end of a transfer the number may be less). • 0=8 Dwords • 1=16 Dwords Reset value: Undefined ...

Page 116

... When 0: Causes the corresponding bit in the CSR memory base address register to act as a read/write bit. Reset value Read only as 0. Value 00000000h 00040000h 000C0000h 001C0000h 003C0000h 007C0000h 00FC0000h 01FC0000h 03FC0000h 07FC0000h 0FFC0000h 21285 Core Logic for SA-110 Datasheet ...

Page 117

... SA-110 control register is set. Dword Bit Name 17:0 — 27:18 Mask 30:28 — 31 SDRAM window disable R/W 21285 Core Logic for SA-110 Datasheet R/W Description R Read only as 0. R/W Each bit of this register is used as a CSR address if the corresponding bit of the CSR base address mask register Reset value Read only as 0 ...

Page 118

... This field contains the upper address bits for PCI- generated SDRAM accesses (see this register is used as a SDRAM address if the corresponding bit of the SDRAM base address mask register Reset value Read only as 0. 21285 Core Logic for SA-110 Datasheet Figure 7-1). Each bit of ...

Page 119

... The expansion ROM base address mask register must be written by the SA-110 before the initialize complete bit [1] in the SA-110 control register is set. Dword Bit Name 19:0 — 23:20 Mask 30:24 — 31 ROM window disable 21285 Core Logic for SA-110 Datasheet SDRAM Address 17 Multiplexer PCI Address ...

Page 120

... ROM base address mask register to enable the different window sizes into ROM. All other values are illegal. Table 7-8. Expansion ROM Window Sizes Window Size 1MB 2MB 4MB 8MB 16MB No window 7-30 Value 00000000h 00100000h 00300000h 00700000h 00F00000h 80F00000h 21285 Core Logic for SA-110 Datasheet ...

Page 121

... RAS-to-CAS delay (T ) rcd 7:6 CAS latency (T 21285 Core Logic for SA-110 Datasheet R/W Description R/W The minimum number of cycles from autoprecharge internally in the SDRAM to the next row activate or auto- refresh command. For reads, autoprecharge is assumed to start four clock cycles after the read command. If the ...

Page 122

... All SDRAMs are refreshed at the same time. Reset value Read only as 0. 21285 Core Logic for SA-110 Datasheet (Sheet will be rc and cs_l is asserted rc Section ...

Page 123

... Note: The 21285 does not detect memory accesses to nonexistent memory locations. The SDRAM sequencer may possibly toggle address and command pins, return unpredictable read data on reads, and discard data on writes ...

Page 124

... Description R Read only as 0. R/W Address inbound post_list tail. 2 Reset value: Undefined. R Read only as 0. R/W Description R Read only as 0. R/W Address outbound post_list head. 2 Reset value: Undefined. R Read only as 0. 21285 Core Logic for SA-110 Datasheet O inbound free_list. O inbound 2 O outbound 2 ...

Page 125

... When a PCI bus master removes an entry from the post_list (via a read to offset 44h), the value is decremented by one. When the value is not equal to 0, the 21285 asserts pci_irq_l (if not masked by the outbound interrupt mask). Dword Bit ...

Page 126

... SDRAM base address mask register • SDRAM base address offset register • Expansion ROM base address mask register When 0: The 21285 returns retry response as the target of PCI configuration cycles, and will not assert devsel_l to the PCI, I/O, or memory commands. When 1: The 21285 returns normal response to PCI configuration cycles ...

Page 127

... FIQEnable registers (see Section Reset value Read only as 0. W0C Set when the discard timer counts to 0 and the 21285 has discarded read data (see Section interrupt to the SA-110 if enabled in the IRQEnable/ FIQEnable registers (see Section To clear this error, software must write this bit. ...

Page 128

... Reset value: 0. R/W Indicates the number of fclk_in cycles to wait from ROM output enable deasserted, until the 21285 allows any other agent, that is; the SA-110, SDRAM, X-Bus, or 21285 to drive D. Exception: a value of 0 means 16 cycles. A value illegal. Reset value: 0. R/W Controls the direction of xcs_l[2:0]. ...

Page 129

... PCI Address 31 Alias Register (offset 20Ch). Dword Bit Name 14:0 — 15 PCI memory space upper address bit 31:16 PCI I/O space upper address field 21285 Core Logic for SA-110 Datasheet O inbound and outbound lists. 2 Number of Entries 256 512 16K 32K ...

Page 130

... When 0: Memory read line command. When 1: Memory read multiple command. Reset value: 0. R/W Determines the maximum number of Dwords that the 21285 attempts to prefetch when there is a match to the prefetchable memory range. • 000=1 Dword • 001=2 Dwords • 010=4 Dwords • 011=8 Dwords • ...

Page 131

... PCI Arbiter 27:24 Interrupt input level 30:28 X-Bus chip select 31 PCI interrupt request 21285 Core Logic for SA-110 Datasheet R/W Description R/W Contains the number of X-Bus cycles for an access to the X-Bus device in xcs_l[0] range. Reset value: 0. R/W Contains the number of X-Bus cycles for an access to the X-Bus device in xcs_l[1] range ...

Page 132

... PCI interrupt request 7-42 R/W Description R/W Indicates which priority group each master is assigned to. 0=Low priority. 1=High priority. Bit [4] controls the 21285 priority; bits [3:0] controls request [3:0] respectively. Reset value: 0. R/W — R Read only Read only as 1. Allows software to determine that the PCI Arbiter is selected. ...

Page 133

... I/O device 1 strobe mask 23:16 I/O device 2 strobe mask 31:24 I/O device n strobe mask 21285 Core Logic for SA-110 Datasheet R/W Description R/W Strobe mask shifted out to xior_l or xiow_l (for read or write respectively) during an access to X-Bus device in xcs_l[0] range. When 1: Strobe asserts. When 0: Strobe deasserts. Reset value: 0. ...

Page 134

... Description R/W Doorbell PCI interrupt causes the assertion of pci_irq_l if enabled in the outbound interrupt mask register. Reset value: 0. R/W Description R/W Doorbell SA-110 interrupt causes the assertion of nIRQ or nFIQ if enabled in the IRQEnable or FIQEnable registers (see Section 7.3.31). Reset value: 0. 21285 Core Logic for SA-110 Datasheet Figure 7-2 ...

Page 135

... Table 7-11. Interrupt Source Bits Bits Interrupt Source 0 Reserved 1 Soft interrupt 2 Console RX 3 Console TX 21285 Core Logic for SA-110 Datasheet FIQEnable Register To nIRQ To nFIQ Read IRQStatus IRQRawStatus IRQEnable — — FIQStatus ...

Page 136

... W1C bit in PCI status register W1C bit in PCI status register R/W Description bit position indicates that the associated interrupt source is both active and enabled. The nIRQ/nFIQ output pin is the NOR of all of the bits in this register. 21285 Core Logic for SA-110 Datasheet (Sheet ...

Page 137

... IRQEnableClear/FIQEnableClear Register—Offset 18Ch/28Ch This write-only register is used to clear bits in the IRQEnable/FIQEnable register. Dword Bit Name 31:0 IRQEnableClear/ FIQEnableClear 21285 Core Logic for SA-110 Datasheet R/W Description bit position indicates that the associated interrupt source is active. R/W Description indicates that the associated interrupt source is enabled and allows an interrupt request ...

Page 138

... Don’t care. WO This bit generates bit [1] (as either the RawStatus register (and its current state can be found by reading that register). — Don’t care. R/W Description R/W Provide bits 63:32 of the PCI address. Reset value: 0 21285 Core Logic for SA-110 Datasheet ...

Page 139

... PCI memory space. Dword Bit Name 31:3 — 2 PCI Address 31 1:0 — 21285 Core Logic for SA-110 Datasheet R/W Description R R/W Specifies if a DAC read should prefetch. When 0: PCI command is Memory Read and 1 Dword is read. When 1: PCI command is specified by DAC Read Command field of this register. ...

Page 140

... R/W Description R/W The act of writing to this register causes the counter to reload with the initial value. Reset value Read only as 0. R/W Description R Contains the current counter value. Reset value: Undefined. 21285 Core Logic for SA-110 Datasheet ...

Page 141

... Any write to the TimerNClear register (any data) clears the associated interrupt. The write has no effect if the associated interrupt was already clear. TimerNClear is a write-only register. Dword Bit Name 31:0 Clear 21285 Core Logic for SA-110 Datasheet R/W Description R Read only as 0. R/W The decodes are: • ...

Page 142

...

Page 143

... JTAG Test Port The 21285 contains a serial scan test port that conforms to IEEE standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. 8.1 Test Access Port Controller The test access port controller is a finite state machine that interprets IEEE 1149.1 protocols received through the tms input ...

Page 144

... Table 8-1 lists the instruction Test Register Operation Selected Boundary-scan External test (the 21285 drives pins using the data in the boundary-scan register). Boundary-scan Samples I/O. Bypass Tristates all output and I/O pins except the tdo pin. Bypass Drives pins from the boundary-scan register and selects the bypass register for shifts ...

Page 145

... The boundary-scan register is a single-shift register-based path formed by boundary-scan cells placed at the chip’s signal pins. The register is accessed through the JTAG ports tdi and tdo pins. A machine-readable boundary-scan index (BSDL.TXT) for each I/O cell in the 21285 design is located at the following URL: http://ftp ...

Page 146

...

Page 147

... PCI Electrical Specification Conformance The 21285 PCI pins conform to the basic set of PCI electrical specifications in the PCI Local Bus Specification,Revision 2.1. See that document for a complete description of the PCI I/O protocol and pin ac specifications. 9.2 Absolute Maximum Ratings The 21285 is specified to operate at a maximum frequency of 33 MHz at a junction temperature (T(j)) not to exceed 125° ...

Page 148

... Electrical Specifications 9.3 DC Specifications Table 9-3 defines the dc parameters met by all 21285 PCI signals under normal operating conditions. Note: In Table 9-3, currents into the chip (chip sinking) are denoted as positive (+) current. Currents from the chip (chip sourcing) are denoted as negative (–) current. Table 9-3. DC Parameters ...

Page 149

... Table 9-4. PCI Clock Signal AC Parameters Symbol Parameter T pci_clk cycle time cyc T pci_clk high time high T pci_clk low time low pci_clk slew rate 21285 Core Logic for SA-110 Datasheet t1 T high T f for 3.3-V clocks cc for 3.3-V clocks cc for 3.3-V clocks cc Minimum ...

Page 150

... PCI signal timing specifications. V test T T inval val Valid off Valid for 3.3-V signals cc FM-05676.AI4 a,b,c a,b,c a,b a,b a,b,c a,b,c a,b Table 9-6 correlates the ac Minimum Maximum Unit — ns — — ns 10, 12 — — ns 21285 Core Logic for SA-110 Datasheet ...

Page 151

... Applies to rising (deasserting) edge only. b. All PCI output drivers are asynchronously floated when pci_rst_l is asserted (except ad, cbe_l, and par, which are driven pci_cfn is asserted). 21285 Core Logic for SA-110 Datasheet Table 9- val ...

Page 152

... All rise/fall AC parameters are measured from 10 measured from 50 fclk_in to 50 signal specified Minimum Maximum Unit 0 10 MHz 45 — — ns — — — — ns — — All other AC parameters are dd 21285 Core Logic for SA-110 Datasheet ...

Page 153

... T MCLK fall time mclkft T fclk to sdclk delay - fclk rising ckosr T fclk to sdclk delay - fclk falling ckosf 21285 Core Logic for SA-110 Datasheet show the SA-110, 21285, and SDRAM clock signal timing specifications. T oscft T ckoof T ckosf T sdclkft T mclkrt T ckomr FM-05930.AI4 ...

Page 154

... This delay is not specified imposed by etch delays in the module design. In the module design, the capacitive load and etch length on the following nets should be matched: 21285 fclk output to 21285 fclk_in; 21285 MCLK output to SA-110 MCLK pin; 21285 sdclk[3:0] outputs to SDRAM CLK pin. ...

Page 155

... SA-110 address in T dqm[3:0] minimum output hold during SA-110 write, dqmh timed from rising fclk_in 21285 Core Logic for SA-110 Datasheet Corresponding Parameter Value T dih , T mrih , T loih , T rwih , T clih, T pih T dqmh, T aih T dis , T mris , T lois , T rwis , T clis, T pis, T dqms, T ais ...

Page 156

... LOCK input setup lois T LOCK input hold loih T nRW input setup rwis T nRW input hold rwih T CLF input setup clis T CLF input hold clih a. For SA-110 writes to 21285, 21285 reads of SDRAM, and 21285 reads of ROM. b. For xcs signals that are configured as outputs. 9-10 Minimum 4.5 4.7 5.0 5.0 5.3 5.1 4.5 4.6 4.5 4.6 5.3 5.1 5.4 5 ...

Page 157

... Mechanical Specifications The 21285 is contained in an industry-standard 256 plastic ball grid array (PBGA) package, as shown in Figure 10-1. Figure 10-1. 256 Plastic Ball Grid Array (PBGA) Package Pin 1 Corner Pin 1 I. Chamfer 4 Places 21285 Core Logic for SA-110 Datasheet ...

Page 158

... The value for this measurement is for reference only. 10-2 Minimum Nominal Maximum Value Value Value a — 1.27 BSC — — 2.15 3.50 0.50 0.60 0.70 — — 2.50 0.60 0.75 0.90 0.10 — 2.50 — — 0.20 — — 0.25 26.80 27.00 27.20 — 24.00 24.70 26.80 27.00 27.20 — 24.00 24.70 b — 1.44 reference — b — 1.44 reference — 21285 Core Logic for SA-110 Datasheet ...

Page 159

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