F65510 Intel Corporation, F65510 Datasheet

no-image

F65510

Manufacturer Part Number
F65510
Description
Controllers, Flat Panel VGA Controller
Manufacturer
Intel Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
F65510A
Manufacturer:
WD
Quantity:
1 831
65510
Flat Panel VGA Controller
P R E L I M I N A R Y
Highly integrated solution and small
form factor flat panel controller
solution
• Integrated 256x18 palette
• Direct support for Dual or Single
• Separate address and data buses
• Single clock source
• 100-pin package
Single 256Kx16 DRAM provides
two-chip VGA subsystem
Memory options are (1) 256Kx16
DRAM or (4) 256Kx4 DRAMs
Mixed 3.3V/5.0V panel, bus and
memory interface capability for low
power operation
Advanced power management fea-
tures minimize power consumption
during panel operation
Dedicated input pin supports mini-
mum power operation in Suspend
and Resume modes
Register programmable 4mA or 8mA
drive on all bus data line (D0-15) and
panel control and data signals
Multiple Bus Interface support for
• High-speed x86 SL PI Bus
• High-speed x86 SX/DX Local Bus
• EISA/ISA (PC/AT) Bus
• Micro Channel (MC) Bus
High performance Linear Accelera-
tion™ drivers for Windows™
acceleration
Scan panel
Supports Dual Panel/Dual Drive
(D/D) and Single Panel/Single Drive
(S/S) LCD, Plasma and El Panels
Generates 64 gray levels of
Monochrome panels
Single clock source with rate multi-
plier function to generate a wide
range of clock frequencies
Optional "clock doubler" func-
tionality
Programmable vertical compensa-
tion techniques increase usable
display area
Intelligent SMARTMAP™ color to
gray scale conversion
Fully compatible with IBM
High performance resulting from
buffered writes (Write Buffer) and
B I O S
R O M
I S A , M C , x 8 6 S L P I o r
x 8 6 S X / D X L o c a l B u s
S i n g l e C l o c k S o u r c e
System Block Diagram
A d d r e s s
D a ta
C o n t r o l
®
VGA
6 5 5 1 0
2 5 6 K x 1 6
D R A M
fast screen updates (internal asyn-
chronous 16-level FIFO)
Text Enhancement feature improves
contrast of text on flat panel displays
Three software selectable RGB color
to gray scale reduction techniques
Full backwards compatibility with
EGA, CGA, MDA and Hercules
graphics standards
Chip pinouts optimized for PCB
layout
Programmable polynomial based
Frame Rage Control gray scale
algorithm supports fast response
"mouse quick" displays by reducing
flicker without increasing panel
vertical refresh rate
16-bit display memory operations
P a n e l C o n t r o l
P a n e l D a t a
T o F la t
P a n e l
D is p la y

Related parts for F65510

F65510 Summary of contents

Page 1

Flat Panel VGA Controller Highly integrated solution and small form factor flat panel controller solution • Integrated 256x18 palette • Direct support for Dual or Single Scan panel • Separate address and data buses • Single clock source • ...

Page 2

Product Overview The 65510 VGA flat panel controller provides a very low power consumption, minimum chip-count, minimum-board space, low-cost graphics solution for inexpensive notebook, sub-notebook, handheld and pen-based portable PCs and word processors. The 65510 only requires a single 256Kx16 ...

Page 3

65510 Flat Panel VGA Controller Data Sheet December 1992 R Y ® ...

Page 4

Copyright Notice Copyright © 1992 Chips and Technologies, Inc. ALL RIGHTS RESERVED. This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language or computer language, ...

Page 5

Highly integrated Flat Panel controller • Separate Address and Data buses • Direct support for Dual or Single Scan panels • Single clock source • 100-pin package n Single 256Kx16 DRAM provides two-chip VGA subsystem n Innovative clock ...

Page 6

Revision Date By 0 0.2 3/92 ST 0.3 3/92 SV 0.4 4/92 ST 0.41 5/92 SV 0.5 6/92 SV/DH 0.6 8/92 DH/SV/JS Fixed 256Kx16 DRAM Pinouts in Application Schematics 0.7 10/92 SV Revision 0.7 Revision History Comment ...

Page 7

Section Introduction ..................................................... Minimum Chip Count / Board Space .......... Display Memory Interface ...................... Clock Selection ....................................... Clock Doubling ....................................... Mixed Voltage Operation ............................ Advanced Power Management.................... Normal Operating Mode ......................... Panel Off Mode ....................................... Standby Mode ......................................... CPU ...

Page 8

Figure System Diagram .............................................. Panel Power Sequencing ................................. T-Package Pinouts........................................... 15 F-Package Pinouts ........................................... 17 Application Schematic Examples ISA/EISA 16-bit Bus ................................... 110 ISA/EISA 16-bit Bus with Extra Drive ....... 111 ISA/EISA 8-bit Bus (for PC/Chip).............. 112 Micro Channel ...

Page 9

The 65510 VGA flat panel controller provides a very low power consumption, minimum-chip- count/board-space, low-cost graphics solution for inexpensive notebook, sub-notebook, hand-held, and pen-based portable PCs and word processors. The 65510 requires only a single 256Kx16 DRAM and single ...

Page 10

... The internal logic and memory power plane is represented by pins 38 and 88 (VCCM) on F65510, the bus power plane by pin 13 (VCCB) on F65510 and the display power plane by pin 63 (VCCD) on F65510. The 65510 provides "mixed" voltage operation where the different power planes may each be run at 3 ...

Page 11

... XR6C bit CPU ACTIVITY INDICATOR In the ISA bus configuration, the 65510 provides an output pin called ACTIND (pin 49 on F65510) to facilitate an orderly powerdown sequence. Therefore, Standby ACTIND output is an active high signal which is ...

Page 12

CRT monitors, the 65510 provides several proprietary features to maximize display quality on monochrome flat panels. Registers, the 65510 provides the flexibility to interface to a wide range of flat panels and provide full compatibility transparently to application ...

Page 13

For example, text mode vertical compensation consists of four priority order options: n Double Scanning+Line Insertion, Double Scanning, Line Insertion n Double Scanning+Line Insertion, Double Scanning n Double Scanning+Tall Scanning, Tall Fonts n Double Scanning+Tall Fonts, Tall Fonts, Double ...

Page 14

FULL COMPATIBILITY The 65510 is fully compatible with the IBM™ VGA standard at the hardware, register, and BIOS level. The 65510 also provides enhanced backward compatibility to EGA™, CGA™, Hercules™, and MDA™ standards without using NMIs. This con- troller ...

Page 15

ICT (In-Circuit Test) Mode In this mode, all pins of the 65510 chip may be tested individually to determine if they are properly connected. The 65510 will enter ICT mode if it sees a rising edge on CLKIN during ...

Page 16

... VGARD signal to control the direction of the transceiver. VGARD may be generated instead of ENAVDD (pin 50 on F65510) by pulling MA3 low. The state of MA4 determines whether clock doubling is enabled. MA2 and MA5-7 are reserved for future use. All eight bits are latched into an extension register on RESET so software may determine the hardware configuration ...

Page 17

... CHIPS offers the BIOS as a standard production version, a customized version source code. PACKAGE The 65510 is available in a 100-pin plastic flat pack: n F65510 - QFP with 0.65 mm (25 mil) lead pitch In the future, the 65510 will also be offered in a smaller, fine-lead-pitch package: n T65510 - QFP with 0 ...

Page 18

Revision 0.7 14 Introduction Preliminary 65510 ...

Page 19

MA0 GND MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 (Memory & Internal Logic) VCCM MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 GND STNDBY/ RESET CLKIN [CMD/] <LCLK> {PCMD/} IORD/ [SETUP/] <LDEV/> {Reserved} IOWR/ Revision 0.7 ...

Page 20

Pin Name A00 <BLE/> A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 (VGAHI) {VGACS/} ACDCLK (M) (DE) ACTIND [ADL/] {PSTART/} <ADS/> AEN [MIO/] {MIO/} <MIO/> BHE/ [BHE/] {BHE/} ...

Page 21

... F65510 Pinout (Standard QFP) MD14 81 MD13 82 MD12 83 MD11 84 MD10 85 MD9 86 (ICTENA1/) MD8 87 (TSENA1/) VCCM 88 (For Memory MD7 89 & Internal Logic) MD6 90 MD5 91 MD4 92 VGA Controller MD3 93 MD2 94 (ICTENA0/) MD1 95 MD0 96 (TSENA0/) GND 97 STNDBY/ 98 RESET 99 CLKIN 100 Revision 0.7 F65510 Flat Panel ...

Page 22

... LP MA0 (CFG0) (LB/) MA1 (CFG1) (MC/) MA2 (CFG2) MA3 (CFG3) (XCV/) MA4 (CFG4) (CD/) MA5 (CFG5) MA6 (CFG6) MA7 (CFG7) MA8 Revision 0.7 F65510 Pin List Pin # Dir Drive Pin Name MD0 (TSENA0 MD1 (ICTENA0 MD2 MD3 ...

Page 23

PIN DESCRIPTIONS T F Pin # Pin # Pin Name ...

Page 24

PIN DESCRIPTIONS T F Pin # Pin # Pin Name 43 45 RFSH/ {DISA/} [DISA/] <DISA/> BHE/ {BHE/} [BHE/] <BHE/> AEN {MIO/} [MIO/] <MIO/> ACTIND {PSTART/} [ADL/] <ADS/> IORD/ {CMD/} [PCMD/] ...

Page 25

PIN DESCRIPTIONS T F Pin # Pin # Pin Name 76 78 MA0 (CFG0) (LB MA1 (CFG1) (MC/) Out 74 76 MA2 (CFG2 MA3 (CFG3) (XCV/) Out 72 74 MA4 (CFG4) (CD MA5 ...

Page 26

PIN DESCRIPTIONS T F Pin # Pin # Pin Name (LD0 (LD1 (LD2 (LD3 (UD0 (UD1 (UD2) 53 ...

Page 27

PIN DESCRIPTIONS T F Pin # Pin # Pin Name 98 100 CLKIN 96 98 STNDBY VCCB 36 38 VCCM 61 63 VCCD 86 88 VCCM 2 4 GND 20 22 GND 52 54 GND 77 79 ...

Page 28

Revision 0.7 24 Preliminary 65510 ...

Page 29

Port Address Read 102 Global Enable (ISA/MC) 3B0 Reserved for MDA/Hercules 3B1 Reserved for MDA/Hercules 3B2 Reserved for MDA/Hercules 3B3 Reserved for MDA/Hercules 3B4 CRTC Index 3B5 CRTC Data 3B6 Reserved for MDA/Hercules 3B7 Reserved for MDA/Hercules 3B8 Hercules ...

Page 30

REGISTER SUMMARY - CGA, MDA, AND HERCULES MODEs Register Register Name ST00 (STAT) Display Status CLPEN Clear Light Pen Flip Flop SLPEN Set Light Pen Flip Flop MODE CGA/MDA/Hercules Mode Control COLOR CGA Color Select HCFG Hercules Configuration RX, ...

Page 31

REGISTER SUMMARY - INDEXED REGISTERS (VGA) Register Register Name SRX Sequencer Index SR0 Reset SR1 Clocking Mode SR2 Plane Mask SR3 Character Map Select SR4 Memory Mode SR7 Reset Horizontal Character Counter CRX CRTC Index CR0 Horizontal Total CR1 ...

Page 32

EXTENSION REGISTER SUMMARY: 00-2F Reg Register Name XRX Extension Index Register XR00 Chip Version XR01 Configuration XR02 CPU Interface Control XR03 -reserved- (ROM Interface) -- XR04 Memory Control XR05 -reserved- (Clock Control) -- XR06 Color Palette Control (DRAM Intfc) ...

Page 33

EXTENSION REGISTER SUMMARY: 30-5F Reg Register Name XR30 (Graphics Cursor Start Address High) XR31 (Graphics Cursor Start Address Low) XR32 (Graphics Cursor End Address) XR33 (Graphics Cursor X Position High) XR34 (Graphics Cursor X Position Low) XR35 (Graphics Cursor ...

Page 34

EXTENSION REGISTER SUMMARY: 60-7F Reg Register Name XR60 Blink Rate Control XR61 SmartMap™ Control XR62 SmartMap™ Shift Parameter XR63 SmartMap™ Color Mapping Control7 XR64 FP Alternate Vertical Total XR65 FP Alternate Overflow XR66 FP Alternate Vertical Sync Start XR67 ...

Page 35

GLOBAL CONTROL (SETUP) REGISTERS The Setup Control Register and Video Subsystem Enable registers are used to enable or disable the VGA. The Setup Control register is also used to place the VGA in normal or setup mode (the Global ...

Page 36

Controller Registers handle internal color lookup table mapping, text/graphics mode, overscan color, and color plane enable. The horizontal Pixel Panning and Pixel Padding Registers control pixel attributes on screen. Color palette registers ...

Page 37

Global Control (Setup) Registers Register Mnemonic Register Name SETUP Setup Control VSE Video Subsystem Enable ENAB Global Enable SETUP CONTROL REGISTER (SETUP) Write only at I/O Address 46E8h Reserved VGA Enable ...

Page 38

GLOBAL ENABLE REGISTER (ENAB) Read/Write at I/O Address 102h VGA Sleep Reserved This register is only accessible in Setup Mode (enabled by register 46E8 in ISA bus configurations or by the ...

Page 39

General Control & Status Registers Register Mnemonic Register Name ST00 Input Status 0 ST01 Input Status 1 FCR Feature Control MSR Miscellaneous Output INPUT STATUS REGISTER 0 (ST00) Read only at I/O Address at 3C2h ...

Page 40

FEATURE CONTROL REGISTER (FCR) Write at I/O Address 3BAh/3DAh Read at I/O Address 3CAh Group 5 Protection Feature Control Reserved Vsync Control Reserved 1-0 Feature Control These bits are used internal ...

Page 41

Register Mnemonic Register Name MODE CGA/Hercules Mode COLOR CGA Color Select HCFG Hercules Configuration CGA / HERCULES MODE CONTROL REGISTER (MODE) Read/Write at I/O Address 3B8h/3D8h Hi-Res Text Graphics Mode Monochrome ...

Page 42

CGA COLOR SELECT REGISTER (COLOR) Read/Write at I/O Address 3D9h Color bit-0 (Blue) Color bit-1 (Green) Color bit-2 (Red) Color bit-3 (Intensity) Intensity Enable Color Set Select Reserved This register is ...

Page 43

HERCULES CONFIGURATION REGISTER (HCFG) Write only at I/O Address 3BFh Enable Graphics Mode Enable Memory Page 1 Reserved This register is effective only in Hercules mode accessible in Hercules ...

Page 44

Revision 0.7 40 Preliminary 65510 ...

Page 45

Register Mnemonic Register Name SRX Sequencer Index SR00 Reset SR01 Clocking Mode SR02 Plane/Map Mask SR03 Character Font SR04 Memory Mode SR07 Horizontal Character Counter Reset SEQUENCER INDEX REGISTER (SRX) Read/Write at I/O Address 3C4h ...

Page 46

SEQUENCER CLOCKING MODE REGISTER (SR01) Read/Write at I/O Address 3C5h Index 01h Group 1 Protection 8/9 Dot Clocks Reserved Shift Load Input Clock Divide Shift 4 Screen Off Reserved 0 8/9 ...

Page 47

CHARACTER FONT SELECT REGISTER (SR03) Read/Write at I/O Address 3C5h Index 03h Group 1 Protection Font Select B bit-1 Font Select B bit-2 Font Select A bit-1 Font Select A bit-2 ...

Page 48

SEQUENCER MEMORY MODE REGISTER (SR04) Read/Write at I/O Address 3C5h Index 04h Group 1 Protection Reserved Extended Memory Odd/Even Mode Quad Four Mode Reserved 0 Reserved (0) 1 Extended Memory 0 ...

Page 49

Register Mnemonic Register Name CRX CRTC Index CR00 Horizontal Total CR01 Horizontal Display Enable End CR02 Horizontal Blank Start CR03 Horizontal Blank End CR04 Horizontal Sync Start CR05 Horizontal Sync End CR06 Vertical Total CR07 Overflow CR08 Preset Row ...

Page 50

CRTC INDEX REGISTER (CRX) Read/Write at I/O Address 3B4h/3D4h CRTC Index Reserved 5-0 CRTC data register index 7-6 Reserved (0) HORIZONTAL TOTAL REGISTER (CR00) Read/Write at I/O Address 3B5h/3D5h Index 00h ...

Page 51

HORIZONTAL BLANK START REGISTER (CR02) Read/Write at I/O Address 3B5h/3D5h Index 02h Group 0 Protection Blank Start This register is used for all VGA and EGA modes also ...

Page 52

HORIZONTAL SYNC START REGISTER (CR04) Read/Write at I/O Address 3B5h/3D5h Index 04h Group 0 Protection Horizontal Sync Start This register is used for all VGA and EGA modes also ...

Page 53

VERTICAL TOTAL REGISTER (CR06) Read/Write at I/O Address 3B5h/3D5h Index 06h Group 0 Protection Total (Scan Lines) This register is used in all modes. 7-0 Vertical Total These are the ...

Page 54

PRESET ROW SCAN REGISTER (CR08) Read/Write at I/O Address 3B5h/3D5h Index 08h Group 3 Protection Start Row Scan Count Byte Panning Control Reserved 4-0 Start Row Scan Count These bits specify ...

Page 55

CURSOR START SCAN LINE REGISTER (CR0A) Read/Write at I/O Address 3B5h/3D5h Index 0Ah Group 2 Protection Cursor Start Scan Line Cursor off Reserved 4-0 Cursor Start Scan Line These bits specify ...

Page 56

START ADDRESS HIGH REGISTER (CR0C) Read/Write at I/O Address 3B5h/3D5h Index 0Ch Display Start Address High 7-0 Display Start Address High This register contains the upper 8 bits of the display ...

Page 57

LIGHTPEN HIGH REGISTER (CR10) Read only at I/O Address 3B5h/3D5h Index 10h Read-only Register loaded at line compare (the light pen flip-flop is not implemented). Effective only in MDA and Hercules modes or when CR03 bit LIGHTPEN ...

Page 58

VERTICAL DISPLAY ENABLE END REGISTER (CR12) Read/Write at I/O Address 3B5h/3D5h Index 12h Group 4 Protection Display Enable End 7-0 Vertical Display Enable End These are the eight low order ...

Page 59

VERTICAL BLANK START REGISTER (CR15) Read/Write at I/O Address 3B5h/3D5h Index 15h Group 4 Protection Blank Start (Lower 8 bits) This register is used in all modes. 7-0 Vertical Blank ...

Page 60

CRT MODE CONTROL REGISTER (CR17) Read/Write at I/O Address 3B5h/3D5h Index 17h Group 3 Protection for bits 0, 1, and 3-7 Group 4 Protection for bit Compatibility Mode Select Row ...

Page 61

Display memory addresses are affected by CR17 bit 6 as shown in the table below: Logical Physical Memory Address Memory Byte Word Address Mode Mode MA00 A00 Note 1 MA01 A01 A00 MA02 A02 A01 MA03 A03 A02 MA04 ...

Page 62

MEMORY DATA LATCH REGISTER (CR22) Read only at I/O Address 3B5h/3D5h Index 22h Data Latch n Bit 7 Data Latch n Bit 6 Data Latch n Bit 5 Data Latch n ...

Page 63

Register Mnemonic Register Name GRX Graphics Index GR00 Set/Reset GR01 Enable Set/Reset GR02 Color Compare GR03 Data Rotate GR04 Read Map Select GR05 Graphics mode GR06 Miscellaneous GR07 Color Don't Care GR08 Bit Mask GRAPHICS CONTROLLER INDEX REGISTER (GRX) ...

Page 64

ENABLE SET/RESET REGISTER (GR01) Read/Write at I/O Address 3CFh Index 01h Group 1 Protection Enable Set/Reset Bit 0 Enable Set/Reset Bit 1 Enable Set/Reset Bit 2 Enable Set/Reset Bit 3 Reserved ...

Page 65

DATA ROTATE REGISTER (GR03) Read/Write at I/O Address 3CFh Index 03h Group 1 Protection Rotate Count 0 Rotate Count 1 Rotate Count 2 Function Select Reserved 2-0 Data Rotate Count These ...

Page 66

GRAPHICS MODE REGISTER (GR05) Read/Write at I/O Address 3CFh Index 05h Group 1 Protection Write Mode Reserved Read Mode Odd/Even Mode Shift Register Mode Reserved 1-0 Write Mode For 16-bit writes, ...

Page 67

Odd/Even Mode 0 All CPU addresses sequentially access all planes 1 Even CPU addresses access planes 0 and 2, while odd CPU addresses access planes 1 and 3. This option is useful for compatibility with the IBM CGA ...

Page 68

MISCELLANEOUS REGISTER (GR06) Read/Write at I/O Address 3CFh Index 06h Group 1 Protection Graphics/Text Mode Chain Odd/Even Planes Memory Map Mode Reserved 0 Graphics/Text Mode 0 Text Mode 1 Graphics mode ...

Page 69

BIT MASK REGISTER (GR08) Read/Write at I/O Address 3CFh Index 08h Group 1 Protection Bit Mask 0=Immune to change 1=Change permitted 7-0 Bit Mask This bit mask is applicable to any ...

Page 70

Revision 0.7 Graphics Controller Registers 66 Preliminary 65510 ...

Page 71

Attribute Controller and VGA Color Palette Registers Register Mnemonic Register Name ARX Attribute Index (for 3C0/3C1h) AR00-AR0F Attribute Controller Color Data AR10 Mode Control AR11 Overscan Color AR12 Color Plane Enable AR13 Horizontal Pixel Panning AR14 Pixel Pad DACMASK ...

Page 72

ATTRIBUTE CONTROLLER COLOR REGISTERS (AR00-AR0F) Read at I/O Address 3C1h Write at I/O Address 3C0/1h Index 00-0Fh Group 1 Protection or XR63 bit Blue Green Red Secondary Blue Secondary Green Secondary ...

Page 73

OVERSCAN COLOR REGISTER (AR11) Read at I/O Address 3C1h Write at I/O Address 3C0/1h Index 11H Group 1 Protection Overscan Color 7-0 Overscan Color These 8 bits define the overscan (border) ...

Page 74

ATTRIBUTE CONTROLLER HORIZONTAL PIXEL PANNING REGISTER (AR13) Read at I/O Address 3C1h Write At I/O Address 3C0/1h Index 13h Group 1 Protection Horizontal Pixel Panning Reserved 3-0 Horizontal Pixel Panning These ...

Page 75

COLOR PALETTE PIXEL MASK REGISTER (DACMASK) Read/Write at I/O Address 3C6h Group 6 Protection Pixel Mask Bit-0 Pixel Mask Bit-1 Pixel Mask Bit-2 Pixel Mask Bit-3 Pixel Mask Bit-4 Pixel Mask ...

Page 76

COLOR PALETTE READ-MODE INDEX REGISTER (DACRX) Write only at I/O Address 3C7h Group 6 Protection COLOR PALETTE INDEX REGISTER (DACX) Read/Write at I/O Address 3C8h Group 6 Protection Color Palette Index ...

Page 77

Register Register Mnemonic Group Extension Register Name XRX -- Extension Index XR00 Misc Chip Version XR01 Misc Configuration XR02 Misc CPU Interface XR04 Misc Memory Control XR06 Misc Palette Control XR0D Misc Auxiliary Offset XR0E Misc Text Mode Control ...

Page 78

EXTENSION INDEX REGISTER (XRX) Read/Write at I/O Address 3B6h/3D6h Index to Extension Registers Reserved 6-0 Index value used to access the extension registers 7 Reserved (0) Revision 0.7 CHIPS VERSION REGISTER ...

Page 79

... CPU Memory Access 0 8-bit CPU memory access (default) 1 16-bit CPU memory access 1 Interrupt Select Control 0 Pin 49 (T65510) or Pin 51 (F65510) outputs ENAVEE Signal (default) 1 Pin 49 (T65510) or Pin 51 (F65510) outputs IRQ Signal 2 Reserved 4-3 Attribute Controller Mapping 00 Write Index and Data at 3C0h. (8-bit ...

Page 80

MEMORY CONTROL REGISTER (XR04) Read/Write at I/O Address 3B7h/3D7h Index 04h Reserved Memory Wraparound Ctrl Reserved Control Signal Generation Write Buffer Enable Reserved Reserved 1-0 Reserved (Must be programmed to 01) ...

Page 81

CPU PAGING REGISTER (XR0B) Read/Write at I/O Address 3B7h/3D7h Index 0Bh Memory Mapping Mode Single/Dual Map CPU Address divide by 4 Reserved Linear Addressing Reserved 0 Memory Mapping Mode 0 Normal ...

Page 82

AUXILIARY OFFSET REGISTER (XR0D) Read/Write at I/O Address 3B7h/3D7h Index 0Dh Lsb of Offset (CR13) Lsb of Alt Offset (XR1E) Reserved 0 Offset Register LSB This bit provides finer granularity to ...

Page 83

SINGLE/LOW MAP REGISTER (XR10) Read/Write at I/O Address 3B7h/3D7h Index 10h Single or Lower Map Base address bits 19-12 This register effects CPU memory address mapping. 7-0 Single / Low Map ...

Page 84

EMULATION MODE REGISTER (XR14) Read/Write at I/O Address 3B7h/3D7h Index 14h Emulation Mode Herc Config (read only) DE Status Mode V Retrace Status Mode Vsync Status Mode Interrupt Polarity 1-0 Emulation ...

Page 85

WRITE PROTECT REGISTER (XR15) Read/Write at I/O Address 3B7h/3D7h Index 15h Protect Group 1 regs Wr Protect Group 2 regs Wr Protect Group 3 regs Wr Protect Group 4 regs ...

Page 86

FP HORIZONTAL DISPLAY END REGISTER (XR18) Read/Write at I/O Address 3B7h/3D7h Index 18h Alternate H Display End 7-0 Horizontal Display End This register specifies the number of characters displayed per scan ...

Page 87

FP HORIZONTAL SYNC END REGISTER (XR1A) Read/Write at I/O Address 3B7h/3D7h Index 1Ah Sync End Reserved 4-0 Horizontal Sync End Lower 5 bits of the character clock count which ...

Page 88

FP HORIZONTAL BLANK START / HORIZONTAL PANEL SIZE REGISTER (XR1C) Read/Write at I/O Address 3B7h/3D7h Index 1Ch Blank Start (Horizontal Panel Size) The value in this register is the Horizontal ...

Page 89

OFFSET REGISTER (XR1E) Read/Write at I/O Address 3B7h/3D7h Index 1Eh Display Buffer Width 7-0 Offset Value See CR13 for description Programmed Value = Actual Value – 1 Revision 0.7 VIRTUAL EGA ...

Page 90

MAXIMUM SCANLINE REGISTER (XR24) Read/Write at I/O Address 3B7h/3D7h Index 24h Max Scanlines Reserved This register is used in text modes when TallFont is enabled during vertical compensation. 4-0 Alternate Maximum ...

Page 91

... FRC logic. 3 CPU Activity Indicator This bit controls the enabling of CPU activity indicator or ERMEN/ functionality on pin 49 (F65510) or pin 47 (T65510). 0 CPU Activity indicator is enabled on pin 49 (F65510) or pin 47 (T65510) (default). 1 ERMEN/ functionality is enabled on pin 49 (F65510) or pin 47 (T65510). ...

Page 92

DEFAULT VIDEO REGISTER (XR2B) Read/Write at I/O Address 3B7h/3D7h Index 2Bh Color displayed when screen is blanked This register affects all modes when the screen is not blanked and XR28 bit-2 ...

Page 93

FP HSYNC (LP) DELAY REGISTER (XR2D) Read/Write at I/O Address 3B7h/3D7h Index 2Dh Delay (graphics mode horizontal compression disabled ) This register is used only in flat panel mode when ...

Page 94

SOFTWARE FLAGS REGISTER (XR44) Read/Write at I/O Address 3B7h/3D7h Index 44h Flag 0 Flag 1 Flag 2 Flag 3 Flag 4 Flag 5 Flag 6 Flag 7 This register contains eight ...

Page 95

PANEL FORMAT REGISTER (XR50) Read/Write at I/O Address 3B7h/3D7h Index 50h Frame Rate Control Dither Enable Clock Divide PWM / FRC Control 1-0 Frame Rate Control (FRC) If bit-6 of this ...

Page 96

DISPLAY TYPE REGISTER (XR51) Read/Write at I/O Address 3B7h/3D7h Index 51h Panel Type Reserved Reserved Video Skew Shift Clock Mask Enable FP Compensation LP During V Blank 1-0 Panel Type (PT) ...

Page 97

... M Signal Control This signal controls the output on pin 63 (T65510) or pin 65 (F65510), whether it is the M signal to the panel or BLANK/ signal to the panel 0 Pin 63 (T65510) or pin 65 (F65510) outputs M Signal (ACDCLK) 1 Pin 63 (T65510) or pin 65 (F65510) outputs BLANK/ signal 7 Reserved 93 Extension Registers Reserved Reserved ...

Page 98

FP INTERFACE REGISTER (XR54) Read/Write at I/O Address 3B7h/3D7h Index 54h Blank Polarity FP Blank Select Clock Divide Reserved FP LP Polarity FP FLM Polarity 0 FP Blank Polarity This ...

Page 99

FP HORIZONTAL COMPENSATION REGISTER (XR55) Read/Write at I/O Address 3B7h/3D7h Index 55h Ena H Compensation Ena H Auto Centering Reserved Reserved Ena Auto H Doubling Reformatter Control Reserved This register is ...

Page 100

HORIZONTAL CENTERING REGISTER (XR56) Read/Write at I/O Address 3B7h/3D7h Left Border This register is used only when non-automatic horizontal centering is enabled. 7-0 Horizontal Left Border (HLB) Programmed Value (in character ...

Page 101

VERTICAL COMPENSATION REGISTER (XR57) Read/Write at I/O Address 3B7h/3D7h Index 57h Enable V Compensation Enable Auto V Centering Enable Text V Stretching Text V Stretch Method Enable Gr V Stretching Gr ...

Page 102

VERTICAL CENTERING REGISTER (XR58) Read/Write at I/O Address 3B7h/3D7h Index 58h Top Border LSBs This register is used only when non-automatic vertical centering is enabled. 7-0 Vertical Top Border LSBs (VTB7-0) ...

Page 103

VERTICAL LINE REPLICATION REGISTER (XR5A) Read/Write at I/O Address 3B7h/3D7h Index 5Ah Line Replication Height Reserved This register is used in text or graphics modes when vertical line replication is enabled. ...

Page 104

ACDCLK CONTROL REGISTER (XR5E) Read/Write at I/O Address 3B7h/3D7h Index 5Eh ACDCLK Count ACDCLK Control This register is used to control the duty cycle of the ACDCLK (M) signal to the ...

Page 105

SMARTMAP™ CONTROL REGISTER (XR61) Read/Write at I/O Address 3B7h/3D7h Index 61h SmartMap™ Enable SmartMap™ Threshold SmartMap™ Saturation Text Enhancement Text Video Output Polarity This register is used in text modes only. ...

Page 106

SMARTMAP™ SHIFT PARAMETER REGISTER (XR62) Read/Write at I/O Address 3B7h/3D7h Index 62h Foreground Shift Background Shift This register is used in text mode when SmartMap is enabled (XR61 bit-0 = 1). ...

Page 107

FP VERTICAL TOTAL REGISTER (XR64) Read/Write at I/O Address 3B7h/3D7h Index 64h Vertical Total This register is used in all modes. 7-0 FP Alternate Vertical Total The contents of this ...

Page 108

FP VERTICAL SYNC START REGISTER (XR66) Read/Write at I/O Address 3B7h/3D7h Index 66h Alternate VSync Start This register is used in all modes. 7-0 FP Alternate Vertical Sync Start The ...

Page 109

... Bus Interface Output Drive Memory Intfc Output Drive Reserved This register is used to control the output drive of the bus, video, and memory interface pins. Please refer to the T65510 and F65510 pin list tables for normal drive values for all outputs. 0 Input Voltage Level Selection 0 V for internal logic is 3 ...

Page 110

SETUP / DISABLE CONTROL REGISTER (XR70) Read/Write at I/O Address 3B7h/3D7h Index 70h Reserved (0) 3C3/46E8 Register Disable 6-0 Reserved (0) 7 3C3 / 46E8 Register Disable 0 In the MC ...

Page 111

CGA / HERCULES COLOR SELECT REGISTER (XR7E) Read/Write at I/O Address 3B7h/3D7h Index 7Eh Color bit-0 (Blue) Color bit-1 (Green) Color bit-2 (Red) Color bit-3 (Intensity) Intensity Enable Color Set Select ...

Page 112

Revision 0.7 108 Preliminary 65510 ...

Page 113

... DRAMs have self-refresh capability so allow the 65510 and all clock inputs to be shut down during standby mode). Note: The circuits in this section assume the use of the F65510 (rectangular 100-pin flat pack with 0.65 mm lead pitch). The pinouts of the T65510 (square 100-pin flat pack with 0.50 mm lead pitch) are different (the pinouts are rotated clockwise by two pins relative to the 'F' package pinouts) ...

Page 114

... D08 C11 GND = B1, B10,B31,D18 D07 A02 D06 A03 D05 A04 D04 A05 D03 A06 D02 A07 D01 A08 D00 A09 Circuit Example - F65510 Interface to 16-Bit ISA Bus Revision 0.7 100 25-50 MHz Reference Clock CLKIN 98 STNDBY/ 99 RESET 45 RFSH/ 44 BHE/ 46 AEN 49 100pF n/c ACTIND [ADL/] ...

Page 115

... Note: If IRQ is used, ENAVEE functionality is lost! F65510 Note: the 'T' package pinouts are [A19] (VGAHI) {VGACS/} [A18] [A17] [A16] [A15] [A14] [A13] [A12] [A11] [A10] [A9] [A8] [A7] [A6] [A5] ...

Page 116

... Note: If IRQ is used, ENAVEE functionality is lost! F65510 Note: the 'T' package pinouts are different from the 'F' package pinouts! [A19] (VGAHI) {VGACS/} [A18] [A17] [A16] [A15] [A14] [A13] [A12] [A11] [A10] [A9] ...

Page 117

... Note: the ENAVEE functionality is not available in the Micro Chanel Interface configuration F65510 Note: the 'T' package pinouts are different from the 'F' package pinouts! [A19] (VGAHI) {VGACS/} [A18] [A17] [A16] [A15] [A14] [A13] [A12] ...

Page 118

... MEMR/ [S1/] {PRD/} <RD/> RDY [RDY] {PRDY/} <LRDY/> IRQ [DS16/] {IRQ} <IRQ/> (ENAVEE) Note: If IRQ is used, ENAVEE functionality is lost! F65510 Note: the 'T' package pinouts are different from the 'F' package pinouts! A19 [A19] (VGAHI) {VGACS/} A18 [A18] A17 [A17] A16 [A16] A15 [A15] A14 ...

Page 119

... MEMR/ [S1/] {PRD/} <RD/> 3 RDY [RDY] {PRDY/} <LRDY/> 51 IRQ [DS16/] {IRQ} <IRQ/> (ENAVEE) Note: If IRQ is used, ENAVEE functionality is lost! F65510 Note: the 'T' package pinouts are different from the 'F' package pinouts! 43 A19 [A19] (VGAHI) {VGACS/} 42 A18 [A18] 41 A17 [A17] 40 A16 [A16] 39 A15 ...

Page 120

... Note: the 'T' package pinouts are different from the 'F' package pinouts! (ICTENA1/) (TSENA1/) F65510 (ICTENA0/) (TSENA0/) (CFG7) (CFG6) (CFG5) (CD/) (CFG4) (XCV/) (CFG3) (CFG2) (MC/) (CFG1) (LB/) (CFG0) (CAS/) (WEL/) (WEH/) Circuit Example - 65510 Display Memory (One 256Kx16 DRAM) Note: 1.5K pulldown resistors may also be connected to selected MA (memory address) outputs above to select various configuration options ...

Page 121

... Note: the 'T' package pinouts are different from the 'F' package pinouts! 80 MD15 81 MD14 82 MD13 83 MD12 84 MD11 85 MD10 86 (ICTENA1/) MD9 87 (TSENA1/) MD8 89 MD7 90 MD6 91 MD5 F65510 92 MD4 93 MD3 94 MD2 95 (ICTENA0/) MD1 96 (TSENA0/) MD0 70 MA8 71 (CFG7) MA7 72 (CFG6) MA6 73 (CFG5) MA5 74 (CD/) (CFG4) ...

Page 122

... P6 60 (LD2) (LD2 (LD3) (LD3 (UD0) (UD0 (UD1) (UD1 (UD2) (UD2 (UD3) (UD3) P0 Circuit Example - F65510 Panel Interface 118 Application Schematic Examples ENAVEE J1-4 ENAVDD J1-2 SHFCLK J1-9 ACDCLK J1-1 LP J1-5 FLM J1-3 PNL7 J1-19 PNL6 J1-21 PNL5 J1-23 PNL4 J1-25 PNL3 J1-11 PNL2 J1-13 PNL1 ...

Page 123

This section includes schematic examples showing how to connect the 65510 to various flat panel displays. Monochrome Panels Manufacturer Part Number 1) Epson EG-9005F-LS 2) Citizen G6481L-FF 3) Sharp LM64P80 4) Sanyo LCM-6494-24NAC 5) Hitachi LMG5162XUFC Revision 0.7 Flat ...

Page 124

DK65510 J1 = 26-Pin Connector J1-9 J1-1 J1-5 J1-3 J1-19 J1-21 J1-23 J1-25 J1-11 J1-13 J1-15 J1-17 J1-7 J1-14 J1-16 J1-18 J1-20 J1-22 J1-24 J1-26 J1-6 J1-8 J1-10 J1-12 65510 Interface - Epson EG-9005F-LS (640x480 Monochrome LCD DD Panel) ...

Page 125

DK65510 J1 = 26-Pin Connector J1-9 J1-1 J1-5 J1-3 J1-19 J1-21 J1-23 J1-25 J1-11 J1-13 J1-15 J1-17 J1-7 J1-14 J1-16 J1-18 J1-20 J1-22 J1-24 J1-26 J1-6 J1-8 J1-10 J1-12 65510 Interface - Citizen G6481L-FF (640X480 Monochrome LCD-DD Panel) Revision ...

Page 126

DK65510 J1 = 26-Pin Connector J1-9 J1-1 J1-5 J1-3 J1-19 J1-21 J1-23 J1-25 J1-11 J1-13 J1-15 J1-17 J1-7 J1-14 J1-16 J1-18 J1-20 J1-22 J1-24 J1-26 J1-6 J1-8 J1-10 J1-12 65510 Interface - Sharp LM64P80 (640x480 Monochrome LCD DD Panel) ...

Page 127

DK65510 J1 = 26-Pin Connector J1-9 J1-1 J1-5 J1-3 J1-19 J1-21 J1-23 J1-25 J1-11 J1-13 J1-15 J1-17 J1-7 J1-14 J1-16 J1-18 J1-20 J1-22 J1-24 J1-26 J1-6 J1-8 J1-10 J1-12 65510 Interface - Sanyo LCM-6494-24NAC (640x480 Monochrome LCD DD Panel) ...

Page 128

DK65510 J1 = 26-Pin Connector J1-9 J1-1 J1-5 J1-3 J1-19 J1-21 J1-23 J1-25 J1-11 J1-13 J1-15 J1-17 J1-7 J1-14 J1-16 J1-18 J1-20 J1-22 J1-24 J1-26 J1-6 J1-8 J1-10 J1-12 65510 Interface - Hitachi LMG5162XUFC (640x480 Monochrome LCD DD Panel) ...

Page 129

The 65510 is the most flexible flat panel graphics controller available, enabling the widest possible range of panel interfaces. This section includes timing diagrams for the following configurations: - Monochrome, Single Drive, 1 pixel/clock - Monochrome, Single Drive, 2 ...

Page 130

DCLK SHFCLK P0 (1, DCLK SHFCLK P0 (2,1) P1 (1, Panel Timing - Single Drive (1 & 2 Pixels / Clock) These timing diagrams show the ...

Page 131

DCLK SHFCLK DCLK SHFCLK Panel Timing - Single Drive (4 & 8 Pixels / Clock) These timing diagrams show the 65510 outputs to ...

Page 132

DCLK SHFCLK (1,1)-1 P3 (1,1)-2 P4 (1,1)-4 P5 (1,1)- DCLK SHFCLK P0 (1,1)-1 P1 (1,1)-2 P2 (1,1)-4 P3 (1,1)-8 P4 (2,1)-1 P5 (2,1)-2 P6 (2,1)-4 P7 (2,1)-8 Panel Timing - Single Drive (1 & ...

Page 133

DCLK SHFCLK This timing diagram shows the 65510 outputs for a double drive monochrome panel with an eight pixels-per- shift-clock interface where the shift clock frequency equals the dot clock frequency ...

Page 134

Revision 0.7 130 Flat Panel Timing Preliminary 65510 ...

Page 135

This section shows detailed timing diagrams for the 65510 outputting data and control sequences to a variety of panel types. The 65510 is a highly configurable controller which can interface to virtually all existing monochrome LCD, EL, and Plasma ...

Page 136

LP SHFCLK 160 Clks /H FLM (1,1)......(640,1) P0-7 (1,241).(640,241) SHFCLK (1,1) (5,1) P0 (2,1) (6,1) P1 (3,1) (7,1) P2 (4,1) (8,1) P3 (1,241) (5,241) P4 (2,241) (6,241) P5 (3,241) (7,241) P6 (4,241) (8,241) P7 Revision 0.7 (1,2)......(640,2) (1,242).(640,242) 240 ...

Page 137

SHFCLK 160 Clks /H FLM (1,1).... (1,241)... P0-7 (640,1) (640,241) SHFCLK P3 (4,1) (8,1) P2 (3,1) (7,1) P1 (2,1) (6,1) P0 (1,1) (5,1) Revision 0.7 (1,2)... (1,242)... (640,2) (640,242) 480 data transfer cycles /V (636,241) (640,241) ...

Page 138

LP BLANK/ SHFCLK 320 Clks /H FLM P0-7 (1,1).........(640,1) SHFCLK (1,1) (3, (1,1) (3, (1,1) (3, (1,1) (3, (2,1) (4, (2,1) (4,1) -2 ...

Page 139

LP BLANK/ SHFCLK 320 Clks /H FLM P0-7 (1,1).........(640,1) SHFCLK (1,1) (3, (1,1) (3, (1,1) (3, (1,1) (3, (2,1) (4, (2,1) (4,1) -2 ...

Page 140

Revision 0.7 136 Flat Panel Pixel Timing Preliminary 65510 ...

Page 141

ABSOLUTE MAXIMUM CONDITIONS Symbol Parameter P Power Dissipation D V Supply Voltage CC V Input Voltage I V Output Voltage O T Operating Temperature (Ambient Storage Temperature STG Note: Permanent device damage may occur if Absolute Maximum ...

Page 142

DC CHARACTERISTICS Symbol Parameter I Power Supply Current 0°C, 5.5V, 50 MHz Clk CC I Power Supply Current 0°C, 3.3V, 40 MHz Clk CC I Power Supply Current 0°C, 5.5V, Standby CCS I Power Supply Current 0°C, 3.3V, Standby ...

Page 143

AC TIMING CHARACTERISTICS - CLOCK TIMING Symbol Parameter T CLK Period C T CLK Period C T CLK High Time CH T CLK Low Time CL T Clock Rise / Fall RF CLKIN AC TIMING CHARACTERISTICS - RESET TIMING ...

Page 144

FOR REFERENCE ONLY: BUS TIMING CHARACTERISTICS Symbol Parameter T Address Latch Pulse Width ADL T Delay from Start of Cycle to Command Strobe CD T Delay from Address Valid to Command Strobe CDM T Command Strobe Pulse Width (Asynchronous ...

Page 145

Unlatched (LA) Addresses & Status† Latched (SA) Addresses (& BHE/ on the PC) IOCS16/ (PC) CSFB/ (MC), DS16/ (MC) MEMCS16/ (PC) ALE (PC only, non-DMA cycles) (high for DMA & master cycles) ADL/ (MC), PSTART/ (PI) CMD/, IORD/, IOWR/, ...

Page 146

AC TIMING CHARACTERISTICS - BUS TIMING Symbol Parameter T Command Strobe Pulse Width CPW T Command Strobe Pulse Width CPW T Command Strobe Hold from Ready CHR T Command Strobe Inactive to Next Strobe NXT T Address Setup to ...

Page 147

A0-19, Status (PC Status: RFSH/, AEN) (MCStatus: S0/, S1/, MIO/) (PI Status: RD/, MIO/) Command Strobe (PC I/O: IORD/, IOWR/) (PC Mem: MEMR/, MEMW/) (MC & PI: CMD/) CSFB/ (MC) ADL/ (MC), PSTART/ (PI) PALRD/, PALWR/ (PC I/O) RDY ...

Page 148

AC TIMING CHARACTERISTICS - DRAM TIMING Symbol Parameter T Read/Write Cycle Time RC T RAS/ Pulse Width RAS T RAS/ Precharge RP T CAS/ to RAS/ precharge CRP T CAS/ Hold from RAS/ CSH T RAS/ to CAS/ delay ...

Page 149

RAS CRP RCD CAS ASR RAH Address Row T RAD T WS WE/ DATA Note: The above diagram represents a typical page mode write cycle. The number of actual CAS cycles may vary between 0 ...

Page 150

RAS CRP RCD CAS ASR RAH Address Row WE/ HIGH Z DATA Note: The above diagram represents a typical page mode read cycle. The number of actual CAS cycles may vary. The maximum number of ...

Page 151

AC TIMING CHARACTERISTICS - REFRESH TIMING Symbol Parameter Notes T RAS to CAS delay MHz CHR T CAS to RAS delay 5Tm = 88.3 ns (56 MHz) or 100 ns (50MHz) CSR T RAS ...

Page 152

AC TIMING CHARACTERISTICS - PANEL TIMING Symbol Parameter T CLKIN to SHFCLK delay (5V CLKIN to SHFCLK delay (3.3V Panel data setup to SHFCLK SPN T Panel data hold to SHFCLK HPN T FLM, LP, ...

Page 153

... Lead Width 0.20 ±0.07 (0.008 ±0.003) Lead Length See Note 3 Pin 1 Date Code † Actual lead pitch is 0.5mm (approximately 19.7mils) for the 'T' package Mechanical Specifications - F65510 (25† mil Lead Pitch) Lead Pitch 0.65 (0.0256) Lead Width 0.3 ±0.10 (0.012 ±0.004) Lead Length 1.2 ±0.2 (0.047 ± ...

Page 154

Chips and Technologies, Inc. 3050 Zanker Road San Jose, California 95134 Phone: 408-434-0600 Telex: 272929 CHIPS UR FAX: 408-434-6452 Title: 65510 Flat Panel VGA Controller Data Sheet Publication No.: DS161.1 Stock No.: 010161-002 Revision No.: 0.7 ...

Related keywords