MB86964 Fujitsu, MB86964 Datasheet
MB86964
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MB86964 Summary of contents
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... LED indicators. The twisted pair receive threshold can be reduced to allow an extended range between nodes in low-noise environments. Its wide range of features makes the MB86964 the ideal device for 10BASE T twisted-pair Ethernet applications. - ...
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... Dual-function pins have their alternate function en- closed in parentheses, e.g., RDY(RDY). Whenever a signal is separated into numbered bits, e.g., BD7, BD6, BD5, BD4, BD3, BD2, BD1 and BD0, the family of bits may also be shown collectively, e.g., as BD<7:0>. MB86964 SQFP100 FTP-100P-M05 TOP VIEW Figure 1. MB86964 Pin Assignments 2 75 TPIN 74 TPIP 73 GND 72 ...
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... I tions. BUS HIGH ENABLE: Active low. This pin is the byte/word control line used only when the MB86964 is configured for a 16-bit data bus by the SB/SW I bit, DLCR6<5>. It allows word, upper byte only or lower byte only transfers. Address pin SA0 is used with BHE for byte or word transfers as follows: ...
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... CLKI: Input for an external 20MHz clock source TYPE BUFFER MEMORY DATA BUS: Data lines between the SRAM buffer I/O memory and the MB86964. BUFFER MEMORY ADDRESS BUS: These lines address kbytes of O buffer memory. BUFFER RAM CHIP SELECT: Active low signal that is the chip select for the O buffer memory ...
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... Figure block diagram illustrating use of the MB86964 in an embedded Ethernet adapter application. One or two 8-bit bi- directional transceivers (if required) provide data buffering be- tween the MB86964 and the 8- or 16-bit system bus. A single kbyte SRAM implements the local packet buffer. The MB86964 provides interfaces to 100- or 150-ohm twisted pair (10BASE-T) as well as direct AUI capability (10BASE5) ...
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... DATA SYSTEM BUS SYSTEM CONTROLS SYSTEM ADDRESS MB86964 CLKO CLKI 20 MHz 20 pF Figure 4. Crystal Oscillator Connection MB86964 DATA TRANSCEIVER CHIP SELECT 20 MHz CRYSTAL ADDRESS DECODER Figure 3. Typical Application, Block Diagram CRYSTAL OSCILLATOR The clock rate of 10 Mbits/s specified by the international LAN ...
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... See Buffer Access section for information on how the host ac- cesses the buffer memory. POWER DOWN MODE When the MB86964 is not in use, the power down feature re- duces power consumption by shutting off all internal clocks. This feature is invoked by first setting the DLC_EN bit, DLCR6< ...
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... FIFOs are dedicated to each direction of data transfer. Writing to the transmit buffer can be inter- leaved with reading from the receive buffer, with the MB86964 automatically maintaining buffer memory pointers, thus re- lieving the host of that task. The Buffer Memory port register pair is at address 08H when DLCR7< ...
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... BMPR13<1:0>, set the maximum number of data transfer cycles (bytes or words single bus acquisition 12. When it is ready to begin, the MB86964 asserts its DMA Request output, DREQ. The host responds by asserting DMA Acknowledge, DMACK, followed by the Read Strobe, RD. ...
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... The MB86964 uses a dedicated buffer memory, organized as shown in Figure 5, for intermediate storage of packets to be transmitted, and of packets received from the network. The MB86964 can operate with kilobytes of total buffer memory, including both transmit and receive spaces. Memory partitioning into transmit and receive sections is controlled by the system software ...
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... Destination ID, Source ID, Length, and Data fields of the pack- et. It does not include the Preamble and CRC fields which are generated by the MB86964 as it transmits the packet, and there- fore are not stored in the buffer. 11 ...
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... A status bit in one of the MB86964’s internal registers informs the host when one or more packets are resident in the receive buffer and available to be read. The host retrieves these packets from the buffer memory by successive reads of BMPR8 ...
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... When DLCR5<5>, the ACPT BAD PKTS bit, is set to a ’0’ (disabled), detection of a bad incoming packet causes the MB86964 to release the buffer space in which that packet is contained and to reset its internal pointers use that space for the next incoming packet. If this bit is set to a ’1’, a packet with a CRC or alignment error will be accepted and the ap- propriate error bits in the status field of its header will be set ...
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... During the last one-third of the IPG, the MB86964 ignores the occurrence of a carrier indication, in accordance with 8802-3, to ensure fairness and equality in access to the network. Thus, if one station begins transmission slightly ahead of another, there is no advantage to the earlier start ...
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... Time domain reflectometry (TDR) allows esti- mates of the distance along the network cable from the node to the fault. The MB86964 is equipped with a special counter to perform the TDR function. The contents of the counter after any trans- mission can be determined by reading the Time Domain Re- flectometry registers, DLCR14 (the least-significant byte) and DLCR15 (the most-significant byte) ...
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... Destination Address field, which is the first data-bearing field following immediately after the Preamble. There are several control bits in the MB86964’s reg- isters which provide programmablility of the filter criteria. The contents of the Destination Address field can be of three basic types ...
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... The actual hashing function used in the MB86964 is to calcu- late the CRC on the multicast address and to store the most-sig- nificant six bits of this calculation in a register . The six bits are ...
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... Data transmitted by the transmitter is passed through the data encoder, internally looped back within the MB86964 before the TPO drivers to the data decoder and re- turned to the receiver. This local loopback function is disabled when a data collision occurs, clearing the received data circuit in the transceiver for the data arriving at the twisted-pair inputs ...
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... MB86964 enters a link-fail state and disables the transmit and automatic local loopback functions. The MB86964 ignores any link integrity pulse with an interval less than millisec- onds. The MB86964 remains in the link-fail state until it de- tects either a serial data packet or two or more link integrity pulses. ...
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... V CC 470 470 470 12 Suitable AUI transformers include Fil-Mag 23Z90, 23Z90SM and Valor LT6030. 2. Suitable 10BASE-T transformers include Fil-Mag 23Z128, 23Z128SM, Valor PT4069, Pulse Engineering PE–65745, PE–68048, and PE–65454. MB86964 CIP 84 CIN 85 DIP 76 DIN 77 DOP2 79 DOP1 78 87 LEDT DON2 81 DON1 80 ...
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... MB86964 CONTROL AND STATUS REGISTERS The control and status registers on the MB86964 are accessed through register addresses 00H through 0FH, and register bank-switching bits RBS1 and RBS0, DLCR7<3:2>. Table 3 summarizes the internal registers and their addresses. In 16-bit mode, even-numbered direct addresses select the registers. For example, address 00H accesses the Transmit and Receive Sta- tus registers simultaneously ...
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... MB86964 Table 3. Internal Register Address Map REGISTER BANK SYSTEM ADDRESS RBS1 RBS0 SA3 SA2 ...
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... MB86964 Table 4. Control and Status Bits, DLCR0-7 REGISTER BIT 7 TX STATUS TX DONE DLCR0 RX STATUS RX PKT DLCR1 TX INT ENABLE DONE DLCR2 INT EN RX INT ENABLE RX PKT DLCR3 INT EN TX MODE COL CTR DLCR4 3 RX MODE 0 DLCR5 CONFIG 0 DLCR6 DLC_EN CONFIG 1 DLCR7 CID 1 Table 5 ...
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... MB86964 Table 6. Control and Status Bits, DLCR8-15 REGISTER BIT 7 NODE DLCR8 NODE DLCR9 NODE DLCR10 NODE DLCR11 NODE DLCR12 NODE DLCR13 TDR 0 7 DLCR14 TDR 1 N/A DLCR15 (0) Table 7. Control and Status Bits, HT8-15 REGISTER BIT 7 HASH TABLE 0 ...
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... MB86964 Table 8. Status Bits, Packet Buffer Headers REGISTER BIT 7 TX LENGTH (LSB) 7 TPH1 TX LENGTH N/A (MSB) TPH2 (0) PKT STATUS N/A RPH1 (0) RESERVED N/A RPH2 (0) RXLENGTH (LSB) 7 RPH3 RXLENGTH N/A (MSB) RPH4 (0) NOTE: 1. Short Error will be set for packets whose stored length bytes. BIT 6 ...
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... Bits and 1 of this register, which can generate interrupts, are cleared by writing a ‘1’ to the bit. Writing ‘0’ to these bits has no effect. Only the MB86964 control logic can set these bits to high. Clearing the bit that causes an interrupt clears the bit and the interrupt ...
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... MB86964 RECEIVE STATUS REGISTER As shown in Table 10, this register contains eight status bits which can generate interrupts if enabled by the corresponding bit in DLCR3. Five of these bits report the status of the most recently received packet accepted for storage in the receive buffer. Bit 7, RX PKT, is set whenever a new packet is success- fully received and stored in the buffer ...
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... MB86964 TRANSMIT INTERRUPT ENABLE REGISTER As shown in Table 11, this register contains the bits that enable the status bits in DLCR0 to generate interrupts. Only bits and 1 can generate interrupts; the other interrupt enable bits are not used. Table 11. DLCR2 - Transmit Interrupt Enable Register ...
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... Normally DMA Request terminates after next-to-the-last cycle. LOOPBACK CONTROL: This bit controls encoder/decoder loopback function. A ‘0’ on this bit places MB86964 in internal loopback mode. ENABLE TRANSMIT DEFER: Program this bit low for normal network operation. When high, the transmitter will not defer to traffic on the network ...
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... MB86964 Table 15. Collision Count COLLISION 16 COL COUNT DLCR0<1> COL CTR3 COL CTR2 DLCR4<7> DLCR4<6> ...
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... Address Filter Mode bits AF1 and AF0 select the destination addresses for which the MB86964 will accept packets for pro- cessing. Table 17 provides additional information on the rela- tionship of the setting of these bits with other control bits and how they interact in terms of packet reception ...
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... MB86964 Table 17. Reception Destination Address Filtering AF1 AF0 LBC DLCR5 DLCR5 DLCR4 <1> <0> <1> AF1 AF0 LBC DLCR5 DLCR5 DLCR4 <1> <0> <1> ...
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... Refer to the System Interface section for additional information. DATA LINK CONTROL ENABLE : When low, enables MB86964 receiver and transmitter sections. This bit must be set high during initialization, and set low to enable loopback test- ing and operation on the network ...
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... CHIP IDENTIFICATION: A code which identifies this chip as the MB86964. POWER DOWN: When set high, enables power to the chip for all functions; when set low, places chip in power down mode for power conservation. ...
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... MB86964 BMPR9 is used only in word mode as the high byte of the word. In word mode, all transfers must be 16-bits wide, as the Buffer Memory Port register does not support byte-wide transfers in this mode. Odd–length packets are transferred to/from the buffer with an arbitrary ’pad byte at the end. All other registers can be accessed word-wide, high-byte-only or low-byte-only ...
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... MB86964 Table 22. Collision Action Codes Written to BMPR11 ACTION CODE 02H or 03H MODE SETUP: Halt after 16 collisions. COMMAND: Resume transmitting, repeat current packet. For use following a halt. Terminates the halt. 02H Instructs transmitter to resume transmitting, repeating the current packet. The collision counter is reset, allow- ing additional attempts to be made ...
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... MB86964 DMA BURST AND TRANSCEIVER MODE REGISTER Table 24 describes the DMA Burst and Transceiver Mode reg- ister, BMPR13, which selects the burst length for DMA opera- tion and programs the 10BASE-T transceiver modes. Burst Table 24. BMPR13 - DMA Burst and Transceiver Mode Register ...
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... BMPR14<5>. REMOTE SIGNALING: When high, indicates that the remote 10BASE-T port has remote function signaling compatible with that of the MB86964. When this is the case, the RLD and RJAB status is valid and is being continuously updated by the remote port. When this bit is low, RLD, and RJAB are meaningless. ...
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... MB86964 ELECTRICAL CHARACTERISTICS All specifications are valid over the Recommended Operating Conditions unless otherwise noted. OPERATIONAL SPECIFICATIONS Table 27. Absolute Maximum Ratings SYMBOL PARAMETER DESCRIPTION V Supply voltage CC V Input voltage IN V Output voltage OUT I Differential output current on DOP pins ODF V Input DC voltage on DIP and CIP ...
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... MB86964 Table 29. DC Specifications SYMBOL PARAMETER DESCRIPTION V Low-level input voltage IL V High-level input voltage IH V Low-level output voltage, SD<15:0> only OL1 V High-level output voltage, SD<15:0> only OH1 Low-level output voltage, all other digital V OL2 outputs High-level output voltage, all other digital V OH2 outputs ...
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... MB86964 Table 31. AUI Electrical Characteristics SYMBOL I Input low current Input high current Receiver input impedance DIP/DIN and CIP/CIN IN V Differential output voltage on DOP/DON common mode on DOP/DON ACCM V DC common mode on DOP/DON DCCM V Differential squelch threshold on DIP/DIN SQ V Differential common mode voltage on DIP/DIN CM 1. Values are and are used for design aid only ...
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... MB86964 Table 33. Jabber and Link Test Timing SYMBOL PARAMETER Jabber Maximum transmit time Timing Unjab time Link Test Time between link test pulses Timing Link loss timeout MINIMUM TYPICAL 20 250 MAXIMUM UNITS 150 ms 750 ...
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... MB86964 TIMING DIAGRAMS All specifications are valid over the Recommended Operating Conditions unless otherwise noted. Table 34. Read Cycle SA<3:0> RDY RDY SD<15:0> SYMBOL PARAMETER DESCRIPTION t SA<3:0> valid to RD low; CS low to RD low high to SA<3:0> invalid; RD high to CS high low pulse width. ...
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... MB86964 Table 35. Write Cycle SA<3:0> RDY RDY SD<15:0> SYMBOL PARAMETER DESCRIPTION t SA<3:0> valid to WR low; CS low to WR low high to SA<3:0> invalid; WR high to CS high low pulse width low to RDY low low to RDY high : 5 For registers and buffer port when port is ready before the write cycle begins ...
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... MB86964 Table 36. Single-cycle DMA Timing DREQ DMACK EOP RDY RDY SYMBOL PARAMETER DESCRIPTION t DMACK low to DREQ low 1 t DMACK high to DREQ high 2 t DMACK low low high to DMACK high low to EOP low 5 t EOP high to DMACK high ...
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... MB86964 Table 37. Burst DMA Timing DREQ DMACK RDY RDY SYMBOL PARAMETER DESCRIPTION low to DREQ low high to DMACK high 2 All of the asserted pulse must fall inside of the DMACK asserted pulse. The DMA cycle uses DMACK as the chip select. DMACK overrides SA< ...
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... MB86964 Table 38. Burst DMA terminated by EOP DREQ DMACK EOP SYMBOL PARAMETER DESCRIPTION t EOP low to DREQ low 1 t EOP high to DMACK high low to EOP low 3 Timing shown for EOP also applies to EOP when EOP(EOP) is programmed to be asserted high. Table 39. RESET Timing ...
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... MB86964 Table 40. Skip Packet Timing WR RD SYMBOL PARAMETER DESCRIPTION t Writing skip packet high to next Buffer Memory Port read 1 Table 41. INT Clear Timing WR INT NOTE: When writing a command to clear interrupt bit(s), the data transfer takes place after the rising edge of the write pulse. ...
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... MB86964 Table 42. SRAM Read Timing BA<14:0> BCS BOE BD<7:0> SYMBOL PARAMETER DESCRIPTION t Read cycle address access time BCS high to address invalid 3 t Address valid to BCS low chip select access time 5 AC, t BOE high to BCS high output enable access time ...
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... MB86964 Table 43. SRAM Write Timing BA<14:0> BCS BWE BD<7:0> SYMBOL PARAMETER DESCRIPTION t Write cycle 1 t Address valid to BCS low 2 t Address valid to BWE high 3 t BCS low to BWE high 4 t BCS high to address invalid 5 t BCS low to BWE low 6 t BWE Pulse Width ...
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... MB86964 PACKAGE INFORMATION 100-Pin Shrink Quad Flat Pack - FPT-100-M05 .630 .008 (16.00 75 (14.00 76 INDEX 100 1 LEAD No. .0197 (0.31) .050 (0.08) SQ .020) .004 SQ 51 0.10 “A” .003 .007 - .001 ) (0.18 + 0.08 – 0.03 .004 (0.10 .008 .059 - .004 (MOUNTING HEIGHT) (1. 0.20 –0.10 .591(15.00) .472(12.00) NOM REF + .002 .005 + - .001 (0 ...
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... MB86964 Worldwide Headquarters Worldwide Headq arters Japan Electronic Devices Tel: +81 44 754 3763 Fax:+81 44 754 3329 http://www.fujitsu.co.jp USA Tel:+1 408 922 9000 Fax:+1 408 922 9179 T el:+1 800 866 8608 Fax:+1 408 922 9179 http://www.fujitsumicro.com All Right Reserved. The information contained in this document has been carefully checked and is believed to be reliable. ...